All The Claims

1.-28. (canceled)
29. An electroluminescence generating device comprising:
a. a channel comprising at least one layer of an organic semiconductor material, said organic semiconductor material being a polycrystalline semiconductor-material, said channel being able to carry both types of charge carriers, said charge carriers being electrons and holes, said channel being realized by one layer of organic semiconductor or by several coplanar layers of organic semiconductors;
b. an electron electrode, said electron electrode being in contact with said channel and positioned on top of a first side of said channel layer or within said channel layer, said electron electrode being able to inject electrons in said channel layer;
c. a hole electrode, said hole electrode being spaced apart from said electron electrode, said hole electrode being in contact with said channel and positioned on top of a first side of said channel layer or within said channel layer, said hole electrode being able to inject holes in said channel, said electron electrode and said hole electrode being positioned in an horizontal plane along said channel;
d. a control electrode positioned on said first side or on a second side of said channel, said control electrode being suitable for controlling the charge injection, the current flow and the charge recombination between the electron electrode and the hole electrode;

whereby said electroluminescence generating device being able to emit light by applying an electrical potential difference between said electron electrode and said hole electrode, characterized in that at least one of said electron electrode and said hole electrode comprise at least one different material which is not comprised in the other one.
30. Device according to claim 29, further comprising a dielectric layer between said channel and said control electrode.
31. Device according to claim 30, wherein said dielectric layer comprises at least one material selected from the group consisting of silicon oxide, alumina, polyimide and polymethylmethacrylate.
32. Device according to claim 29, wherein said electron electrode comprises one or more elements selected from the group consisting of Au, Ca, Mg, Al, In, Perovskite Manganites (Re1-xAxMnO3).
33. Device according to claim 29, wherein said hole electrode comprises at least one material selected from the group consisting of Au, indium tin oxide, Cr, Cu, Fe, Ag, poly(3,4-ethylenedioxythiophene) combined with poly(styrene sulfonate), Perovskite Manganites (Re1-xAxMnO3).
34. Device according to claim 29, wherein said channel comprises at least one material selected from the group consisting of small molecule materials, polymers and metal complexes.
35. Device according to claim 34, wherein said channel comprises at least one material selected from the group consisting of tetracene, pentacene, perylenes, terthiophene, tetrathiophene, quinquethiophene, sexithiophene, bora-diazaindacene, polyphenylenevinylene, polyfluorene, polythiophene and porphyrins.
36. Device according to claim 29, wherein said poly-crystalline semiconductor material has a crystal grain size and said hole electrode and said electron electrode are spaced apart at a distance smaller than said crystal grain size.
37. Device according to claim 29, wherein said hole electrode and said electron electrode are spaced apart at a distance between 5 nm and 5 microns.
38. Device according to claim 29, wherein said electron electrode and said hole electrode have digitated structures comprising a regular repetition of a basic finger structure, and are positioned such that said basic finger structures of said basic finger structures of respectively hole and electron electrodes are alternating each other, and is characterised by two in-plane distances P and R between the basic finger structures.
39. Device according to claim 38 wherein said P and R are equal.
40. Device according to claim 29, wherein said control electrode is an injection control electrode, said injection control electrode being positioned on said second side of said channel whereby being suitable to facilitate the injection of charge carriers into said channel upon the application of an electrical potential difference between said control electrode and said hole electrode or an electron electrode.
41. Device according to claim 29, wherein said control electrode is a current control electrode, said current control electrode being positioned on said second side of said channel whereby being suitable for controlling the current of at least one type of charge carriers upon the application of an electrical potential difference between said control electrode and said electron andor hole electrode.
42. Device according to claim 29, wherein said channel is realized by several coplanar layers of organic semiconductors.
43. Device according to claim 29, further comprising optical confinement andor waveguiding layers on said first andor second side of said channel.
44. Device according to claim 29, further comprising optical resonating structures or cavities on said first andor second side of said channel.
45. Device according to claim 29, further comprising a flexible or rigid substrate.
46. A method for manufacturing a device according to claim 29, wherein said channel is formed by sublimation of small molecules.
47. Method according to claim 46, wherein said channel is formed by simultaneous sublimation of at least two moieties.
48. Method for manufacturing a device according to claim 29, wherein said channel is formed by solution processing of one or more soluble andor polymeric materials.
49. Method for manufacturing a device according to claim 29, wherein said channel is formed by a combination of sublimation and solution processing.
50. Method for manufacturing a device according to claim 29, wherein said channel is formed by thermal, chemical or physical treatment of pre-deposited organic semiconductors.
51. Method for manufacturing a device according to claim 29, wherein said channel is manufactured with printing techniques.
52. A method for generating electroluminescence using a device according to claim 29, by recombination of electrons and holes injected in said channel from said electron electrode and hole electrode.
53. Device according to claim 29, comprising at least two control electrodes.

The claims below are in addition to those above.
All refrences to claims which appear below refer to the numbering after this setence.

1. A plant of soybean variety 01045749, wherein a sample of seed of said variety has been deposited under ATCC Accession No. ______.
2. A plant part of the plant of claim 1, wherein the plant part comprises at least one cell of said plant.
3. The plant part of claim 2, further defined as pollen, a meristem, a cell, or an ovule.
4. A seed of soybean variety 01045749, wherein a sample of seed of said variety has been deposited under ATCC Accession No. ______.
5. A method of producing soybean seed, wherein the method comprises crossing the plant of claim 1 with itself or a second soybean plant.
6. The method of claim 5, wherein the method is further defined as comprising crossing the plant of soybean variety 01045749 with a second, distinct soybean plant to produce an F1 hybrid soybean seed.
7. An F1 hybrid soybean seed produced by the method of claim 6.
8. An F1 hybrid soybean plant produced by growing the seed of claim 7.
9. A composition comprising the seed of claim 4 comprised in plant seed growth media, wherein a sample of seed of said variety has been deposited under ATCC Accession No. ______.
10. The composition of claim 9, wherein the growth media is soil or a synthetic cultivation medium.
11. A plant produced by introducing a single locus conversion into soybean variety 01045749, or a selfed progeny thereof comprising the single locus conversion, wherein the single locus conversion was introduced into soybean variety 01045749 by backcrossing or genetic transformation and wherein a sample of seed of soybean variety 01045749 has been deposited under ATCC Accession No. ______.
12. The plant of claim 11, wherein the single locus conversion comprises a transgene.
13. A seed that produces the plant of claim 11.
14. The seed of claim 13, wherein the single locus confers a trait selected from the group consisting of male sterility, herbicide tolerance, insect resistance, pest resistance, disease resistance, modified fatty acid metabolism, abiotic stress resistance, altered seed amino acid composition, site-specific genetic recombination, and modified carbohydrate metabolism.
15. The seed of claim 13, wherein the single locus confers tolerance to an herbicide selected from the group consisting of glyphosate, sulfonylurea, imidazalinone, dicamba, glufosinate, phenoxy proprionic acid, cyclohexanedione, triazine, benzonitrile, PPO-inhibitor herbicides and broxynil.
16. The seed of claim 13, wherein the single locus conversion comprises a transgene.
17. The method of claim 6, wherein the method further comprises:
(a) crossing a plant grown from said F1 hybrid soybean seed with itself or a different soybean plant to produce a seed of a progeny plant of a subsequent generation;
(b) growing a progeny plant of a subsequent generation from said seed of a progeny plant of a subsequent generation and crossing the progeny plant of a subsequent generation with itself or a second plant to produce a progeny plant of a further subsequent generation; and
(c) repeating steps (a) and (b) using said progeny plant of a further subsequent generation from step (b) in place of the plant grown from said F1 hybrid soybean seed in step (a), wherein steps (a) and (b) are repeated with sufficient inbreeding to produce an inbred soybean plant derived from the soybean variety 01045749.
18. The method of claim 17, comprising crossing said inbred soybean plant derived from the soybean variety 01045749 with a plant of a different genotype to produce a seed of a hybrid soybean plant derived from the soybean variety 01045749.
19. A method of producing a commodity plant product comprising collecting the commodity plant product from the plant of claim 1.
20. The method of claim 19, wherein the commodity plant product is protein concentrate, protein isolate, grain, soybean hulls, meal, flour, or oil.
21. A soybean commodity plant product produced by the method of claim 20, wherein the commodity plant product comprises at least one cell of soybean variety 01045749.

1. A thin-film transistor liquid crystal display (TFT-LCD) driver circuit comprising:
a gate driver adaptable to manipulate the TFT;
a generator capable of providing grayscale voltage for display points;
a timing circuit configured to provide timing signals;
a bias circuit configured to provide bias voltage signals; and
a source driver operable to charge the display points according to the grayscale voltage, wherein the source driver includes:
a source drive latch configured to store data for the display points, the stored data capable of being decoded and converted by a digital to analog converter (DAC) to provide the grayscale voltage that need to be generated and provided to each display point; and
a source drive buffer having an operational power amplifier (OPA), the OPA having first and second differential amplifiers, the differential amplifiers capable of alternating operation according to the timing and bias voltage signals, wherein each differential amplifier, by voltage follower mechanism, is capable of inputting and outputting voltage signals from the DAC for charging the display points.
2. The circuit of claim 1, wherein the source drive buffer further includes a CMOS transmission gate in parallel with the OPA, wherein under control of the timing signals and while the OPA is inactive, the CMOS transmission gate is capable of adjusting the voltage output of the OPA using output signals from the DAC.
3. The circuit of claim 1, wherein the first differential amplifier includes:
a first differential circuit having two N-channel metal oxide semiconductor (NMOS), wherein the gate of the first NMOS is coupled to the output of the DAC and the gate of the second NMOS is coupled to the output of the OPA;
a first current mirror being a loader of the first differential circuit;
an end of current source;
an output level which includes a NMOS and a PMOS, the gate of the NMOS and the end of current source controlled by the bias voltage signals, the gate of the PMOS coupled to the output of the first current mirror; and
a power down PMOS operable to turning on and off the OPA by timing signals.
4. The circuit of claim 1, wherein the second differential amplifier includes:
a second differential circuit having two P-channel metal oxide semiconductor (PMOS), wherein the gate of the first PMOS is coupled to the output of the DAC while the gate of the second PMOS is coupled to the output of the OPA;
a second current mirror being a loader of the second differential circuit;
an end of current source;
an output level which includes a PMOS and a NMOS, the gate of the PMOS and the end of current source controlled by the bias voltage signals, the gate of the NMOS coupled to the output of the second current mirror; and
a power down NMOS which is applied for turning on and off OPA by timing signals.
5. The circuit of claim 1, wherein during sub-threshold zone the threshold voltage of the OPA is higher than the bias voltage generated by the bias voltage signals.
6. A liquid crystal display (LCD) device comprising:
a thin-film transistor (TFT) panel;
a TFT-LCD driver circuit comprising:
a gate driver adaptable to manipulate the TFT;
a generator capable of providing grayscale voltage for display points;
a timing circuit configured to provide timing signals;
a bias circuit configured to provide bias voltage signals; and
a source driver operable to charge the display points according to the grayscale voltage, wherein the source driver includes:
a source drive latch configured to store data for the display points, the stored data capable of being decoded and converted by a digital to analog converter (DAC) to provide the grayscale voltage that need to be generated and provided to each display point; and
a source drive buffer having an operational power amplifier (OPA), the OPA having first and second differential amplifiers, the differential amplifiers capable of alternating operation according to the timing and bias voltage signals, wherein each differential amplifier, by voltage follower mechanism, is capable of inputting and outputting voltage signals from the DAC for charging the display points.
7. The device of claim 6, wherein the source drive buffer further includes a CMOS transmission gate in parallel with the OPA, wherein under control of the timing signals and while the OPA is inactive, the CMOS transmission gate is capable of adjusting the voltage output of the OPA using output signals from the DAC.
8. The device of claim 6, wherein the first differential amplifier includes:
a first differential circuit having two N-channel metal oxide semiconductor (NMOS), wherein the gate of the first NMOS is coupled to the output of the DAC and the gate of the second NMOS is coupled to the output of the OPA;
a first current mirror being a loader of the first differential circuit;
an end of current source;
an output level which includes a NMOS and a PMOS, the gate of the NMOS and the end of current source controlled by the bias voltage signals, the gate of the PMOS coupled to the output of the first current mirror; and
a power down PMOS operable to turning on and off the OPA by timing signals.
9. The device of claim 6, wherein the second differential amplifier includes:
a second differential circuit having two P-channel metal oxide semiconductor (PMOS), wherein the gate of the first PMOS is coupled to the output of the DAC while the gate of the second PMOS is coupled to the output of the OPA;
a second current mirror being a loader of the second differential circuit;
an end of current source;
an output level which includes a PMOS and a NMOS, the gate of the PMOS and the end of current source controlled by the bias voltage signals, the gate of the NMOS coupled to the output of the second current mirror; and
a power down NMOS which is applied for turning on and off OPA by timing signals.
10. The device of claim 6, wherein during sub-threshold zone the threshold voltage of the OPA is higher than the bias voltage generated by the bias voltage signals.
11. A thin-film transistor liquid crystal display (TFT-LCD) driver circuit comprising:
a gate driver adaptable to manipulate the TFT;
a generator capable of providing grayscale voltage for display points;
a timing circuit configured to provide timing signals;
a bias circuit configured to provide bias voltage signals; and
a source driver operable to charge the display points according to the grayscale voltage, wherein the source driver includes:
a source drive latch configured to store data for the display points, the stored data capable of being decoded and converted by a digital to analog converter (DAC) to provide the grayscale voltage that need to be generated and provided to each display point; and
a source drive buffer having an operational power amplifier (OPA), the OPA having:
a first differential amplifier including:
a first differential circuit having two N-channel metal oxide semiconductor (NMOS), wherein the gate of the first NMOS is coupled to the output of the DAC and the gate of the second NMOS is coupled to the output of the OPA;
a first current mirror being a loader of the first differential circuit;
a first end of current source;
an output level which includes a third NMOS and a third PMOS, the gate of the third NMOS and the first end of current source controlled by the bias voltage signals, the gate of the third PMOS coupled to the output of the first current mirror;
a power down PMOS operable to turning on and off the OPA by timing signals;

a second differential amplifier including:
a second differential circuit having two P-channel metal oxide semiconductor (PMOS), wherein the gate of the first PMOS is coupled to the output of the DAC while the gate of the second PMOS is coupled to the output of the OPA;
a second current mirror being a loader of the second differential circuit;
a second end of current source;
an output level which includes a fourth PMOS and a fourth NMOS, the gate of the fourth PMOS and the end of current source controlled by the bias voltage signals, the gate of the fourth NMOS coupled to the output of the second current mirror;
a power down NMOS which is applied for turning on and off OPA by timing signals; and

wherein the two differential amplifiers are capable of alternating operation according to the timing and bias voltage signals, wherein each differential amplifier, by voltage follower mechanism, is capable of inputting and outputting voltage signals from the DAC for charging the display points.
12. The circuit of claim 11, wherein the source drive buffer further includes a CMOS transmission gate in parallel with the OPA, wherein under control of the timing signals and while the OPA is inactive, the CMOS transmission gate is capable of adjusting the voltage output of the OPA using output signals from the DAC.
13. The circuit of claim 11, wherein during sub-threshold zone the threshold voltage of the OPA is higher than the bias voltage generated by the bias voltage signals.

The claims below are in addition to those above.
All refrences to claims which appear below refer to the numbering after this setence.

1. A method, comprising:
forming a hard mask directly on an interlayer dielectric layer wherein said hard mask has a thickness greater than 10 nanometers and less than 30 nanometers and wherein said hard mask comprises titanium;
patterning said hard mask;
etching said interlayer dielectric layer, wherein said etching forms a partial via that leaves a portion of said interlayer dielectric layer in said partial via;
forming a trench before removing said hard mask including:
further patterning said hard mask, and
etching said interlayer dielectric layer to form said trench and to completely remove said interlayer dielectric layer that remains in said partial via, wherein said trench and said via form a dual damascene structure; and, subsequently,

removing said hard mask during a post-etch clean with a wet etchant having a selectivity to etch said hard mask at a greater rate than said interlayer dielectric layer; and depositing a metal in said dual damascene structure to form an interconnect after removing said hard mask.