All The Claims

1. A method comprising:
obtaining network distance information including a compilation of network distance information provided by a plurality of service providers;
storing the network distance information in a network distance table;
receiving a request from a client for an identity of a peer providing content;
identifying a first peer and a second peer providing the content;
determining a first network distance between the first peer and the client and a second network distance between the second peer and the client;
determining that the first peer and the second peer are both distant potential peers to the client based on the first network distance and the second network distance not being included in the network distance table, wherein the distant potential peers have a network distance above a threshold;
utilizing the distant potential peers when no non-distant potential peers are identified; and
providing the identity of the first peer to the client.
2. The method of claim 1 wherein the network distance information is selected from a group consisting of network cost, bandwidth, number of hops, roundtrip time, and any combination thereof.
3. The method of claim 1 wherein providing includes providing a list of peers based on the network distance between the peers and the client.
4. The method of claim 3 wherein the list of peers is sorted by network distance for each peer.
5. The method of claim 1 further comprising:
obtaining policy information for first and second autonomous systems; and
storing the policy information for the first and second autonomous systems in the network distance table.
6. The method of claim 5 wherein the policy information includes a scaling factor for combining the compilation of network distance information provided by the service providers.
7. The method of claim 5 wherein the policy information indicates preferred routes between the autonomous systems.
8. A system comprising:
a memory including a network distance table having network distance information including a compilation of network distance information provided by a plurality of service providers; and
a processor configured to:
receive a request from a client for an identity of a peer providing content;
identify a first peer and a second peer providing the content;
determine a first network distance between the first peer and the client and a second network distance between the second peer and the client;
determine that the first peer and the second peer are both distant potential peers to the client based on the first network distance and the second network distance not being included in the network distance table, wherein the distant potential peers have a network distance above a threshold;
utilize the distant potential peers when no non-distant potential peers are identified; and
provide the identity of the first peer to the client.
9. The system of claim 8 wherein the network distance information is selected from a group consisting of network cost, bandwidth, number of hops, roundtrip time, and any combination thereof.
10. The system of claim 8 wherein the processor is configured to provide the identity by providing a list of peers based on the network distance between the peers and the client.
11. The system of claim 10 wherein the list of peers is sorted by network distance of each peer.
12. The system of claim 8 wherein the memory further includes policy information for first and second autonomous systems.
13. The system of claim 12 wherein the policy information includes a scaling factor for combining the compilation of network distance information provided by the service providers.
14. The system of claim 12 wherein the policy information indicating preferred routes between the autonomous systems.
15. An apparatus comprising:
a processor; and
a memory having instructions to manipulate the processor, the instructions comprising:
instructions to obtain network distance information including a compilation of network distance information provided by a plurality of service providers;
instructions to store the network distance information in a network distance table;
instructions to identify a first peer and a second peer providing content;
instructions to determine a first network distance between the first peer and the client and a second network distance between the second peer and the client;
instructions to determine that the first peer and the second peer are both distant potential peers to the client based on the first network distance and the second network distance not being included in the network distance table, wherein the distant potential peers have a network distance above a threshold;
instructions to utilize the distant potential peers when no non-distant potential peers are identified;
instructions to send a request for content from the device to the first peer; and
instructions to receive the content at the device from the first peer.
16. The apparatus of claim 15 wherein the network distance information is selected from a group consisting of network cost, bandwidth, number of hops, roundtrip time, and any combination thereof.
17. The apparatus claim 16 wherein the network distance information includes the network distance from the first and second peers to the device.
18. The apparatus of claim 15 wherein the network distance information includes the network distance to the first and second peers from the device.
19. The apparatus of claim 15 wherein the plurality of instructions further comprise:
instructions to obtain policy information for first and second autonomous systems; and
instructions to store the policy information for the first and second autonomous systems in the network distance table.
20. The apparatus of claim 19 wherein the policy information includes a scaling factor for combining the compilation of network distance information provided by the service providers.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

What is claimed is:

1. A method of fabricating a semiconductor die on a wafer having a device layer, an etch-stop layer, and a primary handle layer, wherein the etch-stop layer is sandwiched between the device layer and the primary handle layer, the method comprising the steps of:
(a) etching a die release trench in the primary handle layer;
(b) etching a moving parts trench and die release trench in the device layer where the die trench in the device layer is aligned with the die release trench formed in the primary handle layer;
(c) affixing an additional handle layer to the primary handle layer;
(d) removing the etch-stop layer located between the die release trenches on the device and primary handle layers; and
(e) removing the additional handle layer to release the die.
2. The method of claim 1 wherein step (a) further comprises a step of etching a vacuum hole in the primary handle layer.
3. The method of claim 1 wherein step (c) further comprises applying a thermal release material to a surface of the additional handle layer that will come into contact with the primary handle layer.
4. The method of claim 3 wherein step (e) comprises heating the wafer.
5. The method of claim 1 wherein step (d) comprises exposing the wafer to hydrofluoric acid.
6. The method of claim 1 wherein step (a) further comprises a step of etching a stiction relief trench directly underneath the moving parts trench.
7. The method of claim 1, wherein step (b) comprises performing Deep Reactive Ion Etching (DRIE).
8. The method of claim 1 wherein step (a) is performed before step (b).
9. The method of claim 1 wherein step (c) is performed before step (d).
10. The method of claim 3 wherein the thermal release material is Revalpha.
11. A MEMS device formed in a wafer having a device layer, an etch-stop layer and a primary handle layer wherein the etch-stop layer is sandwiched between the device layer and the primary handle layer by the process of claim 1.
12. The MEMS device of claim 11 wherein the device layer and primary handle layer are silicon.
13. A method of fabricating a semiconductor die on a wafer having a device layer, an etch-stop layer, and a primary handle layer, wherein the etch-stop layer is sandwiched between the device layer and the primary handle layer, the method comprising the steps of:
(a) creating a die release trench in the primary handle layer;
(b) creating a die release trench in the device layer where the die trench in the device layer is aligned with the die release trench formed in the primary handle layer;
(c) affixing an additional handle layer to the primary handle layer;
(d) removing the etch-stop layer located between the die release trenches on the device and primary handle layers; and
(e) removing the additional handle layer to release the die.
14. The method of claim 13 wherein step (a) further comprises a step of etching a vacuum hole in the primary handle layer and step (b) further comprises a step of creating a moving parts trench in the device layer.
15. The method of claim 13 wherein step (c) further comprises applying a thermal release material to a surface of the additional handle layer that will come into contact with the primary handle layer.
16. The method of claim 13 wherein step (e) comprises heating the wafer.
17. The method of claim 13 wherein step (d) comprises exposing the wafer to hydrofluoric acid.
18. The method of claim 13 wherein step (a) further comprises a step of creating a stiction relief trench directly underneath the moving parts trench.
19. A MEMS device formed in a wafer having a device layer, an etch-stop layer and a primary handle layer wherein the etch-stop layer is sandwiched between the device layer and the primary handle layer by the process of claim 13.
20. The MEMS device of claim 19 wherein the device layer and primary handle layer are silicon.

1. An electronic apparatus that includes a semiconductor device and is capable of controlling a flow rate of air from a fan for cooling the semiconductor device, comprising:
a measurement unit configured to measure temperature characteristics indicative of a degree of increase in temperature of the semiconductor device; and
a control unit configured to control the fan to operate at a predetermined air flow rate in a case where a result of the temperature characteristics measurement by said measurement unit indicates a degree of increase in temperature not smaller than a predetermined reference value, and control the fan to operate at an air flow rate lower than the predetermined air flow rate in a case where the measurement result indicates a degree of increase in temperature smaller than the predetermined reference value.
2. The electronic apparatus according to claim 1, wherein said measurement unit measures the temperature characteristics based on a time period which elapses after a load is applied to the semiconductor device, and temperature of the semiconductor device which increases after the load starts to be applied to the semiconductor device.
3. The electronic apparatus according to claim 2, wherein said measurement unit measures the temperature characteristics, based on temperature of the semiconductor device measured when a predetermined time elapses after a load starts to be applied to the semiconductor device, by determining a rate of increase in the temperature.
4. The electronic apparatus according to claim 2, wherein said measurement unit measures the temperature characteristics by determining whether or not temperature of the semiconductor device increases to a predetermined temperature before a predetermined time elapses after a load starts to be applied to the semiconductor device.
5. The electronic apparatus according to claim 1, wherein said control unit controls the fan to operate at the predetermined air flow rate when temperature of the semiconductor device is not lower than a predetermined temperature, and also a result of the temperature characteristics measurement indicates a degree of increase in temperature not smaller than the predetermined reference value.
6. The electronic apparatus according to claim 1, wherein said control unit controls the fan to operate at the air flow rate lower than the predetermined air flow rate when temperature of the semiconductor device is lower than a predetermined temperature, or the result of the temperature characteristics measurement indicates a degree of increase in temperature smaller than the predetermined reference value.
7. The electronic apparatus according to claim 1, wherein said control unit acquires information on load on the semiconductor device, and controls the fan to operate at the predetermined air flow rate, when the load indicated by the acquired information is not lower than a predetermined load, and also the result of the temperature characteristics measurement indicates a degree of increase in temperature not smaller than the predetermined reference value.
8. The electronic apparatus according to claim 1, wherein said control unit acquires information on load on the semiconductor device, and controls the fan to operate at the air flow rate lower than the predetermined air flow rate, when the load indicated by the acquired information is lower than a predetermined load, or the measurement result indicates a degree of increase in temperature smaller than the predetermined reference value.
9. The electronic apparatus according to claim 7, wherein said control unit acquires the information on load on the semiconductor device from a tool for measuring load or from information concerning processing being executed.
10. The electronic apparatus according to claim 1, wherein said measurement unit measures the temperature characteristics at predetermined time intervals.
11. A method of controlling an electronic apparatus that includes a semiconductor device and is capable of controlling a flow rate of air from a fan for cooling the semiconductor device, comprising:
measuring temperature characteristics indicative of a degree of increase in temperature of the semiconductor device; and
controlling the fan to operate at a predetermined air flow rate in a case where a result of the temperature characteristics measurement by said measuring indicates a degree of increase in temperature not smaller than a predetermined reference value, and controlling the fan to operate at an air flow rate lower than the predetermined air flow rate in a case where the result of the temperature characteristics measurement indicates a degree of increase in temperature smaller than the predetermined reference value.
12. The method according to claim 11, wherein said measuring includes measuring the temperature characteristics based on a time period which elapses after a load is applied to the semiconductor device, and temperature of the semiconductor device which increases after the load starts to be applied to the semiconductor device.
13. The method according to claim 12, wherein said measuring includes measuring the temperature characteristics, based on temperature of the semiconductor device measured when a predetermined time elapses after a load starts to be applied to the semiconductor device, by determining a rate of increase in the temperature.
14. The method according to claim 12, wherein said measuring includes measuring the temperature characteristics by determining whether or not temperature of the semiconductor device increases to a predetermined temperature before a predetermined time elapses after a load starts to be applied to the semiconductor device.
15. The method according to claim 11, wherein said controlling includes controlling the fan to operate at the predetermined air flow rate when temperature of the semiconductor device is not lower than a predetermined temperature, and also a result of the temperature characteristics measurement indicates a degree of increase in temperature not smaller than the predetermined reference value.
16. The method according to claim 11, wherein said controlling includes controlling the fan to operate at the air flow rate lower than the predetermined air flow rate when temperature of the semiconductor device is lower than a predetermined temperature, or the result of the temperature characteristics measurement indicates a degree of increase in temperature smaller than the predetermined reference value.
17. The method according to claim 11, wherein said controlling includes acquiring information on load on the semiconductor device, and controlling the fan to operate at the predetermined air flow rate, when the load indicated by the acquired information is not lower than a predetermined load, and also the result of the temperature characteristics measurement indicates a degree of increase in temperature not smaller than the predetermined reference value.
18. The method according to claim 11, wherein said controlling includes acquiring information on load on the semiconductor device, and controlling the fan to operate at the air flow rate lower than the predetermined air flow rate, when the load indicated by the acquired information is lower than a predetermined load, or the result of the temperature characteristics measurement indicates a degree of increase in temperature smaller than the predetermined reference value.
19. The method according to claim 17, wherein said controlling includes acquiring the information on load on the semiconductor device from a tool for measuring load or from information concerning processing being executed.
20. The method according to claim 11, wherein said measuring includes measuring the temperature characteristics at predetermined time intervals.
21. A non-transitory computer-readable storage medium storing a computer-executable program for executing a method of controlling an electronic apparatus that includes a semiconductor device and is capable of controlling a flow rate of air from a fan for cooling the semiconductor device,
wherein the method comprises:
measuring temperature characteristics indicative of a degree of increase in temperature of the semiconductor device; and
controlling the fan to operate at a predetermined air flow rate in a case where a result of the temperature characteristics measurement by said measuring indicates a degree of increase in temperature not smaller than a predetermined reference value, and controlling the fan to operate at an air flow rate lower than the predetermined air flow rate in a case where the result of the temperature characteristics measurement indicates a degree of increase in temperature smaller than the predetermined reference value.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method of forming a photoconversion device comprising:
forming an oxide layer over a top surface of a substrate;
forming a three-dimensionally graded doped region of a first conductivity type below the oxide layer and at the top surface of the substrate;
forming a charge collection region below the oxide layer and located at least in part beneath the three-dimensionally graded doped surface region, the charge collection region being doped to a second conductivity type; and
providing a separation region of the substrate such that the three-dimensionally graded doped region of the substrate does not contact the charge collection region of the substrate.
2. The method of claim 1, wherein forming the three-dimensionally graded doped region comprises maintaining an undoped separation region between the three-dimensionally graded doped region and the charge collection region by controlling an implant angle for a dopant.
3. The method of claim 1, wherein at least one of the three-dimensionally graded doped region and charge collection region is formed using an angled implant.
4. The method of claim 2, wherein the three-dimensionally graded doped region comprises a first sub-region doped to a first dopant concentration and a second sub-region doped to a second dopant concentration.
5. The method of claim 1, wherein the act of forming the charge collection region includes forming a neck portion that extends to a transistor channel at the top surface of said substrate.
6. The method of claim 4, wherein said first and second sub-regions partially overlap.
7. The method of claim 4, wherein the second sub-region has a shallower doping profile than the first sub-region relative to the surface of the substrate.
8. A method of forming a photodiode structure comprising:
forming a three-dimensionally graded doped region of a first conductivity type; and
forming a charge collection doped region below the three-dimensionally graded doped region such that an undoped separation region is maintained between the three-dimensionally graded doped region and charge collection doped region such that the three-dimensionally graded doped region and the charge collection doped region are not in contact.
9. A method of forming a photodiode structure comprising:
forming a three-dimensionally graded doped region of a first conductivity type, wherein forming the three-dimensionally graded doped region comprises forming overlapping first and second sub-regions of different doping profiles, each being in contact with a top surface of the photodiode structure; and
forming a charge collection doped region below the three-dimensionally graded doped region such that an undoped separation region is maintained at least partially between the three-dimensionally graded doped region and charge collection doped region.
10. The method of claim 9, wherein forming the three-dimensionally graded doped region further comprises providing a highest dopant concentration at a top surface of the photodiode structure where the first and second sub-regions overlap.
11. The method of claim 9, wherein the second sub-region has a shallower doping profile than the first sub-region relative to the surface of the photodiode structure.
12. A method for forming an image pixel structure comprising:
forming a transistor gate stack on a substrate; and
forming a photodiode comprising a pinned surface region and a charge collection region, wherein the pinned surface region comprises a three-dimensionally graded doped portion and an undoped portion that are laterally offset from the transistor gate and the undoped portion prevents contact between the pinned surface region from the charge collection region.
13. The method of claim 12, wherein the doped portion comprises a first doped sub-region with a first dopant concentration and a second doped sub-region with a second dopant concentration.
14. The method of claim 12, wherein the undoped portion has the same dopant profile as the substrate below the charge collection region.
15. The method of claim 12, wherein forming the charge collection region comprises forming a neck portion that extends to and at least partially below the transistor gate.
16. The method of claim 13, wherein the second doped sub-region has a shallower doping profile than the first doped sub-region relative to a surface of the substrate.
17. The method of claim 12, wherein forming the doped region comprises laterally offsetting the doped region from the transistor gate by a distance La.
18. A method for forming an image pixel structure comprising:
forming a transistor gate stack on a substrate; and
forming a photodiode comprising a pinned surface region and a charge collection region, wherein the pinned surface region comprises doped and undoped portions that are laterally offset from the transistor gate, wherein forming the doped region comprises laterally offsetting the doped region from the transistor gate by a distance La, wherein the distance La is the transistor gate height multiplied by Tan \u03b8a, where \u03b8a is about 2 to about 30 degrees off an axis perpendicular to the substrate.
19. The method of claim 12, further comprising forming an oxide layer over the substrate, wherein forming the photodiode comprises implanting dopant through the oxide layer.
20. A method for forming an image pixel structure comprising:
forming a transistor gate stack on a substrate; and
forming a photodiode comprising a pinned surface region and a charge collection region, wherein the pinned surface region comprises doped and undoped portions that are laterally offset from the transistor gate, wherein the act of forming the doped portion of the pinned surface region comprises using an angled implant, wherein the angled implant is conducted at an angle from about 20 to about 30 degrees off an axis perpendicular to the substrate, the angled implant maintaining the undoped portion of the pinned surface region adjacent to the transistor gate.