All The Claims

1. A system comprising:
a memory;
a processor; and
an integrated circuit (IC) chip coupled to the memory and to the processor, the IC chip comprising:
a plurality of input-output (IO) cells;
a controller to exchange signals between the memory and the processor through the plurality of IO cells; and
a protocol sequence generator to generate test signals to test characteristics of the plurality of IO cells, wherein the protocol sequence generator generates the test signals based on at least one control signal.
2. The system as claimed in claim 1, wherein each of the plurality of IO cells is a dual data rate (DDR) IO cell.
3. The system as claimed in claim 1, wherein the protocol sequence generator generates the test signals based, at least in part, on an external clock signal.
4. The system as claimed in claim 1, wherein at least one of the test signals is selected from a group of a DDR clock signal, a data strobe signal, and a pre-defined number of bits of data signal.
5. The system as claimed in claim 1, wherein the protocol sequence generator simulates the test signals corresponding to a write cycle in the memory.
6. The system as claimed in claim 1, wherein the controller, in a normal mode of operation, generates controller data signals for the plurality of IO cells.
7. The system as claimed in claim 6 further comprising a switching unit to provide the controller data signals to the plurality of IO cells during the normal mode of operation and to provide the test signals to the plurality of IO cells during a test mode of operation.
8. An integrated circuit (IC) chip comprising:
a plurality of dual data rate (DDR) input-output (IO) cells; and
a DDR protocol sequence generator (DPSG) coupled to the DDR IO cells, the DPSG comprising,
a control unit to receive at least one control signal to generate at least one synchronized control signal, wherein the at least one synchronized control signal is synchronized with an external clock signal; and
a sequencing unit to receive the external clock signal and the at least one synchronized control signal to generate test signals.
9. The IC chip as claimed in claim 8, wherein the DPSG further comprises a data unit to generate write data signals for the test signals.
10. The IC chip as claimed in claim 9, wherein the data unit selects the write data signals, based on a data select signal, from internal data signals and external data signals.
11. The IC chip as claimed in claim 8, wherein the DPSG further comprises a clock generator to receive the external clock signal to generate a DDR clock signal having a frequency that is half the frequency of the external clock signal.
12. The IC chip as claimed in claim 8, wherein the IC chip further comprises a memory.
13. The IC chip as claimed in claim 8, wherein the control unit further comprises a counting unit to initiate a counter based on receiving the at least one synchronized control signal, wherein the counter generates counter signal bits to sequence the test signals.
14. The IC chip as claimed in claim 8, wherein the sequencing unit generates test signals comprising a DDR clock signal, a data strobe signal, and at least one bit of data signal.
15. A sequencing unit for sequencing test signals, the sequencing unit comprising:
a data sampler to sample write data signals and internal data enable signals at an edge of an external clock signal to generate at least one bit of a data signal and corresponding data enable signals; and
a data strobe sampler to sample an internal data strobe signal and an internal data strobe enable signal at an opposite edge of the external clock signal to generate a data strobe signal and corresponding data strobe enable signal.
16. The sequencing unit as claimed in claim 15, wherein the sequencing unit comprises a data strobe sequencing unit to determine, based on a data debug signal, a pre-defined number of the at least one bit of the data signal.
17. A method comprising:
receiving at least one control signal to generate, based on an external clock signal, a synchronized control signal; and
generating test signals to test characteristics of a plurality of input-output (IO) cells in an integrated circuit (IC) chip based on the synchronized control signal and the external clock signal.
18. The method as claimed in claim 17 further comprising generating the test signals corresponding to a write cycle in DDR SDRAM memory.
19. The method as claimed in claim 17 further comprising generating the test signals having a DDR clock signal, a data strobe signal, and a write enable signal.
20. The method as claimed in claim 19 further comprising edge aligning the DDR clock signal with the data strobe signal.
21. The method as claimed in claim 19 further comprising generating the test signals having at least one bit of data signal.
22. The method as claimed in claim 21 further comprising center aligning the data strobe signal with the at least one bit of data signal.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A system comprising:
a deposition system configured to deposit a solder outwardly from at least one substrate of a plurality of substrates; and
a plasmabonding system comprising:
a plasma system configured to plasma clean the at least one substrate; and
a bonding system configured to bond the plurality of substrates, the plasmabonding system configured to at least reduce reoxidation of the solder.
2. The system of claim 1, the plasmabonding system comprising:
a chamber in which the at least one substrate is plasma cleaned and the plurality of substrates are bonded.
3. The system of claim 1, the plasmabonding system comprising:
a plasma chamber in which the at least one substrate is plasma cleaned; and
a bonding chamber in which the plurality of substrates are bonded, the bonding chamber coupled to the plasma chamber.
4. The system of claim 1, the plasmabonding system comprising:
a plasma chamber in which the at least one substrate is plasma cleaned;
a bonding chamber in which the plurality of substrates are bonded; and
a load-lock module configured to couple the plasma chamber and the bonding chamber under a substantial vacuum.
5. The system of claim 1, the plasmabonding system comprising:
a vacuum chamber within which there is a substantial vacuum;
a plasma chamber disposed within the vacuum chamber and in which the at least one substrate is plasma cleaned; and
a bonding chamber disposed within the vacuum chamber and in which the plurality of substrates are bonded.
6. The system of claim 1, the plasmabonding system comprising:
a nitrogen chamber configured to use nitrogen gas to push oxygen gas outside of the nitrogen chamber;
a plasma chamber disposed within the nitrogen chamber and in which the at least one substrate is plasma cleaned; and
a bonding chamber disposed within the nitrogen chamber and in which the plurality of substrates are bonded.
7. The system of claim 1, the plasmabonding system configured to:
a vacuum chamber within which there is a substantial vacuum;
a plasma chamber disposed within the vacuum chamber and in which the at least one substrate is plasma cleaned;
a bonding chamber disposed within the vacuum chamber and in which the plurality of substrates are bonded; and
a module configured to couple the plasma chamber and the bonding chamber.
8. A method comprising:
depositing a solder outwardly from at least one substrate of a plurality of substrates;
plasma cleaning the at least one substrate;
at least reducing reoxidation of the solder; and
bonding the plurality of substrates.
9. The method of claim 8, the at least reducing reoxidation of the solder comprising:
plasma cleaning the at least one substrate in a chamber; and
bonding the plurality of substrates in the chamber.
10. The method of claim 8, the at least reducing reoxidation of the solder comprising:
plasma cleaning the at least one substrate in a plasma chamber; and
bonding the plurality of substrates in a bonding chamber coupled to the plasma chamber.
11. The method of claim 8, the at least reducing reoxidation of the solder comprising:
plasma cleaning the at least one substrate in a plasma chamber;
transporting the at least one substrate to a bonding chamber through a load-lock module coupling the plasma chamber and the bonding chamber under a substantial vacuum; and
bonding the plurality of substrates in the bonding chamber.
12. The method of claim 8, the at least reducing reoxidation of the solder comprising:
plasma cleaning the at least one substrate in a plasma chamber disposed within a vacuum chamber within which there is a substantial vacuum; and
bonding the plurality of substrates in a bonding chamber disposed within the vacuum chamber.
13. The method of claim 8, the at least reducing reoxidation of the solder comprising:
plasma cleaning the at least one substrate in a plasma chamber disposed within a nitrogen chamber configured to use nitrogen gas to push oxygen gas outside of the nitrogen chamber; and
bonding the plurality of substrates in a bonding chamber disposed within the nitrogen chamber.
14. A method comprising:
depositing solder outwardly from a first substrate;
removing metal oxide from the first substrate; and
depositing a capping layer outwardly from the first substrate to at least reduce reoxidation of the solder.
15. The method of claim 7, further comprising:
bonding the first substrate and a second substrate.
16. The method of claim 7, further comprising:
allowing the first substrate to be exposed to atmosphere prior to bonding the first substrate and a second substrate.
17. The method of claim 7, the capping layer comprising gold.
18. A system comprising:
a deposition system configured to deposit a solder outwardly from a first substrate; and
a plasmabonding system configured to:
remove metal oxide from the first substrate; and
deposit a capping layer outwardly from the first substrate to at least reduce reoxidation of the solder.
19. The system of claim 18, the plasmabonding system configured to:
bond the first substrate and a second substrate.
20. The system of claim 18, the plasmabonding system configured to:
allow the first substrate to be exposed to atmosphere prior to bonding the first substrate and a second substrate.

What is claimed is:

1. An image recognition apparatus comprising:
a transparent substrate;
a first recognition section disposed on the transparent substrate, the first recognition section receiving an image pattern from an object and generating a first recognition signal corresponding to the received image pattern; and
a second recognition section disposed on the transparent substrate adjacent to the first recognition section, the second recognition section sensing a biological signal from the object so as to check whether or not the first recognition signal is obtained from a human being.
2. The apparatus of claim 1, wherein the first recognition section is disposed on a center portion of the transparent substrate and the second recognition section is disposed on a peripheral area surrounding the first recognition section.
3. The apparatus of claim 2, wherein the first recognition section comprises an image recognition sensor that generates the first recognition signal corresponding to an amount of a reflecting light reflected from the image pattern, the amount of the reflecting light being differently reflected according to a position from which the reflecting light is reflected.
4. The apparatus of claim 3, wherein the image recognition sensor comprises:
a sensing TFT that outputs a voltage signal corresponding to the reflecting light reflected from the image pattern;
a storage capacitor that charges an electron charge corresponding to the voltage signal input from the sensing TFT; and
a switching TFT that outputs a voltage signal corresponding to the electron charge charged into the storage capacitor in response to a switching signal applied from an external.
5. The apparatus of claim 2, wherein the second recognition section comprises:
a first biological-signal recognition section disposed on a first end portion of the transparent substrate, which is adjacent to the first recognition section; and
a second biological-signal recognition section disposed on a second end portion of the transparent substrate, which is adjacent to the first recognition section and opposite to the first end portion.
6. The apparatus of claim 5, wherein the first and second biological-signal recognition sections comprise a capacitance type biological-signal recognition sensor that acts as a capacitor with the object having the image pattern.
7. The apparatus of claim 6, wherein the first and second biological-signal recognition sections act as a lower electrode of the capacitor and the object having the image pattern acts as an upper electrode of the capacitor.
8. The apparatus of claim 7, wherein the biological-signal recognition sensor comprises:
a first TFT that outputs a predetermined voltage signal;
a conductive sensing electrode that acts as the capacitor with the upper electrode, the conductive sensing electrode charging an electron charge corresponding to the predetermined voltage signal from the first TFT; and
a second TFT that outputs a voltage signal corresponding to the electron charge charged into the conductive sensing electrode.
9. The apparatus of claim 1, wherein the image pattern of the object comprises a fingerprint image obtained from the human being.
10. The apparatus of claim 1, wherein the object directly makes contact with the transparent substrate.
11. An image recognition apparatus comprising:
a plurality of sensing signal output lines disposed on a transparent substrate, extended in a first direction and arranged in a second direction substantially perpendicular to the first direction;
a plurality of gate lines disposed on the transparent substrate, extended in the second direction and arranged in the first direction;
a plurality of pixel areas defined by two sensing signal output lines adjacent to each other and two gate lines adjacent to each other;
a first recognition section formed on the pixel areas positioned at a center portion of the transparent substrate, the first recognition section receiving an image pattern from an object that makes contact with the transparent substrate and generating a first recognition signal;
a bias line extended in the first direction, arranged in the second direction and adjacent to the sensing signal output lines, the bias line applying a predetermined voltage signal to the first recognition section;
a gate-off line extended in the second direction, arranged in the first direction and adjacent to the gate lines, the gate-off line outputting a gate-off signal to the first recognition section; and
a second recognition section formed on the pixel areas adjacent to the first recognition section, the second recognition section sensing a biological signal from the object so as to check whether or not the first recognition signal is obtained from a human being.
12. The apparatus of claim 11, wherein the first recognition section comprises an image recognition sensor that generates the first recognition signal corresponding to an amount of a reflecting light reflected from the image pattern, the amount of the reflecting light being differently reflected according to a position from which the reflecting light is reflected.
13. The apparatus of claim 12, wherein the first recognition section comprises:
a sensing TFT that outputs a voltage signal corresponding to the reflecting light reflected from the image pattern;
a storage capacitor that charges an electron charge corresponding to the voltage signal input from the sensing TFT; and
a switching TFT that outputs a voltage signal corresponding to the electron charge charged into the storage capacitor in response to a switching signal applied from an external.
14. The apparatus of claim 13, wherein the sensing TFT comprises:
a drain electrode connected to the bias line;
a gate electrode connected to the gate-off line; and
a source electrode connected to the storage capacitor.
15. The apparatus of claim 13, wherein the switching TFT comprises:
a gate electrode connected to an adjacent gate line;
a drain electrode connected to an adjacent sensing signal output line; and
a source electrode connected to the storage capacitor.
16. The apparatus of claim 11, wherein the second recognition section comprises:
a first biological-signal recognition sensor disposed on a first end portion of the transparent substrate; and
a second biological-signal recognition sensor disposed on a second end portion of the transparent substrate, which is opposite to the first end portion.
17. The apparatus of claim 16, wherein the first and second biological-signal recognition sensors comprise a capacitance type biological-signal recognition sensor that acts as a capacitor with the object having the image pattern.
18. The apparatus of claim 17, wherein the first and second biological-signal recognition sensors act as a lower electrode of the capacitor and the object having the image pattern acts as a upper electrode of the capacitor.
19. The apparatus of claim 17, wherein the biological-signal recognition sensor comprises:
a first TFT that outputs a predetermined voltage signal;
a conductive sensing electrode that acts as the capacitor with the upper electrode, the conductive sensing electrode charging an electron charge corresponding to the predetermined voltage signal from the first TFT; and
a second TFT that outputs a voltage signal corresponding to the electron charge charged into the conductive sensing electrode.
20. The apparatus of claim 19, wherein the first TFT comprises:
a gate electrode connected to an adjacent gate line;
a drain electrode commonly connected to the gate line with the gate electrode; and
a source electrode connected to the conductive sensing electrode.
21. The apparatus of claim 19, wherein the second TFT comprises:
a gate electrode connected to an adjacent gate line;
a drain electrode connected to the sensing signal output line; and
a source electrode connected to the conductive sensing electrode.
22. The apparatus of claim 11, wherein the image pattern of the object comprises a fingerprint image obtained from the human being.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method of forming a dielectric layer pattern, comprising:
forming lower patterns on a substrate;
forming a first dielectric layer on sidewalls and upper surfaces of the lower patterns and a surface of the substrate;
forming a mask pattern on the first dielectric layer to partially expose the first dielectric layer;
partially removing the exposed first dielectric layer on upper surfaces and upper sidewalls of the lower patterns and depositing the removed first dielectric layer on surfaces of the first dielectric layer between the lower patterns, to form a second dielectric layer having a thickness greater than that of the first dielectric layer from the substrate; and
etching the second dielectric layer on the sidewalls of the lower patterns and the substrate to form a dielectric layer pattern under the mask pattern.
2. The method of claim 1, wherein the first dielectric layer comprises a metal oxide having a greater dielectric constant than silicon nitride.
3. The method of claim 2, wherein the first dielectric layer comprises at least one selected from the group consisting of aluminum oxide, hafnium oxide and zirconium oxide.
4. The method of claim 1, wherein forming the second dielectric layer comprises performing an argon sputtering process over the first dielectric layer.
5. The method of claim 4, wherein the argon sputtering process is performed under a pressure of about 20 mTorr to about 40 mTorr and at a bias voltage of about 100 V to about 900 V.
6. The method of claim 1, wherein etching the second dielectric layer comprises anisotropically etching the second dielectric layer.
7. The method of claim 1, wherein the second dielectric layer is etched using an etching gas comprising at least one selected from the group consisting of chlorine (Cl2), boron trichloride (BCl3) and hydrogen bromide (HBr).
8. The method of claim 1, wherein forming the second dielectric layer and etching the second dielectric layer are sequentially performed repeatedly.
9. A method of manufacturing a non-volatile memory device, comprising:
forming a tunnel oxide layer and a conductive layer pattern on a substrate;
forming a first dielectric layer on a surface of the conductive layer pattern and a surface of the substrate;
forming a control gate electrode on the first dielectric layer to partially expose the first dielectric layer;
partially removing the exposed first dielectric layer on an upper surface and upper sidewalls of the conductive layer pattern between the control gate electrodes and depositing the removed first dielectric layer on a surface of the first dielectric layer between the conductive layer patterns, to form a second dielectric layer having a thickness greater than that of the first dielectric layer from the substrate;
etching the second dielectric layer on the sidewalls of the conductive layer pattern and the substrate to form a dielectric layer pattern; and
etching the exposed conductive layer pattern between by the control gate electrodes to form a floating gate electrode.
10. The method of claim 9, further comprising forming an isolation layer pattern in the substrate between the conductive layer patterns.
11. The method of claim 9, wherein forming the isolation layer pattern comprises:
etching the substrate between the conductive layer pattern to form an isolation trench;
filling the trench and a gap between the conductive layer patterns with an insulation layer to form a preliminary isolation layer pattern; and
etching the preliminary isolation layer pattern to partially expose the sidewalls of the conductive layer patter to form the isolation layer pattern.
12. The method of claim 11, further comprising forming a wing spacer on the isolation layer pattern to partially cover the sidewalls of the conductive layer pattern.
13. The method of claim 11, further comprising partially removing the isolation layer pattern, after forming the dielectric layer pattern.
14. The method of claim 9, wherein the first dielectric layer comprises a metal oxide having a greater dielectric constant than silicon nitride.
15. The method of claim 14, wherein the first dielectric layer comprises at least one selected from the group consisting of aluminum oxide, hafnium oxide and zirconium oxide.
16. The method of claim 14, wherein silicon oxide, the metal oxide and silicon oxide are sequentially stacked to form the first dielectric layer.
17. The method of claim 9, wherein forming the second dielectric layer comprises performing an argon sputtering process over the first dielectric layer.
18. The method of claim 9, wherein etching the second dielectric layer comprises anisotropically etching the second dielectric layer.
19. The method of claim 18, wherein the second dielectric layer is etched using an etching gas comprising at least one selected from the group consisting of chlorine (Cl2), boron trichloride (BCl3), and hydrogen bromide (HBr).
20. The method of claim 9, wherein forming the floating gate electrode comprises performing a dry etch process using an etching gas including a series of a fluorocarbon over the conductive layer pattern.
21. The method of claim 20, wherein the etching gas including a series of a fluorocarbon comprises at least one selected from the group consisting of carbon tetrafluoride (CF4), difluoromethane (CH2F2) and octafluorocyclobutane (C4F8).
22. The method of claim 9, wherein forming the second dielectric layer and etching the second dielectric layer are sequentially performed repeatedly, before forming the floating gate pattern.