All The Claims

1. A method for producing a multifunctional particle, the method comprising:
contacting a hydrophobic silane to a surface of a silica particle comprising a diatomaceous earth particle, a fused silica particle or a rice husk ash particle to chemically bond the hydrophobic silane to at least a portion of the surface of the silica particle;
contacting a silane coupling agent to the surface of the silica particle to chemically bond the silane coupling agent to at least a portion of the surface of the silica particle;
rinsing the silica particle with a solvent after contacting at least one of the hydrophobic silane or the silane coupling agent to remove impurities and to remove any of the at least one of the hydrophobic silane or the silane coupling agent that are unattached to the silica particle; and
wherein the multifunctional particle is superhydrophobic and chemically reactive.
2. The method of claim 1, wherein the hydrophobic silane and the silane coupling agent are simultaneously bonded to the surface of the silica particle.
3. The method of claim 1, wherein the hydrophobic silane bonds to the surface of the silica particle before the silane coupling agent bonds to the surface of the silica particle.
4. The method of claim 1, wherein the silane coupling agent bonds to the surface of the silica particle before the hydrophobic silane bonds to the surface of the silica particle.
5. The method of claim 1, wherein the silane coupling agent is selected from the group consisting of amino-functional hydrocarbon silanes, N-(6-aminohexyl)-3-aminopropyltrimethoxysilane, aminohexylaminoethyltrimethoxysilane, aminopropyltrimethoxysilane, aminopropyltriethoxysilane, N-(2-Aminoethyl)-3-aminopropyl-trimethoxysilane, methyacryloxypropyl-trimethoxysilane, and combinations thereof.
6. The method of claim 1, wherein the silane coupling agent comprises amine silanes, olefin silanes, anhydride silanes, epoxy silanes, halogen silanes, hydroxyl silanes, dipodal silanes, acrylate silanes, sulfur-containing silanes, isocyanate silanes, or azide silanes.
7. The method of claim 1, wherein the hydrophobic silane comprises a molecule of the structure:
Xy(CH3)(3-y)SiLR

where y is 1 to 3;
X is Cl, Br, I, H, HO, R\u2032HN, R\u20322N, imidizolo, R\u2032C(O)N(H), R\u2032C(O)N(R\u2033), R\u2032O, F3CC(O)N(H), F3CC(O)N(CH3), or F3S(O)2O, where R\u2032 is a straight or branched chain hydrocarbon of 1 to 4 carbons and R\u2033 is methyl or ethyl;
L, a linking group, is CH2CH2, CH2CH2CH2, CH2CH2O, CH2CH2CH2O, CH2CH2C(O), CH2CH2CH2C(O), CH2CH2OCH2, CH2CH2CH2OCH2; and
R is (CF2)nCF3 or (CF(CF3)OCF2)nCF2CF3, where n is 0 to 24.
8. The method of claim 1, wherein the ratio of the hydrophobic silane to the silane coupling agent chemically bonded to the surface of the silica particle is from 5:1 to 2.5:1 by weight.
9. The method of claim 1, wherein the multifunctional particle comprises a self-assembled monolayer.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. An apparatus for connecting superior and inferior vertebrae, comprising:
a fastener adapted for connecting the superior vertebra to the inferior vertebra; and
a receiver for positioning between the superior and inferior vertebrae, the receiver including a passage for receiving the fastener, the receiver having a first surface for positioning adjacent the first vertebrae and a second surface for positioning adjacent to the inferior vertebrae, the passage extending at an angle relative to the first and second surfaces.
2. The apparatus of claim 1, wherein the receiver includes first and second passages, each adapted for receiving a fastener for connecting with the superior and inferior vertebrae.
3. The apparatus of claim 2, wherein the first and second passages extend at angles relative to each other.
4. The apparatus of claim 1, further including a tool adapted for temporarily connecting with the receiver, the tool including a guide for guiding a drilling element for forming an opening in one of the superior or inferior vertebrae when connected to the receiver.
5. The apparatus of claim 4, wherein the guide is tubular.
6. The apparatus of claim 4, wherein the guide is connected to the tool for movement along an arcuate path to a position in alignment with the angled passage of the receiver.
7. The apparatus of claim 4, wherein the tool comprises a connector adapted for connecting to the body of the receiver.
8. The apparatus of claim 1, further including a tubular guide for guiding a drilling element for forming an opening in one of the superior or inferior vertebrae.
9. The apparatus of claim 8, wherein the tubular guide is connected to the receiver in alignment with the angled passage.
10. An apparatus for use in connection with a procedure for connecting superior and inferior vertebrae using a receiver including at least one passage, comprising:
a tool adapted to be connected to the receiver for guiding a drilling element for forming an opening in one of the superior or inferior vertebrae.
11. The apparatus of claim 10, wherein the tool comprises a guide adapted for receiving the drilling element.
12. The apparatus of claim 11, wherein the guide is connected to the tool for movement along an arcuate path to a position in alignment with the angled passage of the receiver.
13. The apparatus of claim 10, wherein the tool includes a connector for connecting to the receiver in a manner that prevents relative rotation during use in forming the opening on one of the superior or inferior vertebrae.
14. The apparatus of claim 10, wherein the tool includes a connector for connecting to the receiver in a manner that allows relative rotation after forming the opening on one vertebrae to form an opening in the other vertebra.
15. An apparatus for use in connection with a procedure for connecting superior and inferior vertebrae, comprising:
a receiver for positioning between the superior and inferior vertebrae, the receiver adapted for positioning between the superior vertebra and the inferior vertebra; and
a tool adapted to be connected to the receiver for guiding a drilling element for forming an opening in one of the superior or inferior vertebrae.
16. The apparatus of claim 15, wherein the receiver includes at least one passage adapted for receiving a fastener, the passage extending at an angle relative to a first surface of the receiver for positioning adjacent to the superior vertebra and a second surface of the receiver for positioning adjacent to the inferior vertebra.
17. The apparatus of claim 15, wherein the tool comprises a guide adapted for receiving the drilling element.
18. The apparatus of claim 17, wherein the guide is connected to the tool for movement along an arcuate path to a position in alignment with the angled passage of the receiver.
19. The apparatus of claim 15, wherein the tool includes a connector for connecting to the receiver in a manner that prevents relative rotation during use in forming the opening on one of the superior or inferior vertebrae.
20. The apparatus of claim 15, wherein the tool includes a connector for connecting to the receiver in a manner that allows relative rotation after forming the opening on one vertebrae to form an opening in the other vertebra.

1. A manufacturing method of a semiconductor device comprising:
forming a mask insulator on a silicon oxide film on a semiconductor substrate;
patterning the mask insulator into a device isolation pattern;
forming a device isolation trench in the semiconductor substrate using the patterned mask insulator as a mask;
filling an isolation dielectric in the device isolation trench to form device isolation, thereby separating a silicon substrate surface to active regions;
removing the mask insulator and the silicon oxide film to expose a surface of the active region;
forming a gate dielectric on the active region;
depositing a first conductive film on a whole surface of the gate dielectric;
forming a slit in the first conductive film, the gate dielectric, and the semiconductor substrate so as to include at least end portion of the active region;
forming an inter-electrode dielectric on a whole face of the first conductive film including an inner face of the slit;
depositing a second conductive film on the inter-electrode dielectric;
patterning the second conductive film, the inter-electrode dielectric, the first conductive film, and the gate dielectric to form a gate electrode of a memory cell transistor and a gate electrode of a select transistor;
introducing dopant to the semiconductor substrate using the gate electrodes of the memory cell transistor and the select transistor as masks to form sourcedrain;
forming a first wiring electrically connected to the sourcedrain; and
forming a second wiring electrically connected to the first conductive film of the select transistor.
2. The manufacturing method of a semiconductor device according to claim 1, wherein the slit separates the active region such that the active region is consisted of a flat face alone.
3. The manufacturing method of the semiconductor device according to claim 2, wherein a single slit simultaneously separates channel regions of a plurality of memory cell transistors.
4. The manufacturing method of the semiconductor device according to claim 1, wherein a plurality of the memory cell transistors are disposed between a pair of the select transistors.
5. The manufacturing method of the semiconductor device according to claim 1, further comprising:
removing the inter-electrode dielectric, the first conductive film, and the gate dielectric to expose a surface of the active region of the semiconductor substrate in a peripheral circuit region;
forming a second gate dielectric on the active region in the peripheral circuit region;
depositing the second conductive film on a whole face of the peripheral circuit region;
patterning the second conductive film and the second gate dielectric in the peripheral circuit region to form a gate electrode of a peripheral transistor; and
introducing dopant to the semiconductor substrate using the gate electrodes of the peripheral transistor as a mask to form sourcedrain.
6. The manufacturing method of the semiconductor device according to claim 5, wherein the slit separates the active region such that the active region is consisted of a flat face alone.
7. The manufacturing method of the semiconductor device according to claim 1, further comprising:
forming a second silicon oxide film having a thickness that is at least three times that of the gate dielectric on a bottom of the slit prior to form the inter-electrode dielectric, wherein an upper face of the second silicon oxide film is higher than that of the gate dielectric.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A device (1000; 2000) for encoding an input signal (102) into a digital pulse-width andor phase modulated output signal (162), said signal being referred to hereinafter as a digital output signal (162), said device comprising:
an input for receiving the input signal (102) and an output for outputting the digital output signal (162),
a phase encoder (100) configured to derive a binary first start phase word (104) and a binary first terminal phase word (106) with a first resolution from the input signal (102), wherein
the first start phase word (104) determines a starting time within an encoding period, at which a rising edge of a target pulse (108) is to occur in the digital output signal (162), and the first terminal phase word (106) determines a termination point within the encoding period, at which a falling edge of the target pulse (108) is to occur in the digital output signal (162),
a phase interpolator (110) connected downstream from the phase encoder (100) and configured to convert the first start phase word (104) into a plurality of second binary start phase words (114.1 . . . M) and the first terminal phase word (106) into a plurality of second binary terminal phase words (116.1 . . . M), with a second resolution that is smaller than the first resolution,
wherein a respective second start phase word describes one of N possible discrete times in the encoding period and thus approximately determines the starting time with the second resolution, and a respective second terminal phase word describes one of the N possible discrete times in the encoding period and thus approximately determines the termination point with the second resolution, and
an output signal generator (130, 140, 150, 160; 200, 220) configured to convert the plurality of second start phase words (114.1 . . . M) and the plurality of second terminal phase words (116.1 . . . M) into a serial sequence of output pulses and to output these as an output signal (162) via the output, the serial sequence of output pulses corresponding on average over time to the target pulse (108).
2. The device (1000) according to claim 1, in which the output signal generator (130, 140, 150, 160) is fed a reference clock signal (132) and the output signal generator (130, 140, 150, 160) comprises:
a multiphase clock signal generator (130) configured to derive a multiphase clock signal (134) from the reference clock signal (132), said reference clock signal (132) comprising a plurality of clock signals phase-shifted by discrete amounts of phase, the phase shift of said clock signals relative to the reference clock signal increasing, beginning at zero, by one phase shift from one clock signal to the next and,
a start phase multiplexer (140) and a terminal phase multiplexer (150), to the input side of each of which the multiphase clock signal (134) is supplied, wherein
the start phase multiplexer (140) is configured to switch one of the phase-shifted clock signals, as a start phase signal (144), through to its output according to the plurality of second start phase words (114.1 . . . M) and
the terminal phase multiplexer (150) is configured to switch one of the phase-shifted clock signals, as a terminal phase signal (156), through to its output according to the plurality of second terminal phase words (116.1 . . . M) and
a signal combiner (160) configured to combine the start phase signal (144) and the terminal phase signal (156) to form the digital output signal (162), by
making the start phase signal (144) trigger the rising edge of a respective output pulse in the output signal and making the terminal phase signal (156) trigger the falling edge of the respective output pulse.
3. The device (2000) according to claim 1, in which the output signal generator (200, 220) comprises:
a mapper (200) to which the plurality of second start phase words (114.1 . . . M) and the plurality of second terminal phase words (116.1 . . . M) are fed and which is configured to provide a plurality of mapper output signals (210) according to the plurality of second start phase words (114.1 . . . M) and the plurality of second terminal phase words (116.1 . . . M), wherein
a respective one of the mapper output signals (210) forms a pulse whose pulse width and phase are determined by a respective word pair which is formed from a respective one of the plurality of second start phase words (114.1 . . . M) and a respective one of the plurality of second terminal phase words (116.1 . . . M), and
an output multiplexer (220) configured to convert the plurality of mapper output signals into the digital output signal.
4. The device (1000; 2000) according to claim 1, in which the phase encoder (100) is operated at a phase encoder clock rate andor the phase interpolator (110) is operated at a phase interpolator clock rate, and the output signal generator is operated at a output signal generator clock rate, the phase encoder clock rate and the phase interpolator clock rate each being lower by at least a factor of two than the output signal generator clock rate.
5. The device (1000; 2000) according to claim 1, in which the phase encoder (100) is configured to derive the first start phase word (104) and the first terminal phase word (106) in such a way that the time of the rising edge of a respective output pulse and the time of the falling edge of the respective output pulse are symmetrically varied with respect to a reference phase.
6. The device (1000; 2000) according to claim 1, in which the output signal generator (160, 130, 140, 150; 200, 210) is configured to
produce an output pulse with a permitted minimal pulse width (169) in the digital output signal (162) and then to suppress any subsequent output pulse or
to suppress any output pulse and then to produce an output pulse with a permitted minimal pulse width (169) in the digital output signal (162),

if the pulse width of the target pulse (169) falls below a prohibited minimum.
7. The device (1000; 2000) according to claim 1, wherein the input signal (102) comprises an amplitude signal (102.1) and a phase signal (102.2).
8. The device (1000; 2000) according to claim 1, in which the phase interpolator (110) includes at least one delta sigma modulator for conversion purposes.
9. A power amplifier (170) having the device (1000; 2000) according to claim 1.
10. A transmission arrangement (190) having a device (1000; 2000) according to claim 1.
11. A method for encoding an input signal (102) into a digital pulse-width andor phase modulated output signal (162), referred to hereinafter as a digital output signal (162), comprising the steps of:
receiving the input signal,
deriving a binary first start phase word (104) and a binary first terminal phase word (106) from the input signal, with a first resolution, wherein
the first start phase word (104) determines a starting time within an encoding period, at which a rising edge of a target pulse (108) is to occur in the digital output signal (162), and the first terminal phase word (106) determines a termination point within the encoding period, at which a falling edge of the target pulse (108) is to occur in the digital output signal (162),
converting the first start phase word (104) into a plurality of second binary start phase words (114.1 . . . M) and the first terminal phase word (106) into a plurality of second binary terminal phase words (116.1 . . . M), with a second resolution that is smaller than the first resolution, wherein
a respective second start phase word describes one of N possible discrete times in the encoding period and thus approximately determines the starting time with the second resolution, and a respective second terminal phase word describes one of the N possible discrete times in the encoding period and thus approximately determines the termination point with the second resolution,
converting the plurality of second start phase words (114.1 . . . M) and the plurality of second terminal phase words (116.1 . . . M) into a serial sequence of output pulses, the serial sequence of output pulses corresponding on average over time to the target pulse (108), and
outputting the serial sequence of output pulses as a digital output signal (162).
12. The method of claim 11, in which conversion includes:
providing a reference clock signal (132),
deriving a multiphase clock signal (134) from the reference clock signal (132), the reference clock signal (132) comprising a plurality of clock signals phase-shifted by discrete amounts of phase, the phase shift of said clock signals relative to the reference clock signal increasing, beginning at zero, by one phase shift from one clock signal to the next,
selecting a first of the plurality of clock signals (134) according to the plurality of second start phase words (114.1 . . . M) and providing the selected first clock signal as the start phase signal (144),
selecting a second of the plurality of clock signals (134) according to the plurality of second terminal phase words (116.1 . . . M) and providing the selected second clock signal as the terminal phase signal (156),
combining the start phase signal (144) and the terminal phase signal (156) to form the output signal (162), by making the start phase signal (144) trigger the rising edge of a respective output pulse in the digital output signal (162) and making the terminal phase signal (156) trigger the falling edge of the respective output pulse.
13. The method of claim 11, in which conversion includes:
generating a plurality of mapper output signals (210) according to the plurality of second start phase words (114.1 . . . M) and the plurality of second terminal phase words (116.1 . . . M) by means of a mapper (200), wherein
a respective one of the mapper output signals (210) forms a pulse whose pulse width and phase are determined by a respective word pair which is formed from a respective one of the plurality of second start phase words (114.1 . . . M) and a respective one of the plurality of second terminal phase words (116.1 . . . M), and
serially outputting the plurality of mapper output signals (210) as the digital output signal (162).
14. A method for transmitting a high-frequency output signal, wherein a low-frequency input signal (102) is transformed by a method according to claim 11 into the high-frequency digital pulse-width andor phase modulated output signal (162) and then transmitted.