All The Claims

1. A method of repairing a circuit, comprising:
positioning a circuit in a vacuum chamber;
creating a layer of at least one reactive material in proximity with a surface of the circuit;
exciting a portion of the layer of reactive materials to form chemical radicals;
removing a portion of the surface of the circuit to expose at least one defect;
at least one of etching to remove a first defective portion of the circuit, and depositing a material to fill a second defective portion of the circuit; and
depositing at least one material to replace the removed portion of the surface of the circuit.
2. The method of claim 1, wherein the etching to remove the first defective portion of the circuit comprises creating a layer of a second at least one reactive material in proximity with the surface and the exposed defect of the circuit, exciting a portion of the layer of the second reactive materials to form chemical radicals to etch and remove the first defective portion of the circuit.
3. The method of claim 1, wherein the depositing to fill a second defective portion of the circuit comprises creating a layer of a third at least one reactive material in proximity with the surface and the exposed defect of the circuit, exciting a portion of the layer of the third reactive materials to form chemical radicals to deposit a material compatible with the second defective portion of the circuit and fill the second defective portion of the circuit.
4. The method of claim 1, wherein the depositing at least one material to replace the removed portion of the surface of the circuit comprises creating a layer of a fourth at least one reactive material in proximity with the surface and the exposed defect of the circuit, exciting a portion of the layer of the fourth reactive materials to form chemical radicals to deposit at least one material compatible with the removed portion of the circuit, and to fill the removed portion of the circuit.
5. The method of claim 4, wherein at least one of the reactive materials includes at least one material that does not directly interact with the other reactive materials.
6. The method of claim 1, wherein the reactive materials includes a halogen.
7. The method of claim 6, wherein the halogen comprises xenon fluoride.
8. The method of claim 1, wherein exciting a portion of the layer of reactive materials to form chemical radicals comprises an energetic beam including at least one of an electron beam, ion beam, laser beam, microwave beam and X-ray beam.
9. The method of claim 8, wherein an area containing the chemical radicals has a diameter of less than 0.10\u03bc.
10. The method of claim 9, wherein the energetic beam is an electron beam which comprises a portion of a scanning electron microscope disposed to provide an image of the portion of the surface of the circuit.
11. The method of claim 1, wherein the at least one reactive material is changed, as the surface of the circuit is removed to expose the at least one defect, to selectively remove different material layers above the at least one defect.
12. The method of claim 1, wherein removing a portion of the surface creates reaction products analyzed by at least one of residual gas analyzer, mass spectroscopy, optical emission spectroscopy, atomic absorption spectroscopy, infrared spectroscopy, Raman spectroscopy and energy dispersive analysis of X-rays.
13. The method of claim 1, wherein a vacuum pressure of the vacuum chamber is determined by a desired mean free path of the chemical radicals generated by the exciting a portion of the layer of reactive materials to form chemical radicals.
14. The method of claim 13, wherein the at least one reactive material is one of a gas, a liquid and a solid at standard temperature and pressure which sublimes in the vacuum chamber at the determined vacuum pressure.
15. The method of claim 2, wherein the defective portion of the circuit includes a conductive material that one of shorts two signals lines, creates a leakage path, is an unblown fuse link, and is a circuit design error.
16. The method of claim 3, wherein the defective portion of the circuit includes a conductive material that one of open circuits a signal line, open circuits a power line, open circuits a clock line, is a blown fuse link, and is a circuit design error.
17. The method of claim 3, wherein the defective portion of the circuit includes at least one of a void in an insulator layer, an incompletely etched contact forming an open circuit, and an oxidized surface of a conductive material.
18. The method of claim 1, wherein creating a layer of reactive material in proximity with the surface includes at least one of directed gas flow, gaseous diffusion through a showerhead, sublimation of a solid material, bubbling an inert gas through a liquid material, and spraying a liquid.
19. The method of claim 1, wherein the at least one reactive material includes at least one of halogen, a metallo-halide, a metallo-organic, a silane, and oxygen.
20. The method of claim 1, wherein the circuit includes an integrated circuit.
21. A method of repairing a circuit, comprising:
positioning a circuit in a vacuum chamber;
creating a combination of reactive materials in proximity with a surface of the circuit;
exciting a portion of the layer of reactive materials to form chemical radicals;
removing a portion of the surface of the circuit to expose at least one defect;
at least one of etching to remove a defective portion of the circuit, depositing a material to fill a defective portion of the circuit, depositing at least one material to replace the removed portion of the circuit; and
testing the repaired circuit.
22. The method of claim 21, wherein the exciting a portion of the layer of reactive materials to form chemical radicals comprises an energetic beam.
23. The method of claim 22, wherein the vacuum chamber is a portion of a scanning electron microscope disposed to image the circuit, the energetic beam comprises the electron beam of the scanning electron microscope, and the scanning electron microscope provides an image of the circuit to determine the location and status of a defective portion of the circuit.
24. The method of claim 21, wherein each one of the etching to remove a defective portion of the circuit, depositing to fill a defective portion of the circuit and depositing to replace the removed portion of the circuit, comprise at least one separate combination of reactive materials excited to form radicals.
25. The method of claim 21, wherein the defective portion of the circuit includes at least one of:
a conductive material that one of shorts two signals lines, creates a leakage path, is an unblown fuse link, and is a circuit design error;
a conductive material that one of open circuits a signal line, open circuits a power line, open circuits a clock line, is a blown fuse link, and is a circuit design error; and
a void in an insulator layer, an incompletely etched contact forming an open circuit, and an oxidized surface of a conductive material.
26. The method of claim 21, wherein the combination of reactive materials includes at least one of a liquid, a gas, a solid that sublimates in a vacuum, and comprises at least one of a halogen containing material, a metallo-halide, a metallo-organic, a silane, oxygen, and an inert material that does not chemically react with any of the other materials in the combination under the conditions of the vacuum chamber.
27. The method of claim 21, wherein removing a portion of the surface creates chemical reaction products that may be analyzed by at least one of residual gas analyzer, mass spectroscopy, optical emission spectroscopy, atomic absorption spectroscopy, infrared spectroscopy, Raman spectroscopy and energy dispersive analysis of X-rays.
28. The method of claim 27, wherein the circuit is an integrated circuit and the analysis provides an endpoint detector for an etch stop between one layer of the integrated circuit and a second layer of the integrated circuit.
29. A system for repairing integrated circuits, comprising:
a vacuum chamber;
a first gas inlet for creating a layer of a selected chemical combination in proximity with a surface of the sample;
a first energetic beam directed at a selected location on the surface of the integrated circuit with sufficient energy to form chemical radicals from at least one component of the selected chemical combination;
an analysis device for examining material removed from the surface of the sample and determining when a defect location has been exposed;
a second gas inlet for creating a second layer of a second chemical combination in proximity with the surface of the sample; and
a second energetic beam with sufficient energy to form chemical radicals from at least one component of the second chemical combination.
30. The system of claim 29, wherein the first and second energetic beams include an electron beam.
31. The system of claim 30, wherein the electron beam is a portion of a scanning electron microscope.
32. The system of claim 31, wherein the electron microscope is disposed to provide images of the selected area during the formation of chemical radicals.
33. The system of claim 29, wherein the selected chemical combination comprises a halogen containing compound.
34. The system of claim 29, wherein the first and second gas inlets for creating a layer of selected chemical combinations in proximity with the surface of the sample includes a directed gas jet, a gaseous diffusion head, a sublimation device, a bubbler and a liquid spray device.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method of neutralizing holes in the tunnel oxide of a floating-gate memory cell, the method comprising:
after applying a positive voltage to a source of the memory cell relative a common voltage while applying a first negative voltage to a control gate of the memory cell relative the common voltage, discharging the positive voltage and disabling any voltage regulation of the first negative voltage; and
allowing the first negative voltage to discharge for a predetermined period.
2. The method of claim 1, further comprising discharging the positive voltage at a rate sufficient to couple a second negative voltage to a floating gate of the memory cell during the predetermined period.
3. The method of claim 2, wherein discharging the positive voltage occurs in less than 1 ms.
4. The method of claim 2, wherein the second negative voltage has a magnitude of at least about 3 volts.
5. The method of claim 1, wherein holes are neutralized during the predetermined period.
6. The method of claim 1, wherein the predetermined period is at least about 2 ms.
7. The method of claim 6, wherein the predetermined period is at least about 10 ms.
8. The method of claim 1, further comprising programming a duration of the predetermined period after manufacture of a memory device containing the memory cell.
9. The method of claim 1, wherein a magnitude of the second negative voltage is effectively increased by using wordline drive transistors with low parasitic drain capacitance compared with a wordline capacitance.
10. The method of claim 9, wherein the low parasitic drain capacitance is on the order of 1-10 fF.
11. The method of claim 1, wherein disabling any voltage regulation of the first negative voltage further comprises disabling any regulation of the first negative voltage by a negative pump used to supply the first negative voltage.
12. The method of claim 1, wherein the positive voltage is between approximately 4V to 6V.
13. The method of claim 1, wherein the first negative voltage is initially between approximately \u22128V to \u221213V.
14. A method of neutralizing holes in the tunnel oxide of a floating-gate memory cell, the method comprising:
after applying a positive voltage to a source of the memory cell relative a common voltage while applying a first negative voltage to a control gate of the memory cell relative the common voltage, discharging the positive voltage and disabling any voltage regulation of the first negative voltage; and
allowing the first negative voltage to discharge for a predetermined period of at least about 2 ms;
wherein discharging the positive voltage occurs at a rate sufficient to couple a second negative voltage to a floating gate of the memory cell during the predetermined period.
15. The method of claim 14, wherein discharging the positive voltage occurs in less than 1 ms.
16. The method of claim 14, wherein the second negative voltage has a magnitude of at least about 3 volts.
17. The method of claim 14, wherein holes are neutralized during the predetermined period.
18. The method of claim 14, wherein the predetermined period is at least about 10 ms.
19. The method of claim 14, further comprising programming a duration of the predetermined period after manufacture of a memory device containing the memory cell.
20. The method of claim 14, wherein a magnitude of the second negative voltage is effectively increased by using wordline drive transistors with low parasitic drain capacitance compared with a wordline capacitance.
21. The method of claim 20, wherein the low parasitic drain capacitance is on the order of 1-10 fF.
22. The method of claim 14, wherein disabling any voltage regulation of the first negative voltage further comprises disabling any regulation of the first negative voltage by a negative pump used to supply the first negative voltage.
23. The method of claim 14, wherein the positive voltage is between approximately 4V to 6V.
24. The method of claim 14, wherein the first negative voltage is initially between approximately \u22128V to \u221213V.

1. A fence system comprising:
a first base having a first receiver and a first pair of base slots;
a first post having a first top with a pair of first top slots and a first bottom with a pair of first bottom slots;
a second base having a second receiver and a second pair of base slots;
a second post having a second top with a pair of second top slots and a second bottom with a pair of second bottom slots;
a first generally rectangular tarp having four corners;
a first clip removably attached to a respective one of the corners of the first tarp;
a second clip removably attached to another respective one of the corners of the first tarp;
a third clip removably attached to yet another respective one of the corners of the first tarp;
a fourth clip removably attached to yet another respective one of the corners of the first tarp; and
wherein, the first clip is received within a respective one of the first top slots and the second clip is received within a respective one of the first bottom slots and the first post is received within the first receiver such that the second clip is received within a respective one of the first base slots and wherein the third clip is received within a respective one of the second top slots and the fourth clip is received within a respective one of the second bottom slots and the second post is received within the second receiver and the fourth clip is received within a respective one the second base slots.
2. The fence system as in claim 1 wherein each clip comprises:
a first arm having a first bulbous proximal end, a first distal end with a first extension, and a snap head; and
a second arm having a second bulbous proximal end, a second distal end with a second extension, and a snap opening, the first bulbous end pivotally attached to the second bulbous such that the clip is capable of pivoting between an open position wherein the first extension and the second extension are spaced apart from one another and a closed position wherein the first extension and the second extension are in apposed position and the snap head is frictionally received within the snap opening such that the clip is attached to its respective corner of the tarp by placing the clip into the closed position and sandwiching the tarp between the apposed first extension and the second extension.
3. The fence system as in claim 1 wherein the first base has a first hollow interior with a first fill spout leading thereto, and the second base has a second hollow interior with a second fill spout leading thereto.
4. The fence system as in claim 1 further comprising:
a third base having a standard extending upwardly therefrom;
a cross brace extending from the standard;
a collar attached to the cross brace such that the collar is attached to the first top of the first post; and
a third post extending upwardly from the collar.
5. The fence system as in claim 1 further comprising:
a third base having a third receiver and a third pair of base slots;
a third post having a third top with a pair of third top slots and a third bottom with a pair of first bottom slots;
a second generally rectangular tarp having four corners;
a fifth clip removably attached to a respective one of the corners of the second tarp;
a sixth clip removably attached to another respective one of the corners of the second tarp;
a seventh clip removably attached to yet another respective one of the corners of the second tarp;
a eighth clip removably attached to yet another respective one of the corners of the second tarp; and
wherein, the fifth clip is received within another respective one of the second top slots and the sixth clip is received within another respective one of the second bottom slots and within a respective another of the second base slots and wherein the seventh clip is received within a respective one of the third top slots and the eighth clip is received within a respective one of the third bottom slots and the third post is received within the third receiver and the eighth clip is received within a respective one the third base slots.
6. The fence system as in claim 5 wherein each clip comprises:
a first arm having a first bulbous proximal end, a first distal end with a first extension, and a snap head; and
a second arm having a second bulbous proximal end, a second distal end with a second extension, and a snap opening, the first bulbous end pivotally attached with the second bulbous such that the clip is capable of pivoting between an open position wherein the first extension and the second extension are spaced apart from one another and a closed position wherein the first extension and the second extension are in apposed position and the snap head is frictionally received within the snap opening such that the clip is attached to its respective corner of the tarp by placing the clip into the closed position and sandwiching the tarp between the apposed first extension and the second extension.
7. The fence system as in claim 5 wherein the first base has a first hollow interior with a first fill spout leading thereto, the second base has a second hollow interior with a second fill spout leading thereto, and the third base has a third hollow interior with a third fill spout leading thereto.
8. The fence system as in claim 5 further comprising:
a fourth base having a standard extending upwardly therefrom;
a cross brace extending from the standard;
a collar attached to the cross brace such that the collar is attached to the first top of the first post; and
a fourth post extending upwardly from the collar.
9. A fence system comprising:
a first base having a first receiver;
a first post having a first section of hook and loop material, the first post received within the first receiver;
a second base having a second receiver;
a second post having a second section of hook and loop material, the second post received within the second receiver;
a tarp having a first end with a third section of hook and loop material and a second end having a fourth section of hook and loop material such that the first end of the tarp is attached to the first post by cooperatively mating the first section of hook and loop material with the third section of hook and loop material and the second end of the tarp is attached to the second base by cooperatively mating the second section of hook and loop material with the fourth section of hook and loop material.
10. The fence system as in claim 9 wherein the first base has a first hollow interior with a first fill spout leading thereto, and the second base has a second hollow interior with a second fill spout leading thereto.
11. The fence system as in claim 9 further comprising:
a third base having a standard extending upwardly therefrom;
a cross brace extending from the standard;
a collar attached to the cross brace such that the collar is attached to the first top of the first post; and
a third post extending upwardly from the collar.
12. The fence system as in claim 9 further comprising:
a third base having a third receiver;
a third post having a pair of slots, the third post received within the third receiver such that the tarp passes through the pair of slots.
13. The fence system as in claim 12 wherein the first base has a first hollow interior with a first fill spout leading thereto, the second base has a second hollow interior with a second fill spout leading thereto, and the third base has a third hollow interior with a third fill spout leading thereto.
14. The fence system as in claim 12 further comprising:
a fourth base having a standard extending upwardly therefrom;
a cross brace extending from the standard;
a collar attached to the cross brace such that the collar is attached to the first top of the first post; and
a fourth post extending upwardly from the collar.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method for initializing a data processing system comprising functional hardware elements and a system management controller for controlling said functional hardware elements, the method comprising:
defining sequences of initialization steps for selected hardware elements of said functional hardware elements, wherein each sequence of initialization steps is defined for a single selected hardware element of said selected hardware elements;
determining dependencies among said initialization steps;
generating a control flow table representing said sequences of initialization steps and said dependencies;
generating a system configuration database representing a list of all active functional hardware elements in said data processing system;
during an initialization phase of said data processing system, executing on said system management controller the steps:
analyzing said control flow table and said system configuration database;
based on said analyzing said control flow table and said system configuration database, assigning said sequences of initialization steps to said selected hardware elements; and
generating and executing a parallel thread of execution for each of said assigned sequences of initialization steps, wherein said sequences of initialization steps are executed in parallel; and

wherein, said dependencies between said initialization steps are represented by trigger and wait steps that are inserted in said sequences of initialization steps, and a first parallel thread of execution signals a second parallel thread of execution that a dependency is resolved when performing a trigger step, and wherein said second parallel thread of execution stops its execution when performing a wait step until receiving a signal from said first thread of parallel execution.
2. A computer program stored into internal memory of a digital computer system, the computer program comprising software code portions for performing a method when said computer program is executed on said computer system, the method comprising:
defining sequences of initialization steps for selected hardware elements, wherein each sequence of initialization steps is defined for a single selected hardware element of said selected hardware elements;
determining dependencies among said initialization steps;
generating a control flow table representing said sequences of initialization steps and said dependencies;
generating a system configuration database representing a list of all active functional hardware elements in said computer system;
during an initialization phase of said computer system, executing on a system management controller the steps:
analyzing said control flow table and said system configuration database,
based on said analyzing said control flow table and said system configuration database, assigning said sequences of initialization steps to said selected hardware elements; and
generating and executing a parallel thread of execution for each of said assigned sequences of initialization steps, wherein said sequences of initialization steps are executed in parallel; and

wherein said dependencies between said initialization steps are represented by trigger and wait steps that are inserted in said sequences of initialization steps, and a first parallel thread of execution signals a second parallel thread of execution that a dependency is resolved when performing a trigger step, and wherein said second parallel thread of execution stops its execution when performing a wait step until receiving a signal from said first thread of parallel execution.
3. The computer program according to claim 2, wherein said computer system executes an operating system, and wherein for the generation of said parallel threads of execution at least one of the following facilities of said operating system is used: operating system threads, operating system processes.
4. The computer program according to claim 2, wherein the analyzing step, programming objects are used to represent at least one of the following: said selected hardware elements, said initialization steps.
5. A data processing system comprising:
functional hardware elements; and
a system management controller for controlling said functional hardware elements, where said system management controller is configured to:
define sequences of initialization steps for selected hardware elements of said functional hardware elements, wherein each sequence of initialization steps is defined for a single selected hardware element of said selected hardware elements;
determine dependencies among said initialization steps;
generate a control flow table representing said sequences of initialization steps and said dependencies;
generate a system configuration database representing a list of all active functional hardware elements in said data processing system; and
during an initialization phase of said data processing system, execute on said system management controller the steps:
analyzing said control flow table and said system configuration database;
based on said analyzing said control flow table and said system configuration database, assigning said sequences of initialization steps to said selected hardware elements; and
generating and execute executing a parallel thread of execution for each of said assigned sequences of initialization steps, wherein said sequences of initialization steps are executed in parallel; and
wherein said dependencies between said initialization steps are represented by trigger and wait steps that are inserted in said sequences of initialization steps, and a first parallel thread of execution signals a second parallel thread of execution that a dependency is resolved when performing a trigger step, and wherein said second parallel thread of execution stops its execution when performing a wait step until receiving a signal from said first thread of parallel execution.
6. The data processing system according to claim 5, further comprising hardware nodes with a subset of said functional hardware elements and a node controller each, where the node controllers are used by said system management controller for the execution of said initialization steps.
7. The data processing system according to claim 5, wherein a persistent storage of said system management controller is used to store at least one of the following: said control flow table, a said system configuration database.