All The Claims

1. A singulation apparatus comprising:
a carrier including a plurality of singulation sites and a scribe line between each of the plurality of singulation sites and an adjacent singulation site, wherein a top surface of the carrier is configured to receive a semiconductor substrate thereon;
and wherein each of the plurality of singulation sites includes a deformable portion and at least one vacuum hole, wherein the at least one vacuum hole and the deformable portion is configured to form a seal around the at least one vacuum holes when a force is applied.
2. The apparatus of claim 1, wherein the deformable portion is a polymer.
3. The apparatus of claim 1, wherein the deformable portion is a cylinder.
4. The apparatus of claim 1, wherein the deformable portion is a plate having at least one vacuum hole.
5. The apparatus of claim 1 wherein each of the plurality of singulation sites has a rim between at least one vacuum hole and the scribe line.
6. The apparatus of claim 1 wherein each of the plurality of singular sites has a groove between the at least one vacuum hole and the scribe line, wherein the groove includes an inner wall and a outer wall.
7. The apparatus of claim 6, wherein a top of the inner wall of the groove and the semiconductor substrate form a seal when a force is applied to the semiconductor substrate against the carrier.
8. The apparatus of claim 1, wherein one end of the at least one vacuum hole is on a bottom surface of the carrier, wherein the bottom surface is opposite to the top surface.
9. The apparatus of claim 1, wherein one end of the at least one vacuum hole is on a side wall of the carrier.
10. The apparatus of claim 1, wherein the semiconductor substrate is a packaged substrate.
11. The apparatus of claim 1, wherein the deformable portion is detachable.
12. A singulation apparatus comprising:
a carrier having a deformable portion proximate to a top surface of the carrier configured to receive a semiconductor substrate;
a plurality of through holes in the carrier with one end from the top surface; and
a plurality of chucks in the plurality of vacuum holes, wherein each of the plurality of chucks has a first surface configured to support the semiconductor substrate when the deformable portion is deformed.
13. The apparatus of claim 12, wherein the stiffness of the plurality of chucks is higher than the deformable portion.
14. The apparatus of claim 12, wherein each of the plurality of chuck includes a vacuum hole.
15. The apparatus of claim 12, wherein the deformable portion and the semiconductor substrate form a seal around the plurality of vacuum holes when the semiconductor substrate is against the carrier.
16. The apparatus of claim 12, wherein the deformable portion is a cylinder.
17. The apparatus of claim 12 wherein the carrier has a plurality of singulation sites, and a scribe line between each of the plurality of singular sites an adjacent singulation site, the semiconductor substrate includes a carrier wafer having fabricated device thereon
18. A method of manufacturing semiconductor devices, the method comprising:
placing a semiconductor substrate on a top surface of a carrier;
introducing vacuum into a plurality of vacuum holes in the carrier to form a seal between the semiconductor substrate and a deformable portion of the carrier; and
singulating the semiconductor substrate into a plurality of semiconductor devices.
19. The method of claim 18, further comprising supporting the semiconductor substrate using a chuck in the vacuum hole,
20. The method of claim 18 further comprising inserting a detachable deformable portion in the carrier.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method for obtaining a population of cells, the method comprising:
providing a population of cells comprising a target type of differentiated cells having a pre-identified cytoskeletal profile and at least one cell selected from the group consisting of undifferentiated cells, differentiating cells and differentiated cells being different from the target type of differentiated cells; and
incubating the population of cells with a cytotoxic agent selective to a pre-identified cytoskeletal profile characterizing the target type of differentiated cells, in an amount and for a time period effective to selectively provide a modified population of cells being enriched with the target type of differentiated cells,
wherein the modified population comprises at least 90% of the target type of differentiated cells, and
wherein when transplanted into a subject, the modified population of cells do not develop rosette structures.
2. The method of claim 1, wherein the population of cells comprises neural cells, and neuronal cells.
3. The method of claim 1, wherein the pre-identified cytoskeletal profile comprises presence of tubulin on the target type of differentiated cells.
4. The method of claim 3, wherein the tubulin is class III \u03b2-tubulin present on the target type of differentiated cells.
5. The method of claim 3, wherein the cytotoxic agent is paclitaxel.
6. The method of claim 1, wherein the population of cells is obtained from stem cells that are incubated with a culture medium that promotes differentiation into the target type of differentiated cells to form the population of cells.
7. The method of claim 1, wherein the population of cells is obtained from somatic cells that are induced to transdifferentiate into the target type of differentiated cells to form the population of cells.
8. The method of claim 1, wherein the modified population of cells comprises at least 95% differentiated cells.
9. The method of claim 8, wherein the modified population of cells comprises essentially 100% differentiated cells.
10. The method of claim 1, wherein said modified population of cells comprises dopaminergic neurons.

We claim:

1. A method for planarizing a surface of an isolating layer deposited on a semiconductor body of an integrated semiconductor circuit configuration, the surface lying at a higher level in first zones of the integrated semiconductor circuit configuration than in second zones of the integrated semiconductor circuit configuration, which comprises the steps of:
covering the second zones with a block mask; and
etching the isolating layer in the first zones.
2. The method according to claim 1, which comprises forming the isolating layer as a shallow trench isolation layer.
3. The method according to claim 2, which comprises utilizing a silicon dioxide layer as the shallow trench isolation layer.
4. The method according to claim 2, which comprises forming a level of the shallow trench isolation layer at least 10 nm higher in the first zones than in the second zones.
5. The method according to claim 1, which comprises:
using the first zones of the integrated semiconductor memory configuration as a cell field; and
using the second zones of the integrated semiconductor memory configuration for a logic area.
6. The method according to claim 1, which comprises using thick oxide zones as the first zones, and thin oxide zones as the second zones.
7. The method according to claim 1, which comprises using one of dry chemical reactive ion etching and wet chemical reactive ion etching for the etching.
8. The method according to claim 1, which comprises carrying out the etching one of before and after a removal of a silicon nitride layer covering the semiconductor body outside the isolating layer.
9. The method according to claim 8, which comprises using a CHF3CF4 oxide etch chemistry for removing the silicon nitride layer.
10. A method for forming an integrated semiconductor configuration, which comprises the steps of:
depositing an isolating layer on a semiconductor body, a surface of the semiconductor body lying at a higher level in first zones than in second zones of the semiconductor body:
covering the second zones with a block mask; and
etching the isolating layer in the first zones.
11. The method according to claim 10, which comprises forming the isolating layer as a shallow trench isolation layer.
12. The method according to claim 11, which comprises utilizing a silicon dioxide layer as the shallow trench isolation layer.
13. The method according to claim 11, which comprises forming a level of the shallow trench isolation layer at least 10 nm higher in the first zones than in the second zones.
14. The method according to claim 10, which comprises:
using the first zones as a cell field; and
using the second zones for a logic area.
15. The method according to claim 10, which comprises using thick oxide zones as the first zones, and thin oxide zones as the second zones.
16. The method according to claim 10, which comprises using one of dry chemical reactive ion etching and wet chemical reactive ion etching for the etching.
17. The method according to claim 10, which comprises:
applying a silicon nitride layer covering the semiconductor body outside an area of the isolating layer before performing the covering step; and
carrying out the etching one of before and after a removal of a silicon nitride layer covering the semiconductor body outside the isolating layer.
18. The method according to claim 17, which comprises using a CHF3CF4 oxide etch chemistry for removing the silicon nitride layer.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method for installing a large bore completion system, comprising:
providing real time monitoring of reservoir parameters in a well via a retrievable instrumented stinger;
retrieving the retrievable instrumented stinger after determining a need for controlling flow;
running a lower completion section comprising one or more valves and one or more sensors in hole; and
controlling flow by manipulating one or more valves.
2. The method as recited in claim 1, wherein running the lower completion section comprises running an intelligent lower completion section.
3. The method as recited in claim 1, wherein detecting comprises utilizing sensors deployed along the retrievable instrumented stinger.
4. The method as recited in claim 1, wherein retrieving comprises retrieving the retrievable instrumented stinger from a wet connect.
5. The method as recited in claim 1, wherein running comprises running the lower completion section into engagement with a wet connect located downhole in the well.
6. The method as recited in claim 1, wherein controlling comprises operating flow control valves positioned in a plurality of well zones along the lower completion section.
7. The method as recited in claim 1, further comprising providing a power source downhole to power both sensors and valves along the lower completion section.
8. The method as recited in claim 1, wherein running comprises running the lower completion section down into a lower liner section suspended by a liner hanger and seal assembly below an upper liner section.
9. The method as recited in claim 1, further comprising communicating with the lower completion section through a wet connect comprising at least one of an inductive coupler wet connect, an electrical wet connect, a hydraulic wet connect, and a fiber optic wet connect.
10. A system, comprising:
a large bore completion system having a lower liner section disposed in a wellbore across at least one well zone;
a retrievable instrument having at least one sensor to monitor a reservoir parameter in a well zone when the retrievable instrument is conveyed downhole through an interior of the lower liner section;
a lower completion system which is run in hole to replace the retrievable instrument upon determining a need for controlling flow, the lower completion system having at least one sensor and at least one flow control valve to control flow; and
a power source located downhole to provide power to the lower completion system.
11. The system as recited in claim 10, wherein the power source is retrievable.
12. The system as recited in claim 10, wherein the large bore completion system comprises an upper liner section from which the lower liner section is suspended by a liner hanger and seal assembly.
13. The system as recited in claim 10, wherein the large bore completion system comprises an upper liner section disposed above the lower liner section but not directly coupled to the lower liner section.
14. The system as recited in claim 10, wherein the retrievable instrument comprises a retrievable instrumented stinger which is engaged and disengaged downhole via a wet connect.
15. The system as recited in claim 10, wherein the lower completion system is engaged and disengaged downhole via a wet connect.
16. The system as recited in claim 10, wherein the lower completion system is engaged and disengaged downhole via an inductive coupler.
17. A method of installing a large bore completion system, comprising:
suspending a lower liner section downhole across a plurality of well zones;
segregating well zones along the lower liner section with a plurality of controllable valves;
monitoring a well parameter; and
based on the monitoring, manipulating individual valves of the plurality of controllable valves to selectively block or limit flow at specific well zones along the plurality of well zones.
18. The method as recited in claim 17, further comprising initially detecting water intrusion with a retrievable instrumented stinger which may be temporarily inserted within the lower liner section and engaged with a wet connect at a downhole location.
19. The method as recited in claim 18, further comprising:
delivering a plurality of flow control valves and sensors downhole into the lower liner section via a lower completion system after removing the retrievable instrumented stinger; and
engaging the lower completion system with the wet connect to enable the transfer of signals to and from the plurality of flow control valves and sensors and to provide power.
20. The method as recited in claim 17, further comprising providing a removable power source downhole to provide power for the lower completion system.