All The Claims

1. A fuel cell system which is mounted in and used for a portable and small electric device, comprising:
a thin housing having a substantially rectangular parallelepiped shape;
a cell unit comprising one or more fuel cells;
a fuel tank unit for storing a fuel to be supplied to the cell unit; and
a fuel feed unit for supplying the fuel from the fuel tank unit to the cell unit, the fuel feed unit, the fuel tank unit and the cell unit being provided in the housing,
wherein the fuel tank unit, the fuel feed unit and the cell unit are located in order of i) the fuel tank unit, ii) the fuel feed unit, and iii) the cell unit in one direction between two opposite faces of the housing,
wherein the fuel tank unit comprises a valve, which supplies fuel to the fuel feed unit and opens to release the fuel in the fuel cell system only when the fuel tank unit is mounted, and
wherein the fuel feed unit connects sides of the fuel tank unit and the cell unit that face each other and reduces a pressure of gaseous fuel supplied from the fuel tank unit.
2. The fuel cell system according to claim 1, wherein the fuel tank unit, the fuel feed unit and the cell unit are located in order of i) the fuel tank unit, ii) the fuel feed unit, and iii) the cell unit in one direction between two opposite side faces of the housing.
3. The fuel cell system according to claim 2, wherein the fuel tank unit, the fuel feed unit and the cell unit are located in this order between the two opposite side faces.
4. The fuel cell system according to claim 2, wherein the one or more fuel cells of the cell unit are stacked parallel to a bottom face of the housing.
5. The fuel cell system according to claim 1, wherein the fuel tank unit, the fuel feed unit and the cell unit are located in order of i) the fuel tank unit, ii) the fuel feed unit, and iii) the cell unit in one direction between a top face and a bottom face of the housing.
6. The fuel cell system according to claim 5, wherein the cell unit faces and is located parallel to at least one of a top face and a bottom face of the housing.
7. The fuel cell system according to claim 5, wherein the cell unit, the fuel feed unit, the fuel tank unit, another fuel feed unit and another cell unit are located in this order between the top face and the bottom face.
8. The fuel cell system according to claim 1, wherein the housing has an opening for supplying an oxidizer gas.
9. The fuel cell system according to claim 8, wherein the housing comprises a portion that contains a cell unit and a portion that contains the fuel tank unit and the opening is at least in the portion of the housing that contains the cell unit.
10. The fuel cell system according to claim 8, wherein the opening is provided in a top face, a bottom face and a side face of the housing.
11. The fuel cell system according to claim 1, further comprising a wiring unit for collecting generated power and supplying it to the outside of the fuel cell, and wherein the wiring unit is provided at a location where the fuel tank unit does not exist.
12. The fuel cell system according to claim 1, wherein the fuel tank unit is provided detachably from the housing.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. Method for transferring information on the Internet, comprising the steps of:
intercepting an information request;
determining whether the information request relates to a content provider address having a corresponding alternative address, the alternative address providing at least part of the information provided at the content provider address, wherein determining whether the information request has an corresponding alternative address is accomplished by comparing the content provider address to information located on a storage means directly connected to an interceptor; and
directing an information request to one of the alternative address and the content provider address.
2. A method as recited in claim 1, further comprising the step of:
updating information at the alternative address.
3. The method of claim 1 further comprising:
providing a first list of information relating to content provider addresses having respective corresponding alternative addresses;
accessing the first list of information content provider addresses having respective corresponding alternative addresses; and
determining whether the request relates to a content provider address having a corresponding alternative address.
4. The method of claim 1 further comprising:
providing a plurality of lists of information relating to content provider addresses having respective corresponding alternative addresses;
accessing a plurality of lists of information relating to content provider addresses having respective corresponding alternative addresses; and
determining whether the request relates to a content provider address having a corresponding alternative address.
5. A method for transferring information comprising the steps of:
determining whether data entered and transmitted by an Internet user is an information request;
intercepting an information request;
determining whether the information request relates to a content provider address having a corresponding alternative address, the alternative address providing at least part of the information provided at the content provider address, wherein determining whether said information request has an corresponding alternative address is accomplished by comparing said content provider address to information located on a storage means directly connected to an interceptor; and
directing an information request to one of said alternative address and said content provider address.
6. A method as recited in claim 5, further comprising the step of:
updating information at said alternative address.
7. The method of claim 5 further comprising:
providing a first list of information relating to content provider addresses having respective corresponding alternative addresses;
accessing the first list of information content provider addresses having respective corresponding alternative addresses; and
determining whether the request relates to a content provider address having a corresponding alternative address.
8. The method of claim 5 further comprising:
providing a plurality of lists of information relating to content provider addresses having respective corresponding alternative addresses;
accessing a plurality of lists of information relating to content provider addresses having respective corresponding alternative addresses; and
determining whether the request relates to a content provider address having a corresponding alternative address.
9. A method for efficiently delivering cached information to users, comprising the steps of:
intercepting an information request;
determining the information request relates to a content provider address having a corresponding alternative address, the alternative address providing at least part of the information provided at the content provider address, wherein determining whether the information request has an corresponding alternative address is accomplished by comparing the content provider address to information located on a storage means directly connected to an interceptor;
directing an information request to one of the alternative address and the content provider address; and
providing the user requested information to the user from one of the alternative address and the content provider address.
10. A method as recited in claim 9, further comprising the step of:
updating information at said alternative address.
11. The method of claim 9 further comprising:
providing a first list of information relating to content provider addresses having respective corresponding alternative addresses;
accessing the first list of information content provider addresses having respective corresponding alternative addresses, and
determining whether the request relates to a content provider address having a corresponding alternative address.
12. The method of claim 9 further comprising:
providing a plurality of lists of information relating to content provider addresses having respective corresponding alternative addresses;
accessing a plurality of lists of information relating to content provider addresses having respective corresponding alternative addresses; and
determining whether the request relates to a content provider address having a corresponding alternative address.
13. A method comprising the steps of:
receiving a information request, wherein the information request includes information related to a content provider address;
intercepting the received information request;
determining whether the content provider address has a corresponding alternative address by comparing said content provider address to information located on a storage means directly connected to an interceptor, the corresponding alternative address also being located on a said storage means;
providing at least part of the information requested at the content provider address; and
providing the information to the Internet user based upon the information request.
14. A system for efficiently delivering cached information to Internet users, the system comprising:
means for intercepting an information request;
means for determining whether or not said information request relates to a content provider address having a corresponding alternative address, said alternative address providing at least part of the information provided at said content provider address, wherein the means for determining whether said information request has an corresponding alternative address is accomplished by comparing said content provider address to information located on a storage means directly connected to an interceptor means; and
means for directing an information request to one of said alternative address and said content provider address.
15. The system of claim 14, further comprising:
means for updating information at said alternative address.
16. The system of claim 14 further comprising:
means for providing a first list of information relating to content provider addresses having respective corresponding alternative addresses;
means for accessing the first list of information content provider addresses having respective corresponding alternative addresses; and
means for determining whether the request relates to a content provider address having a corresponding alternative address.
17. The system of claim 14 further comprising:
means for providing a plurality of lists of information relating to content provider addresses having respective corresponding alternative addresses;
means for accessing a plurality of lists of information relating to content provider addresses having respective corresponding alternative addresses; and
means for determining whether the request relates to a content provider address having a corresponding alternative address.

What is claimed is:

1. A semiconductor memory device having a data latch circuit, the semiconductor memory device comprising:
a plurality of bit lines to which a reprogrammable memory cell is connected;
a data bus on which data is transferred;
a latch connected to each of the plurality of bit lines;
a read out circuit connected to the data bus; and
a data transfer circuit group having an ability to directly transfer the data loaded in the latch circuit, to the read out circuit without being transferred to the memory cell.
2. The semiconductor memory device of claim 1, wherein the data transfer circuit group includes:
a first operation mode to transfer a data loaded to the latch circuit, to the memory cell connected to the bit line;
a second operation mode to transfer the data read out from the memory cell to the read out circuit; and
a third operation mode to directly transfer the data loaded in the latch circuit, to the read out circuit.
3. The semiconductor memory device of claim 2, wherein:
the third operation mode is performed during a test of the semiconductor memory device.
4. The semiconductor memory device of claim 2, wherein:
the first and second operation modes are performed during a normal operation; and
the third operation mode is performed during a test of the semiconductor memory device.
5. The semiconductor memory device of claim 1, wherein the data transfer circuit group includes:
a first transfer gate, one end of which is electrically connected to the bit line;
a second transfer gate, one end of which is electrically connected to an other end of the first transfer gate;
a third transfer gate, one end of which is electrically connected to the one end of the first transfer gate and an other end of which is electrically connected to the latch circuit; and
a fourth transfer gate, one end of which is electrically connected to an other end of the second transfer gate and an other end of which is electrically connected to the read out circuit.
6. The semiconductor memory device of claim 5, wherein:
when data loaded to the latch circuit is transferred to the memory cell, the first transfer gate is set to an ON state, the second transfer gate is set to an OFF state, the third transfer gate is set to an ON state, the fourth transfer gate is set to an OFF state;
when the data read out from the memory cell is transferred to the read out circuit, the first transfer gate is set to an ON state, the second transfer gate is set to an ON state, the third transfer gate is set to an OFF state, the fourth transfer gate is set to an ON state;
when the data loaded to the latch circuit is directly transferred to the read out circuit not via the memory cell, the first transfer gate is set to an OFF state, the second transfer gate is set to an ON state, the third transfer gate is set to an ON state, the fourth transfer gate is set to an ON state.
7. The semiconductor memory device of claim 6, wherein:
a potential of the control electrode of the third transfer gate is gradually raised to an ON state.
8. The semiconductor memory device of claim 5, wherein:
when the data loaded to the latch circuit is transferred to the memory cell, the first transfer gate is set to an ON state, the second transfer gate is set to an OFF state, the third transfer gate is set to an ON state, the fourth transfer gate is set to an OFF state;
when the data read out from the memory cell is transferred to the read out circuit, the first transfer gate is set to an ON state, the second transfer gate is set to an ON state, the third transfer gate is set to an OFF state, the fourth transfer gate is set to an ON state;
when the data loaded to the latch circuit is transferred to the read out circuit, the first to the fourth transfer gates are set to an ON state, and the memory cell is set to a non-selected state.
9. The semiconductor memory device of claim 8, wherein:
a potential of the control electrode of the third transfer gate is gradually raised to an ON state.
10. The semiconductor memory device of claim 1, further comprising:
a control circuit configured to control the transfer gate group so as to achieve a first operation mode and a second operation mode, wherein:
the first operation mode involves programming data loaded to the latch circuit to the memory cell; and
the second operation mode involves stopping an operation after data is loaded to the latch circuit.
11. The semiconductor memory device of claim 10, wherein:
the first operation mode is performed in a normal operation; and
the second operation mode is performed in a testing operation.
12. The semiconductor memory device of claim 1, further comprising:
an error correction circuit that is electrically connected to the read out circuit.
13. A semiconductor memory device having a data latch circuit, the semiconductor memory device comprising:
a plurality of bit lines to which a reprogrammable memory cell is connected;
a data bus on which data is transferred;
a latch circuit configured to latch the data transferred on the data bus;
a read out circuit connected to the data bus; and
a data transfer circuit group;
wherein the data transfer circuit group is controlled so as to transfer the data latched in the latch circuit to the read out circuit without being transferred to the memory cell.
14. The semiconductor memory device of claim 13, wherein the data transfer circuit has:
a first operation mode to transfer data loaded to the latch circuit to the memory cell connected to the bit line;
a second operation mode to transfer data read out from the memory cell to the read circuit; and
a third operation mode to directly transfer the data latched in the latch circuit to the read circuit.
15. The semiconductor memory device of claim 14, wherein:
the third operation mode is performed during a test of the semiconductor memory device.
16. The semiconductor memory device of claim 14, wherein:
the first and the second operation modes are performed during a normal operation; and
the third operation mode is performed during a test of the semiconductor memory device.
17. The semiconductor memory device of claim 13, wherein the data transfer circuit group includes:
a first transfer gate, one end of which electrically connected to the bit line;
a second transfer gate, one end of which electrically connected to an other end of the first transfer gate;
a third transfer gate, one end of which electrically connected to the one end of the first transfer gate and an other end of which electrically connected to the latch circuit; and
a fourth transfer gate, one end of which electrically connected to an other end of the second transfer gate and an other end of which electrically connected to the read out circuit.
18. The semiconductor memory device of claim 17, wherein:
when data loaded in the latch circuit is transferred to the memory cell, the first transfer gate is set to an ON state, the second transfer gate is set to an OFF state, the third transfer gate is set to an ON state, the fourth transfer gate is set to an ON state;
when data read out from the memory cell is transferred to the read out circuit, the first transfer gate is set to an ON state, the second transfer gate is set to an ON state, the third transfer gate is set to an OFF state, and the fourth transfer gate is set to and ON state;
when data loaded to the latch circuit is directly transferred to the read out circuit not via the memory cell, the first transfer gate is set to an OFF state, the second transfer gate is set to an ON state, the third transfer gate is set to an ON state, the fourth transfer gate is set to an ON state.
19. The semiconductor memory device of claim 18, wherein:
a voltage of a gate electrode of the third transfer gate is gradually raised to an ON state.
20. The semiconductor memory device of claim 17, wherein:
when data loaded to the latch circuit is transferred to the memory cell, the first transfer gate is set to an ON state, the second transfer gate is set to an OFF state, the third transfer gate is set to an ON state, and the fourth transfer gate is set to an OFF state;
when data read out from the memory cell is transferred to the read out circuit, the first transfer gate is set to an ON state, the second transfer gate is set to an ON state, the third transfer gate is set to an OFF state, and the fourth transfer gate is set to an ON state;
when data loaded to the latch circuit is transferred to the read out circuit, the first to the fourth transfer gates are set to an ON state, and the memory cell is set to a non-selected state.
21. The semiconductor memory device of claim 20, wherein:
a voltage of a gate electrode of the third transfer gate is gradually raised to set to an ON state.
22. The semiconductor memory device of claim 13, further comprising:
a control circuit configured to control the transfer gate group so as to achieve a first and second operation modes, wherein:
the first operation mode involves programming data loaded to the latch circuit to the memory cell; and
the second operation mode involves stopping an operation after data is loaded to the latch circuit.
23. The semiconductor memory device of claim 21, wherein:
the first operation mode is performed in a normal operation; and
the second operation mode is performed in a testing operation.
24. The semiconductor memory device of claim 13, further comprising:
an error correction circuit that is electrically connected to the read out circuit.
25. A test method of a semiconductor memory device, the method comprising:
latching data in a page latch via a data bus on which the data are transferred; and
transferring the data latched in the page latch to a cell matrix for storing the data in a first mode and to a read-out circuit in a second mode for testing whether or not an error occurs in a data transfer circuit group including the data bus, the page latch and read out circuit.
26. A memory card including the semiconductor memory device of claim 1.
27. A card holder into which the memory card of claim 26 is inserted.
28. A connecting device into which the memory card of claim 26 is inserted.
29. The connecting device according to claim 28, wherein:
the connecting device is connected to a computer.
30. A memory card comprising:
the semiconductor memory device of claim 1; and
a controller that controls the semiconductor memory device.
31. A card holder into which the memory card of claim 30 is inserted.
32. A connecting device into which the memory card of claim 30 is inserted.
33. The connecting device according to the claim 32, wherein:
the connecting device is connected to a computer.
34. A memory card including the semiconductor memory device of claim 13.
35. A card holder into which the memory card of claim 34 is inserted.
36. A connecting device into which the memory card of claim 34 is inserted.
37. The connecting device of claim 36, wherein:
the connecting device is connected to a computer.
38. A memory card comprising:
the semiconductor memory device of claim 13; and
a controller that controls the semiconductor memory device.
39. A card holder into which the memory card of claim 38 is inserted.
40. A connecting device into which the memory card of claim 38 is inserted.
41. The connecting device of claim 40, wherein:
the connecting device is connected to a computer.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A physical training device, comprising:
a rebounder platform comprising a mat surface,
a foam element beneath said mat surface, and
a plurality of resistance members, said plurality of resistance members carried by said rebounder platform.
2. The physical training device of claim 1, wherein said rebounder platform further comprises a plurality of ports defined about a perimeter of said platform, and wherein said plurality of resistance members are secured to said rebounder platform proximate said ports.
3. The physical training device of claim 1, wherein said foam element comprises memory foam.
4. A physical training system, comprising:
an elongated mini-trampoline
a foam element underlying a mat of said mini-trampoline; and
a plurality of stretchable cords adapted for removable attachment to said elongated mini-trampoline, wherein at least some of said plurality of stretchable cords have different coefficients of elasticity from one another,
wherein said mat surface and foam element of said mini-trampoline function as a generally unstable foundation surface, and wherein said plurality of stretchable cords function as resistance trainers for said physical training system.
5. The physical training system of claim 4, wherein said elongated mini-trampoline is rectangular, further comprising a frame and a plurality of springs.
6. The physical training system of claim 4, wherein said mat surface is comprised of fabric with little or no elasticity.
7. The physical training system of claim 4, wherein said mini-trampoline further comprises a surface treatment to impart non-slip characteristics.
8. The physical training system of claim 4, wherein said mat surface further comprises a surface treatment to impart non-slip characteristics.
9. The physical training system of claim 5, wherein said frame is rigid and further comprises a peripheral edge and a plurality of support legs, wherein said plurality of stretchable cords are attached proximate said peripheral edge of said frame, and wherein means are provided in association with said frame for constraining movement of said foam element.
10. The physical training system of claim 4, wherein a protective covering is installed proximate an upper surface of said plurality of springs.
11. The physical training system of claim 4, wherein said plurality of stretchable cords have different colorations from one another according to said different coefficients of elasticity.
12. The physical training system of claim 4, wherein said plurality of stretchable cords are each generally tubular-shaped and further comprise a handle at a distal end thereof.
13. The physical training device of claim 1, wherein said plurality of resistance members are a plurality of bands, and wherein each said band is a generally flat, continuously circular resilient member.
14. The physical training device of claim 1, wherein said rebounder platform is figure-eight shaped.
15. The physical training device of claim 1, wherein said rebounder platform is oval shaped.
16. The physical training device of claim 1, wherein said plurality of resistance members are permanently fastened to said rebounder platform.
17. The physical training device of claim 1, wherein said plurality of resistance members are selected from the group consisting of bands, cords, pulley arrangements, or weighted members.
18. The physical training device of claim 1, wherein said rebounder platform further comprises one or more accessory features selected from the group consisting of a countdown timer, a clock, a speaker, a sound generator, or an aroma dispenser.
19. The physical training device of claim 1, wherein said rebounder platform is foldably portable.
20. The physical training system of claim 4, wherein said foam element further comprises memory foam.