All The Claims

1) A method for reducing soft errors in logic comprising:
a) obtaining a first delayed data signal;
b) obtaining a second delayed data signal;
c) applying a data signal from a logic circuit, the delayed data signals, and a clock signal to a triple redundant memory element;
d) such that the time delay of the first delayed data signal is equal to or greater than the pulse width of a soft error event occurring in the logic circuit;
e) such that the time delay of the second delayed data signal is equal to or greater than half the pulse width of a soft error event occurring in the logic circuit.
2) The method as in claim 1 wherein the delayed data signals are obtained by fabricating a chain of inverters in series.
3) The method as in claim 1 wherein the delayed data signals are obtained by fabricating one or more capacitors and one or more resistors in a pi-network.
4) The method as in claim 1 wherein the triple redundant memory element comprises:
a) three memory elements;
b) a majority voting logic circuit;
c) wherein an output from each memory element is connected to a separate input of the majority voting logic circuit;
d) wherein the clock signal is connected to all three memory elements;
e) wherein the data signal is connected to the first memory element;
f) wherein the first delayed data signal is connected to the third memory element;
g) wherein the second delayed data signal is connected to the second memory element.
5) The method as in claim 4 wherein the memory elements are DRAMs.
6) The method as in claim 4 wherein the memory elements are SRAMs.
7) The method as in claim 4 wherein the memory elements are D-type flip-flops.
8) The method as in claim 4 wherein the memory elements are pulsed latches.
9) The method as in claim 4 wherein the majority voting logic circuit comprises:
a) three two-input NANDs;
b) one three-input NAND;
c) wherein each output from the three two-input NANDs are connected to an input of the three-input NAND.
10) The method as in claim 4 wherein the majority voting logic circuit comprises:
a) three two-input ANDs;
b) one three-input OR;
c) wherein each output from the three two-input ANDs are connected to an input of the three-input OR.
11) A circuit for reducing soft errors in logic comprising:
a) a first delay element;
b) a second delay element;
c) a triple redundant memory element;
d) wherein a data signal from a logic circuit is applied to the first delay element, the second delay element, and to a triple redundant memory element;
e) wherein an output from the first delay element is connected to the triple redundant memory element;
f) wherein an output from the second delay element is connected to the triple redundant memory element;
g) wherein a clock signal is applied to the triple redundant memory element;
h) such that the time delay of the first delayed data signal is equal to or greater than the pulse width of a soft error event occurring in the logic circuit;
i) such that the time delay of the second delayed data signal is equal to or greater than half the pulse width of a soft error event occurring in the logic circuit.
12) The circuit as in claim 11 wherein the delay elements are a chain of inverters in series.
13) The circuit as in claim 11 wherein the delay elements are one or more capacitors and one or more resistors in a pi-network.
14) The circuit as in claim 11 wherein the triple redundant memory element comprises:
a) three memory elements;
b) a majority voting logic circuit;
c) wherein an output from each memory element is connected to a separate input of the majority voting logic circuit;
d) wherein the clock signal is connected to all three memory elements;
e) wherein the data signal is connected to the first memory element;
f) wherein the first delayed data signal is connected to the third memory element;
g) wherein the second delayed data signal is connected to the second memory element.
15) The circuit as in claim 14 wherein the memory elements are DRAMs.
16) The circuit as in claim 14 wherein the memory elements are SRAMs.
17) The circuit as in claim 14 wherein the memory elements are D-type flip-flops.
18) The circuit as in claim 14 wherein the memory elements are pulsed latches.
19) The circuit as in claim 14 wherein the majority voting logic circuit comprises:
a) three two-input NANDs;
b) one three-input NAND;
c) wherein each output from the three two-input NANDs are connected to an input of the three-input NAND.
20) The circuit as in claim 4 wherein the majority voting logic circuit comprises:
a) three two-input ANDs;
b) one three-input OR;
c) wherein each output from the three two-input ANDs are connected to an input of the three-input OR.
21) A circuit for reducing soft errors in logic comprising:
a) a first means for delaying a data signal;
b) a second means for delaying a data signal;
c) a means for storing a logical value in three distinct locations;
d) a means for outputting a same logical value as is present on two of the three inputs;
e) wherein a data signal is applied to the first means for delaying a data signal, the second means for delaying a data signal, and to a first location of the means for storing a logical value in three distinct locations;
f) wherein a clock signal is applied to the means for storing a logical value in three distinct locations;
g) such that the time delay through the first means for delaying a data signal is greater than the pulse width of a soft error event occurring in the logic circuit;
h) such that the time delay through the second means for delaying a data signal is greater than half the pulse width of a soft error event occurring in the logic circuit.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A resonator of a hybrid laser diode comprising:
a substrate including a semiconductor layer where a hybrid waveguide, a multi-mode waveguide, and a single mode waveguide are connected in series;
a compound semiconductor waveguide, provided on the hybrid waveguide of the semiconductor layer, having a tapered coupling structure at one end of the compound semiconductor waveguide, the tapered coupling structure overlapping the multi-mode waveguide partially; and
a reflection part provided on one end of the single mode waveguide,
wherein the multi-mode waveguide has a narrower width than the hybrid waveguide and the single mode waveguide has a narrower width than the multi-mode waveguide.
2. The resonator of claim 1, wherein the compound semiconductor waveguide has a width of more than about 5 \u03bcm.
3. The resonator of claim 1, wherein the compound semiconductor waveguide comprises a Group III-V compound semiconductor.
4. The resonator of claim 1, wherein the substrate is a silicon on insulator (SOI) substrate including an underlying semiconductor layer, an insulation layer on the underlying semiconductor layer, and the semiconductor layer on the insulation layer.
5. The resonator of claim 4, wherein the compound semiconductor waveguide is formed by bonding with the semiconductor layer of the substrate.
6. The resonator of claim 1, further comprising a mode selecting unit provided between the multi-mode waveguide and the single mode waveguide.
7. The resonator of claim 6, wherein the mode selecting unit is a multi-mode interference waveguide.
8. The resonator of claim 1, wherein the reflection part uses a distributed Bragg reflector or a facet reflection, the disturbed Bragg reflector being a waveguide with diffraction gratings.
9. The resonator of claim 1, wherein the hybrid waveguide, the multi-mode waveguide, and the single mode waveguide are connected in series through respective transition area waveguides therebetween.
10. The resonator of claim 9, wherein the transition area waveguide has a width that becomes narrower when it approaches from the hybrid waveguide to the multi-mode waveguide and from the multi-mode waveguide to the single mode waveguide.

1. A loudspeaker system comprising:
a first pair of transducer assemblies including a first transducer assembly having a front side and a back side and a second transducer assembly having a front side and a back side;
an enclosure supporting the first and second transducer assemblies and having an internal volume;
the first transducer assembly being supported on the enclosure to radiate sound energy from its front side directly into the internal volume;
the second transducer assembly being supported on the enclosure to radiate sound energy into the internal volume from its back side; and
the first and second transducer assemblies being oriented with respect to one another such that the back side of the first transducer is partially nested in the front side of the second transducer, the respective front and back sides being spaced and open to the environment along a part of an edge thereof.
2. The loudspeaker system as set forth in claim 1, further comprising the first transducer assembly being canted with respect to the second transducer assembly.
3. The loudspeaker system as set forth in claim 2, further comprising a port from the internal volume.
4. The loudspeaker system as set forth in claim 3, further comprising the first and second transducer assemblies being set one each in legs of a narrow V indent extending into the enclosure from a side thereof.
5. The loudspeaker system as set forth in claim 4, further comprising:
a audio frequency driver connected to the first pair of transducers for energizing the first and second transducers in phase with one another, and
the acoustic centers of the first and second transducers being spaced by no more than one quarter of a wavelength of sound energy at a design limit frequency.
6. The loudspeaker system as set forth in claim 4, further comprising:
a second pair of transducer assemblies including a third transducer assembly supported on the enclosure to radiate sound energy from its front side directly into the internal volume and a fourth transducer assembly supported on the enclosure to radiate sound energy into the internal volume from its back side; and
the third and fourth transducer assemblies being oriented with respect to one another such that the back side of the first transducer is partially nested in the front side of the second transducer, the respective front and back sides being spaced and open to the environment along a part of an edge thereof.
7. The loudspeaker system of claim 6, further comprising:
the third and fourth transducer assemblies being set one each in legs of a narrow V indent extending into the enclosure from a side thereof.
8. The loudspeaker system of claim 7, further comprising:
an audio driver coupled to energize the third and fourth transducer assemblies in phase with one another with the acoustic centers of the transducer assemblies of the second pair of transducer assemblies being spaced by no more than one quarter of a wavelength of sound energy radiated at a design limit frequency.
9. The loudspeaker system of claim 8, wherein the first and second pairs of transducers are axially aligned on the centers of one of the transducer assemblies of each pair of transducer assemblies and the first and second pairs of transducer assemblies have the same design limit frequency.
10. The loudspeaker system of claim 9, further comprising:
a common source for an energization signal for the first and second pairs of transducers; and
a timing differentiation element for introducing phase differentiation in the sound energy produced by the first pair of transducer assemblies and the second pair of transducer assemblies.
11. The loudspeaker system of claim 10, where the timing differentiation element controls phase differentiation as a function of the frequency of the energization signed.
12. A loudspeaker system comprising:
an enclosure having a front face and enclosing an interior volume;
a first pair of substantially opposed baffle boards having inside and outside edges, the outside edges of the baffle boards being located across a gap in the front face and the inside edges meeting along an axis parallel to the front face;
a first diaphragm loudspeaker mounted on a first of the first pair of substantially opposed baffle boards oriented to have a front face directed into the interior volume;
a second diaphragm loudspeaker mounted on a second of the first pair of substantially opposed baffle boards oriented to have a front face substantially directed into a back face of the first diaphragm loudspeaker and partially oriented toward the gap in the front face; and
a port from the interior volume.
13. The loudspeaker system of claim 12, further comprising:
the first and second diaphragm loudspeakers being spaced apart at their respective acoustic center points by no more than a quarter wavelength of radiated sound energy at a design frequency; and
an acoustic driver coupled to the energize the first and second diaphragm loudspeakers in phase with one another.
14. The loudspeaker system of claim 13, further comprising:
a second pair of substantially opposed baffle boards having inside and outside edges, the outside edges of the baffle boards being located across a gap in the front face and the inside edges meeting along an axis parallel to the front face;
a third diaphragm loudspeaker mounted on a first of the second pair of substantially opposed baffle boards oriented to have a front face directed into the interior volume; and
a fourth diaphragm loudspeaker mounted on a second of the second pair of substantially opposed baffle boards oriented to have a front face substantially directed into a back face of the first diaphragm loudspeaker and partially oriented toward the gap in the front face.
15. The loudspeaker system of claim 14, further comprising:
the third and fourth diaphragm loudspeakers being spaced apart at their respective acoustic center points by no more than a quarter wavelength of radiated sound energy at a design frequency; and
an acoustic driver coupled to the energize the third and fourth diaphragm loudspeakers in phase with one another.
16. The loudspeaker system of claim 15, wherein a signal from the acoustic driver for application to the third and fourth diaphragm loudspeakers is delayed respective the signal for the first and second diaphragm loudspeakers.
17. The loudspeaker system of claim 16, wherein the delay is selectable to control the direction of a lobe of sound energy radiated by the loudspeaker system.
18. The loudspeaker system of claim 15, wherein the delay is a function of dominant frequency of the signal from the acoustic driver.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. An optocoupler package, comprising:
first and second input signal terminals;
first and second output terminals;
third and fourth output terminals;
a layer of dielectric optically semi-reflective and transmissive material having an upper surface and a lower surface;
a light emitting diode (LED) operably connected to the first and second input signal terminals and configured to emit infrared or near-infrared light in proportion to at least one predetermined characteristic of the input signals;
a first photodetector operably connected to the first and second output terminals and configured to provide LED feedback control signals thereacross, and
a second photodetector operably connected to the third and fourth output terminals and configured to provide isolated output signals thereacross;
wherein the LED and the first photodetector are both located above the upper surface of the layer of dielectric semi-reflective material, the second photodetector is located beneath the lower surface of the layer of dielectric semi-reflective material, and the layer of dielectric semi-reflective material is configured to reflect a first portion of light generated by the LED and incident upon the upper surface thereof towards the first photodetector thereby to provide the feedback control signals therefrom and to transmit a second portion of light generated by the LED through the upper and lower surfaces thereof for detection by the second photodetector thereby to provide the isolated output signals therefrom.
2. The optocoupler of claim 1, wherein the LED and the first photodetector are operably connected to a first lead frame.
3. The optocoupler of claim 2, wherein the first lead frame comprises the first and second input signal terminals and the first and second output terminals.
4. The optocoupler of claim 1, wherein the second photodetector is operably connected to a second lead frame.
5. The optocoupler of claim 4, wherein the second lead frame comprises the third and fourth output terminals.
6. The optocoupler of claim 1, wherein at least one of the first and second photodetectors is a photo diode, a bipolar detector transistor, and a Darlington detector transistor.
7. The optocoupler of claim 1, wherein the LED is one of an AlGaAs LED, an ACE AlGaAs LED, a DPUP AlGaAs LED, and a GaAsP LED.
8. The optocoupler of claim 1, wherein the optocoupler further comprises a molding compound that at least partially surrounds or encases a plurality of the terminals and portions of the layer of dielectric optically semi-reflective and transmissive material.
9. The optocoupler of claim 8, wherein the molding compound comprises plastic.
10. The optocoupler of claim 1, wherein the optocoupler is an 8-pin DIP package.
11. The optocoupler of claim 1, wherein the layer of dielectric optically semi-reflective and transmissive material is at least partially polymeric.
12. The optocoupler of claim 1, wherein the layer of dielectric optically semi-reflective and transmissive material is a film.
13. The optocoupler of claim 12, wherein the film is at least partially polymeric.
14. The optocoupler of claim 13, wherein the at least partially polymeric film is a multi-layer optical film.
15. The optocoupler of claim 14, wherein the multi-layer optical film is a selective wavelength mirror multi-layer optical film.
16. The optocoupler of claim 12, wherein the film comprises between about 100 layers and about 1,000 layers.
17. The optocoupler of claim 16, wherein each of the layers ranges between about 10 nanometers and about 200 nanometers in thickness.
18. The optocoupler of claim 1, wherein the LED feedback control signals are employed to regulate and control the output of the LED.
19. The optocoupler of claim 1, wherein the at least one predetermined characteristic includes at least one of input signal amplitude, phase and frequency.
20. A method of operating an optocoupler package, comprising:
providing input signals across first and second input signal terminals of an LED included in the optocoupler package;
generating and emitting, on the basis of the input signals, infrared or near-infrared light signals with the LED;
reflecting a first portion of light generated by the LED and incident upon an upper surface of a layer of dielectric semi-reflective material towards a first photodetector thereby to generate and provide LED feedback control signals therefrom, the LED and the first photodetector being located above the upper surface;
transmitting a second portion of light generated by the LED through the upper surface and an opposing lower surface of the layer of dielectric semi-reflective material towards a second photodetector thereby to generate and provide isolated output signals therefrom, the second photodetector being located beneath the lower surface.
21. The method of claim 20, wherein at least one of the first and second photodetectors is a photo diode, a bipolar detector transistor, and a Darlington detector transistor.
22. The method of claim 20, wherein the LED is one of an AlGaAs LED, an ACE AlGaAs LED, a DPUP AlGaAs LED, and a GaAsP LED.
22. The method of claim 20, wherein the optocoupler is an 8-pin DIP package.
23. The method of claim 20, wherein the layer of dielectric optically semi-reflective and transmissive material is at least partially polymeric.
24. The method of claim 20, wherein the layer of dielectric optically semi-reflective and transmissive material is a film.
25. The method of claim 24, wherein the film is at least partially polymeric.
26. The method of claim 25, wherein the at least partially polymeric film is a multi-layer optical film.
27. The method of claim 26, wherein the multi-layer optical film is a selective wavelength mirror multi-layer optical film.
28. The method of claim 24, wherein the film comprises between about 100 layers and about 1,000 layers.
29. The method of claim 28, wherein each of the layers ranges between about 10 nanometers and about 200 nanometers in thickness.
30. The method of claim 20, further comprising regulating and controlling the output of the LED using the LED feedback control signals.