All The Claims

1. A shift register, comprising:
cascade-connected unit circuits, each of which includes a thin-film transistor which includes a source electrode, a drain electrode, and a gate electrode, wherein
the thin-film transistor is a bottom gate thin-film transistor which includes a comb-shaped sourcedrain structure,
the source electrode includes a source trunk portion and a plurality of source branch portions which are branched from the source trunk portion and which correspond to teeth of a comb,
the drain electrode includes a drain trunk portion and a plurality of drain branch portions which are branched from the drain trunk portion and which correspond to teeth of a comb,
the source electrode and the drain electrode face each other,
the plurality of source branch portions and the plurality of drain branch portions are alternatingly arranged,
the gate electrode is provided with at least one of a cut and an opening in at least one of a region overlapping with the source electrode and a region overlapping with the drain electrode, and
the at least one of the cut and the opening faces at least one of the plurality of source branch portions and the plurality of drain branch portions.
2. The shift register according to claim 1,
wherein the cascade-connected unit circuits each include a clock terminal into which a clock signal is fed and an output terminal through which an output signal is sent out, and
the shift register includes an output transistor disposed between the clock terminal and the output terminal, the output transistor switching passage and cutout of the clock signal according to a gate potential.
3. The shift register according to claim 2,
wherein the thin-film transistor is the output transistor, and
the at least one of a cut and an opening is defined in a region overlapping with one electrode connected to the clock terminal, the one electrode being selected from the source electrode and the drain electrode.
4. The shift register according to claim 3,
wherein the gate electrode is provided with no cut and no opening in a region overlapping with one electrode selected from the source electrode and the drain electrode, the one electrode being connected to the output terminal.
5. The shift register according to claim 2,
wherein the thin-film transistor is a transistor arranged to apply a low level voltage to the output terminal at times other than a time of sending of the output signal, and
the at least one of a cut and an opening is defined in a region overlapping with the source electrode and a region overlapping with the drain electrode.
6. The shift register according to claim 2,
wherein the thin-film transistor is a transistor arranged to apply a low level voltage to a node connected to a gate of the output transistor during a period other than a period for turning the output transistor ON, and
the at least one of a cut and an opening is defined in a region overlapping with the source electrode and a region overlapping with the drain electrode.
7. The shift register according to claim 2,
wherein the shift register includes a first transistor in which source or drain is connected to the gate of the output transistor,
the thin-film transistor is a transistor arranged to apply a low level voltage to a node connected to a gate of the first transistor during a period for turning the output transistor ON, and
the at least one of a cut and an opening is defined in a region overlapping with the source electrode and a region overlapping with the drain electrode.
8. The shift register according to claim 2,
wherein the cascade-connected unit circuits each include an input terminal into which a start pulse is fed or an output signal is fed from the previous circuit,
the thin-film transistor is a transistor in which one of a source and a drain is connected to the gate of the output transistor and a gate and the other of the source and the drain are connected to the input terminal,
the at least one of a cut and an opening is defined in a region overlapping with the source electrode and a region overlapping with the drain electrode.
9. The shift register according to claim 1,
wherein the thin-film transistor is made of amorphous silicon.
10. A display device, comprising:
a plurality of pixel circuits arranged in a matrix pattern; and
a driver including the shift register according to claim 1.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. An apparatus for receiving a FEC frame for variable-length frame transmission in a TDMA system, the apparatus comprising:
a first receiver determining whether a received frame is a FEC encoded frame, wherein when the received frame is a FEC encoded frame having a predetermined number of message blocks and parities equal in number to the message blocks sequentially, the first receiver divides the FEC encoded frame into the message blocks and parities after removing a FEC frame identifier from the FEC encoded frame, the first receiver includes a data buffer and a parity buffer respectively storing the message blocks and the parities;
a Reed-Solomon decoder receiving the FEC encoded frame from the first receiver, and Reed-Solomon decoding the FEC encoded frame in a same processing time regardless of the length of the FEC encoded frame, wherein the Reed-Solomon decoder calculates an error magnitude polynomial to determine an error value of the FEC encoded frame, the Reed-Solomon decoder buffers an error magnitude polynomial in a first buffer and an error location polynomial in a second buffer to determine an error value of the FEC encoded frame, the Reed-Solomon decoder further comprising:
a syndrome calculator calculating a syndrome for each of the codewords,
a codeword counter counting the length of the codewords,
the error location polynomial generator receiving the syndrome calculated by the syndrome calculator, and generating an error location polynomial and the error magnitude polynomial using a recursive modified Euclid algorithm,
an error location detection unit searching for a location of the error of the codeword using the Chien algorithm based on initial values of the lengths of codewords,
an error magnitude detection unit searching for the magnitude of the error of the codeword using the Forney algorithm based on the initial values, and
a memory comprising a first queue storing the error location polynomial output from the error location polynomial generator, and a second queue storing the error magnitude polynomial output from the error location polynomial generator, and storing the error location polynomial and the error magnitude polynomial until the error location detection unit and the error magnitude detection unit complete to process a previous codeword for output;

a matching delay receiving an input FEC unencoded frame from the first receiver, and delaying the FEC unencoded frame by the time required to decode a FEC encoded frame, or delaying a FEC frame identifier by the time required to decode a FEC encoded frame; and
a frame recombiner adding a Reed-Solomon decoded codeword to the FEC frame identifier in response to the output from the matching delay to form an original FEC frame.
2. The apparatus of claim 1, wherein the data buffer and the parity buffer are elastic buffers that provide each of the received frames with the same delay time.
3. The apparatus of claim 1, wherein the Reed-Solomon decoder further comprises:
a look-up table storing the initial values each in the error location detection unit and the error magnitude detection unit, and outputting the initial values in the codeword counter using them as addresses for outputting to the error location detection unit and the error magnitude detection unit.
4. The apparatus of claim 3, wherein the memory further comprises a third queue queuing the codeword.
5. The apparatus of claim 1, further comprising:
a buffer that delays the received frame by a time required to perform the Reed-Solomon decoding, resulting in an error corrected frame; and
wherein the frame recombiner zero-pads a position in the error corrected frame corresponding to a parity storing space.
6. A method of receiving a FEC frame structure for variable-length frame transmission in a TDMA system, the method comprising:
determining whether a received frame is a FEC encoded frame;
when the received frame is determined to be a FEC encoded frame having a predetermined number of message blocks and parities equal in number to the message blocks sequentially, removing a FEC frame identifier from the FEC encoded frame and dividing the FEC encoded frame into the message blocks and parities;
Reed-Solomon decoding the FEC encoded frame with a fixed processing time regardless of its length, wherein the Reed-Solomon decoding comprises buffering an error magnitude polynomial and an error location polynomial to determine an error value of the FEC encoded frame, wherein the Reed-Solomon decoding comprises:
buffering the divided message blocks and parities for the same time for every frame,
calculating a syndrome of codewords,
counting the length of the codewords,
generating an error location polynomial and the error magnitude polynomial using a recursive modified Euclid algorithm on the syndrome, and
queuing the error location polynomial and the error magnitude polynomial until generating the error location polynomial and the error magnitude polynomial with respect to a previous codeword,
determining a location of an error of the codeword using the Chien algorithm based on initial values selected from a predetermined look-up table according to the length of the codeword; and
determining a magnitude of the error of the codeword using the Forney algorithm based on the initial values;

delaying the received frame by the time required to decode a FEC encoded frame when the received frame is determined to be a FEC unencoded frame, or delaying a FEC frame identifier by the time required to perform the Reed-Solomon decoding; and
adding a Reed-Solomon decoded codeword and the delayed FEC frame identifier in response to delaying the FEC frame identifier to form an original FEC frame.
7. The method of claim 6, wherein the determining location of the error of the codeword further comprises:
configuring the look-up table storing the initial values each in order for the error location detection and the error magnitude detection, and using the length of the codeword as an address in order to generate the initial values.
8. The method of claim 6, wherein the delaying the FEC frame identifier comprises:
zero-padding a position in the frame corresponding to a parity storing space.

1. A seed of the hybrid corn variety CH848055, produced by crossing a first plant of variety CV252827 with a second plant of variety CV596742, wherein representative seed of said varieties CV252827 and CV596742 have been deposited under ATCC Accession numbers PTA-10192 and PTA-______, respectively.
2. A plant of the hybrid corn variety CH848055 grown from the seed of claim 1.
3. A plant part of the plant of claim 2.
4. The plant part of claim 3, further defined as an ear, ovule, pollen or cell.
5. A tissue culture of cells of the plant of claim 2.
6. The tissue culture of claim 5, wherein cells of the tissue culture are from a tissue selected from the group consisting of leaf, pollen, embryo, root, root tip, anther, silk, flower, kernel, ear, cob, husk, stalk and meristem.
7. The seed of claim 1, further comprising a transgene.
8. The seed of claim 7, wherein the transgene confers a trait selected from the group consisting of male sterility, herbicide tolerance, insect resistance, disease resistance, waxy starch, modified fatty acid metabolism, modified phytic acid metabolism, modified carbohydrate metabolism and modified protein metabolism.
9. The plant of claim 2, further comprising a transgene.
10. A method of producing hybrid corn seed comprising crossing a plant of variety CV252827 with a plant of variety CV596742, wherein representative seed of variety CV252827 and variety CV596742 have been deposited under ATCC Accession numbers PTA-10192 and PTA-______, respectively.
11. The method of claim 10, wherein the plant of inbred variety CV252827 is pollinated with pollen from a plant of variety CV596742.
12. The method of claim 10, wherein the plant of inbred variety CV596742 is pollinated with pollen from a plant of variety CV252827.
13. A method of introducing a heritable trait into hybrid corn variety CH848055 comprising the steps of:
(a) introducing at least a first heritable trait into at least one inbred corn variety selected from the group consisting of variety CV252827 and variety CV596742 to produce a plant of the first inbred corn variety that heritably carries the trait, wherein the heritable trait is introduced into said first inbred corn variety by backcrossing and wherein representative samples of seed of variety CV252827 and variety CV596742 have been deposited under ATCC Accession numbers PTA-10192 and PTA-______, respectively; and
(b) crossing a plant of the first inbred corn variety that heritably carries the trait with a plant of a different variety selected from said group consisting of CV252827 and CV596742 to produce a plant of hybrid corn variety CH848055 comprising the heritable trait.
14. The method of claim 13, wherein the trait is selected from the group consisting of male sterility, herbicide tolerance, insect resistance, disease resistance, waxy starch, modified fatty acid metabolism, modified phytic acid metabolism, modified carbohydrate metabolism and modified protein metabolism.
15. The method of claim 14, further comprising repeating step (a) at least once to introduce at least a second heritable trait into hybrid corn variety CH848055, wherein the second heritable trait is selected from the group consisting of male sterility, herbicide tolerance, insect resistance, disease resistance, waxy starch, modified fatty acid metabolism, modified phytic acid metabolism, modified carbohydrate metabolism and modified protein metabolism.
16. A plant produced by the method of claim 13.
17. A seed that produces the plant of claim 16.
18. A method of introducing a trait into hybrid corn variety CH848055 comprising the steps of:
(a) introducing a transgene conferring the trait into a variety selected from the group consisting of CV252827 and CV596742 to produce a transgenic plant heritably carrying the trait, wherein representative samples of seed of variety CV252827 and variety CV596742 have been deposited under ATCC Accession numbers PTA-10192 and PTA-______, respectively; and
(b) crossing the transgenic plant or an isogenic progeny plant thereof with a plant of a different variety selected from the group consisting of CV252827 and CV596742 to produce a plant of the hybrid corn variety CH848055 that comprises the trait.
19. The method of claim 18, wherein the desired trait is selected from the group consisting of male sterility, herbicide tolerance, insect resistance, disease resistance, waxy starch, modified fatty acid metabolism, modified phytic acid metabolism, modified carbohydrate metabolism and modified protein metabolism.
20. The method of claim 18, further comprising repeating step (a) at least once to introduce at least a second trait into hybrid corn variety CH848055, wherein the second trait is selected from the group consisting of male sterility, herbicide tolerance, insect resistance, disease resistance, waxy starch, modified fatty acid metabolism, modified phytic acid metabolism, modified carbohydrate metabolism and modified protein metabolism.
21. A plant produced by the method of claim 18.
22. The plant of claim 21, wherein the plant comprises a trait selected from the group consisting of male sterility, herbicide tolerance, insect resistance, disease resistance, waxy starch, modified fatty acid metabolism, modified phytic acid metabolism, modified carbohydrate metabolism and modified protein metabolism.
23. A method of producing a corn plant derived from the hybrid corn variety CH848055, comprising crossing the plant of claim 2 with a second corn plant to produce a progeny corn plant derived from the hybrid corn variety CH848055.
24. The method of claim 23, further comprising the steps of:
(a) crossing the progeny corn plant derived from the hybrid corn variety CH848055 with itself or a second plant to produce a seed of a progeny plant of a subsequent generation;
(b) growing a progeny plant of a subsequent generation from the seed and crossing the progeny plant of a subsequent generation with itself or a second plant; and
(c) repeating steps (a) and (b) for an additional 3-10 generations to produce a corn plant further derived from the hybrid corn variety CH848055.
25. The method of claim 24, further comprising the step of:
(d) crossing the corn plant further derived from the hybrid corn variety CH848055 with a second, distinct corn plant.
26. A method of producing a commodity plant product comprising obtaining the plant of claim 2 or a part thereof and producing said commodity plant product therefrom.
27. The method of claim 26, wherein the commodity plant product is grain, starch, seed oil, corn syrup or protein.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1.-20. (canceled)
21. A semiconductor element, comprising:
a semi-insulating substrate having a first first-conductivity-type layer selectively on a surface of the semi-insulating substrate;
a first semiconductor layer provided on the semi-insulating substrate and the first first-conductivity-type layer, the first semiconductor layer containing AlxGa1-xN (0\u2266X<1);
a second semiconductor layer provided on the first semiconductor layer, the second semiconductor layer containing AlYGa1-YN (0<Y\u22661 and X<Y)), and conductivity-type of AlYGa1-yN (0<Y\u22661 and X<Y)) not being first-conductivity-type;
a first major electrode connected to the second semiconductor layer;
a second major electrode connected to the second semiconductor layer; and
a control electrode provided on the second semiconductor layer between the first major electrode and the second major electrode, wherein
the first first-conductivity-type layer is provided under the control electrode.
22. The element according to claim 21, wherein a first edge of the first first-conductivity-type layer on a side of the second major electrode is positioned between the control electrode and the second major electrode, when viewed in a direction perpendicular to a major surface of the semi-insulating substrate.
23. The element according to claim 21, further comprising:
a first insulating film provided on the second semiconductor layer except the control electrode, the first major electrode, and the second major electrode; and
a first field plate electrode provided on the first insulating film, wherein
the first field plate electrode is connected to the control electrode, and
a first edge of the first first-conductivity-type layer on the side of the second major electrode is positioned between the first field plate electrode and the second major electrode, when viewed in a direction perpendicular to a major surface of the semi-insulating substrate.
24. The element according to claim 21, further comprising:
a first insulating film provided on the second semiconductor layer except the control electrode, the first major electrode, and the second major electrode; and
a first field plate electrode provided on the first insulating film,
a second insulating film covering the first field plate electrode; and
a second field plate electrode provided on the second insulating film, wherein
the first field plate electrode is connected to the control electrode,
the second field plate electrode is connected to the first major electrode, and a first edge of the first first-conductivity-type layer on the side of the second major electrode is positioned between the second field plate electrode and the second major electrode, when viewed in a direction perpendicular to a major surface of the semi-insulating substrate.
25. The element according to claim 21, wherein at least one of convex parts directed from a side of the second major electrode to a side of the first major electrode is provided at an edge part of the first first-conductivity-type layer on the side of the second major electrode, when viewed in a direction perpendicular to a major surface of the semi-insulating substrate.
26. The element according to claim 21, further comprising a gate insulating film provided between the second semiconductor layer and the control electrode.
27. The element according to claim 21, wherein the semi-insulating substrate is made of silicon.
28. The element according to claim 27, wherein
another first first-conductivity-type layer is provided on the surface of the semi-insulating substrate other than the first first-conductivity-type layer, and
at least one of second first-conductivity-type layers is provided selectively on the surface of the semi-insulating substrate in a part sandwiched by the first first-conductivity-type layer and the another first first-conductivity-type layer.
29. The element according to claim 28, wherein an impurity concentration in the second first-conductivity-type layer is lower than an impurity concentration in the first first-conductivity-type layer.
30. The element according to claim 27, wherein
a second-conductivity-type layer is provided on a second major surface opposite to a first major surface of the semi-insulating substrate, the first first-conductivity-type layer is provided on the first major surface of the semi-insulating substrate, and
the second-conductivity-type layer is electrically connected to the second major electrode.
31. The element according to claim 28, wherein at least one of third first-conductivity-type layers is provided selectively on the surface of the semi-insulating substrate except a region, and the first first-conductivity-type layer or the second first-conductivity-type layers is provided in the region.
32. The element according to claim 31, wherein the second semiconductor layer is not provided on the at least one of third first-conductivity-type layers.
33. The element according to claim 31, wherein a device separation layer is provided on the first semiconductor layer on the at least one of third first-conductivity-type layers.