All The Claims

1. A magnetic junction for use in a magnetic device comprising:
a pinned layer;
a nonmagnetic spacer layer; and
a free layer having a magnetic anisotropy, the nonmagnetic spacer layer residing between the pinned layer and the free layer, at least a portion of the magnetic anisotropy being a biaxial anisotropy;
wherein the magnetic junction is configured such that the free layer is switchable between a plurality of stable magnetic states when a write current is passed through the magnetic junction.
2. The magnetic junction of claim 1 wherein the magnetic anisotropy includes a uniaxial anisotropy and the biaxial anisotropy.
3. The magnetic junction of claim 2 wherein the uniaxial anisotropy corresponds to an easy axis, wherein the magnetic anisotropy corresponds to a magnetic anisotropy energy having at least one minimum at an angle from the easy axis.
4. The magnetic junction of claim 3 wherein the angle is nonzero.
5. The magnetic junction of claim 4 wherein the angle is at least ten and not more than forty-five degrees.
6. The magnetic junction of claim 5 wherein the angle is at least twenty and not more than forty degrees.
7. The magnetic junction of claim 2 wherein an absolute value of the uniaxial anisotropy is greater than an absolute value of the biaxial anisotropy.
8. The magnetic junction of claim 1 wherein the biaxial anisotropy is crystalline-induced.
9. The magnetic substructure of claim 8 wherein the free layer includes at least one of LaSrMnO3, GaAs, MnAs, MnAl, Nd2Fe14B, Ho2Fe14B, NdFeB, Fe, FeCo, YCo5, CoOFe2O3, .FeO\u2014Fe2O3, MnO\u2014Fe2O3, NiO\u2014Fe2O3, MgO\u2014Fe2O3,
10. The magnetic junction of claim 1 wherein the biaxial anisotropy is structure-induced.
11. The magnetic junction of claim 10 wherein the free layer has a saturation magnetization and a crystalline anisotropy energy coefficient, the saturation magnetization increasing in a first direction, the crystalline anisotropy energy coefficient increasing in a second direction opposite to the first direction.
12. The magnetic junction of claim 11 wherein the free layer is substantially in a plane and the first direction is substantially perpendicular to the plane.
13. The magnetic junction of claim 12 wherein the free layer includes a plurality of sublayers, each of the plurality of layers having a sublayer saturation magnetization and a sublayer crystalline anisotropy energy coefficient, the sublayer saturation magnetization contributing to the saturation magnetization such that the saturation magnetization increases in the first direction, the sublayer crystalline anisotropy energy coefficient contributing to the crystalline anisotropy energy coefficient such that the crystalline anisotropy energy coefficient increases in the second direction.
14. The magnetic junction of claim 1 wherein the biaxial anisotropy is magnetostriction induced.
15. The magnetic junction of claim 1 wherein the nonmagnetic spacer layer is a tunneling barrier layer.
16. The magnetic junction of claim 1 wherein the nonmagnetic spacer layer is a conductive spacer layer.
17. The magnetic junction of claim 1 wherein the pinned layer includes a reference layer, a spacer layer, and a fixed magnetization layer, the spacer layer residing between the reference layer and the fixed magnetization layer.
18. The magnetic junction of claim 1 wherein the free layer includes a perpendicular anisotropy energy and an out-of-plane demagnetization energy, the out-of-plane demagnetization energy being less than the perpendicular anisotropy energy.
19. The magnetic junction of claim 18 wherein the pinned layer includes a pinned layer perpendicular anisotropy energy and a pinned layer out-of-plane demagnetization energy, the pinned layer out-of-plane demagnetization energy being less than the pinned layer perpendicular anisotropy energy.
20. The magnetic junction of claim 1 wherein the free layer includes a perpendicular anisotropy energy and a out-of-plane demagnetization energy, the out-of-plane demagnetization energy being greater than or equal to the perpendicular anisotropy energy.
21. The magnetic junction of claim 1 further comprising:
an additional pinned layer; and
an additional nonmagnetic spacer layer, the additional nonmagnetic spacer layer residing between the free layer and the additional pinned layer.
22. The magnetic junction of claim 21 wherein at least one of the nonmagnetic spacer layer and the additional nonmagnetic spacer layer includes crystalline MgO.
23. A magnetic junction for use in a magnetic device comprising:
a pinned layer;
a nonmagnetic spacer layer including crystalline MgO; and
a free layer having a magnetic anisotropy including a uniaxial anisotropy and a biaxial anisotropy, the nonmagnetic spacer layer residing between the pinned layer and the free layer, the uniaxial anisotropy corresponding to an easy axis, the magnetic anisotropy corresponding to a magnetic anisotropy energy having at least one minimum at an angle from the easy axis, the angle being at least ten degrees and not more than twenty degrees, the free layer including a perpendicular anisotropy energy and a out-of-plane demagnetization energy, the out-of-plane demagnetization energy being less than the perpendicular anisotropy energy;
wherein the magnetic junction is configured such that the free layer is switchable between a plurality of stable magnetic states when a write current is passed through the magnetic junction.
24. The magnetic junction of claim 23 further comprising:
an additional pinned layer; and
an additional nonmagnetic spacer layer, the additional nonmagnetic spacer layer residing between the free layer and the additional pinned layer, the additional nonmagnetic spacer layer including MgO.
25. A magnetic memory comprising:
a plurality of magnetic storage cells, each of the plurality of magnetic storage cells including at least one magnetic junction, the at least one magnetic junction including a pinned layer, a nonmagnetic spacer layer, and a free layer having a magnetic anisotropy, the nonmagnetic spacer layer residing between the pinned layer and the free layer, at least a portion of the magnetic anisotropy being a biaxial anisotropy
the at least one magnetic junction being configured to allow the free layer to be switched between a plurality of stable magnetic states when a write current is passed through the magnetic junction.
26. The magnetic memory of claim 25 wherein the magnetic anisotropy includes a uniaxial anisotropy and the biaxial anisotropy.
27. The magnetic memory of claim 26 wherein the uniaxial anisotropy corresponds to an easy axis, wherein the magnetic anisotropy corresponds to a magnetic anisotropy energy having at least one minimum at an angle from the easy axis.
28. The magnetic memory of claim 27 wherein the angle is at least ten and not more than forty-five degrees.
29. The magnetic memory of claim 28 wherein the angle is at least twenty and not more than forty degrees.
30. The magnetic junction of claim 2 wherein an absolute value of the of uniaxial anisotropy is greater than an absolute value of the biaxial anisotropy.
31. The magnetic memory of claim 26 wherein the biaxial anisotropy is at least one of crystalline-induced, structure induced, and magnetostriction induced.
32. The magnetic memory of claim 31 wherein the free layer includes at least one of LaSrMnO3, GaAs, MnAs, MnAl, Nd2Fe14B, Ho2Fe14B, NdFeB, Fe, FeCo, YCo5, CoOFe2O3, .FeO\u2014Fe2O3, MnO\u2014Fe2O3, NiO\u2014Fe2O3, MgO\u2014Fe2O3,
33. The magnetic memory of claim 31 wherein the free layer has a saturation magnetization and crystalline anisotropy energy coefficient, the saturation magnetization increasing in a first direction, the crystalline anisotropy energy coefficient increasing in a second direction opposite to the first direction.
34. The magnetic memory of claim 33 wherein the free layer is substantially in a plane and the first direction is substantially perpendicular to the plane.
35. The magnetic memory of claim 34 wherein the free layer includes a plurality of sublayers, each of the plurality of layers having a sublayer saturation magnetization and a sublayer crystalline anisotropy energy coefficient, the sublayer saturation magnetization contributing to the saturation magnetization such that the saturation magnetization increases in the first direction, the sublayer crystalline anisotropy energy coefficient contributing to the crystalline anisotropy energy coefficient such that the crystalline anisotropy energy coefficient increases in the second direction.
36. The magnetic memory of claim 25 wherein the nonmagnetic spacer layer is a tunneling barrier layer.
37. The magnetic memory of claim 25 wherein the pinned layer includes a reference layer, a spacer layer, and a fixed magnetization layer, the spacer layer residing between the reference layer and the fixed magnetization layer.
38. The magnetic memory of claim 25 wherein the free layer includes a perpendicular anisotropy energy and an out-of-plane demagnetization energy, the out-of-plane demagnetization energy being less than the perpendicular anisotropy energy.
39. The magnetic memory of claim 25 wherein the free layer includes a perpendicular anisotropy energy and a out-of-plane demagnetization energy, the out-of-plane demagnetization energy being greater than or equal to the perpendicular anisotropy energy.
40. The magnetic memory of claim 25 wherein the magnetic junction further includes:
an additional pinned layer; and
an additional nonmagnetic spacer layer, the additional nonmagnetic spacer layer residing between the free layer and the additional pinned layer.
41. The magnetic junction of claim 21 wherein at least one of the nonmagnetic spacer layer and the additional nonmagnetic spacer layer includes crystalline MgO.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A plenum for a bifurcated duct, the plenum comprising:
an outer cylindrical body intersected by a pair of exhaust duct stubs that are configured to be coupled to a corresponding pair of exhaust ducts, the outer cylindrical body including an axial rear end portion; and
an inner body disposed in the axial rear end portion and that increases in diameter in the aft direction, the inner body comprising one of a generally axi-symmetrical inner body or a non-axi-symmetrical inner body.
2. The plenum of claim 1, wherein the inner body and the outer cylindrical body cooperate to form the plenum comprising a seamless unitary plenum.
3. The plenum of claim 1, wherein the inner body is coupled to the outer cylindrical body to form the plenum comprising a plenum assembly.
4. The plenum of claim 1, wherein the outer cylindrical body and the inner body are co-axially disposed.
5. The plenum of claim 1, wherein the generally axi-symmetrical inner body is selected from the group consisting of a generally conical body, a generally elliptical body, a generally frustoconical body, and a generally hemispherical body.
6. The plenum of claim 1, wherein the plenum is configured to be disposed between a diffuser in an exhaust section of a gas turbine engine and the pair of exhaust ducts.
7. The plenum of claim 1, wherein an inner surface of the outer cylindrical body is contoured to define a rounded fillet where intersected by the pair of exhaust duct stubs.
8. The plenum of claim 1, wherein the inner body comprises one of a hollow body, a solid body, or a substantially solid body.
9. A bifurcated duct comprising:
a plenum comprising:
an outer cylindrical body intersected by a pair of exhaust duct stubs, the outer cylindrical body including an axial rear end portion; and
an inner body disposed in the axial rear end portion and that increases in diameter in the aft direction, the inner body comprising one of a generally axi-symmetrical inner body or a non-axi-symmetrical inner body; and

a pair of exhaust ducts coupled to the pair of exhaust duct stubs.
10. The bifurcated duct of claim 9, wherein the plenum comprises a seamless unitary plenum.
11. The bifurcated duct of claim 9, when the plenum comprises a plenum assembly comprising the inner body coupled to the outer cylindrical body.
12. The bifurcated duct of claim 9, wherein the pair of exhaust duct stubs comprises a first exhaust duct stub and a second exhaust duct stub and the pair of exhaust ducts comprises a first exhaust duct and a second exhaust duct, the first exhaust duct stub coupled to the first exhaust duct and the second exhaust duct stub coupled to the second exhaust duct.
13. The bifurcated duct of claim 12, wherein the first exhaust duct stub is coupled to the first exhaust duct with a first air gap therebetween and the second exhaust duct stub is coupled to the second exhaust duct with a second air gap therebetween to define a part of an exhaust eductor system.
14. The bifurcated duct of claim 9, wherein the bifurcated duct comprises a bifurcated exhaust duct for a gas turbine engine.
15. The bifurcated duct of claim 9, wherein the generally axi-symmetrical inner body is selected from the group consisting of a generally conical body, a generally elliptical body, a generally frustoconical body, and a generally hemispherical body
16. An exhaust system for an aircraft comprising:
a gas turbine engine comprising an exhaust section including a diffuser; and
a bifurcated exhaust duct in communication with the diffuser, the bifurcated exhaust duct comprising:
a plenum comprising:
an outer cylindrical body intersected by a pair of exhaust duct stubs, the outer cylindrical body including an axial rear end portion; and
an inner body disposed in the axial rear end portion, that increases in diameter in the aft direction, and comprises one of a generally axi-symmetrical inner body or a non-axi-symmetrical inner body; and

a pair of exhaust ducts in fluid communication with the pair of exhaust duct stubs.
17. The exhaust system of claim 16, wherein the bifurcated exhaust duct comprises a seamless unitary structure.
18. The exhaust system of claim 16, wherein the plenum comprises a seamless unitary plenum or a plenum assembly comprising the inner body coupled to the outer cylindrical body.
19. The exhaust system of claim 16, wherein the pair of exhaust duct stubs comprises a first exhaust duct stub and a second exhaust duct stub and the pair of exhaust ducts comprises a first exhaust duct and a second exhaust duct, the first exhaust duct stub coupled to the first exhaust duct and the second exhaust duct stub coupled to the second exhaust duct.
20. The exhaust system of claim 19, wherein the first exhaust duct stub is coupled to the first exhaust duct with a first air gap therebetween and the second exhaust duct stub is coupled to the second exhaust duct with a second air gap therebetween to define a part of an exhaust eductor system of the gas turbine engine.

1. A manufacturing apparatus for processing substrates, comprising:
a process chamber;
a process fluid supply unit including a fluid supply line, and a showerhead disposed at an upper portion of the process chamber and to which the fluid supply line is connected whereby the showerhead injects fluid fed through the fluid supply line into the process chamber; and
a plasma supply unit including a remote plasma reactor disposed outside of the process chamber, and a plasma supply line connected to the remote plasma reactor and to the process chamber, the plasma supply line having an open end disposed at the upper portion of the process chamber such that plasma generated by the remote plasma reactor is injected downward into the process chamber from the upper portion of the process chamber.
2. The manufacturing apparatus according to claim 1, wherein the process fluid supply unit further includes a diffuser disposed in the showerhead to diffuse gas fed through the process fluid supply line throughout the showerhead before the gas is injected by the showerhead into the process chamber.
3. The manufacturing apparatus according to claim 2, wherein the diffuser consists of a plate having passageways extending straight therethrough.
4. The manufacturing apparatus according to claim 3, wherein the process chamber comprises a lid forming the top thereof, and the showerhead of the process supply unit is mounted to the lid of the process chamber.
5. The manufacturing apparatus according to claim 4, wherein the end of the plasma supply line of the plasma supply unit is attached to the lid of the process chamber along with the showerhead.
6. The manufacturing apparatus according to claim 5, wherein the plasma supply line is a waveguide.
7. A manufacturing apparatus for processing substrates, comprising:
a process chamber;
a process fluid supply unit including a process gas supply source having at least one source of gas used in the processing of a substrate within the process chamber, a fluid supply line, and a showerhead disposed at an upper portion of the process chamber and to which the fluid supply line is connected whereby the showerhead injects fluid fed through the fluid supply line from the process gas supply source into the process chamber; and
a plasma supply unit including a remote plasma reactor disposed outside of the process chamber, and a plasma supply line connected to the remote plasma reactor and to the process chamber, the plasma supply line having an open end disposed at the upper portion of the process chamber such that plasma generated by the remote plasma reactor is injected downward into the process chamber from the upper portion of the process chamber.
8. The manufacturing apparatus according to claim 7, wherein the process chamber comprises a lid forming the top thereof, and the showerhead of the process supply unit is mounted to the lid of the process chamber.
9. The manufacturing apparatus according to claim 8, wherein the end of the plasma supply line of the plasma supply unit is attached to the lid of the process chamber along with the showerhead.
10. The manufacturing apparatus according to claim 9, wherein the process fluid supply unit further includes a diffuser disposed in the showerhead to diffuse gas fed through the process fluid supply line throughout the showerhead before the gas is injected by the showerhead into the process chamber.
11. The manufacturing apparatus according to claim 10, wherein the diffuser consists of a plate having passageways extending straight therethrough.
12. The manufacturing apparatus according to claim 11, wherein the plasma supply line is a waveguide.
13. The manufacturing apparatus according to claim 7, further comprising:
an upper electrode disposed in the process chamber;
a lower electrode disposed below the upper electrode in the process chamber; and
RF power supplies connected to the electrodes, respectively.
14. The manufacturing apparatus according to claim 11, wherein the process gas supply source includes a source of TEOS.
15. A substrate processing method comprising:
supporting a substrate in a lower portion of a process chamber;
subsequently injecting a processing medium comprising gas into the process chamber from an upper portion of the process chamber, and processing the substrate using the processing medium;
subsequently cleaning the interior of the process chamber by generating a cleaning plasma outside the process chamber, and injecting the cleaning plasma into the process chamber from the upper portion of the process chamber.
16. The method according to claim 16, wherein the processing of the substrate using the processing medium comprises exciting the process gas within the process chamber to convert the process gas into a plasma within the process chamber.
17. The method according to claim 15, wherein the injecting of the processing medium into the process chamber comprises delivering the processing medium into a showerhead disposed at the upper portion of the process chamber, and the injecting of the cleaning plasma into the process chamber also comprises delivering the cleaning plasma into the showerhead, whereby the cleaning plasma cleans the showerhead in addition to the interior of the process chamber.
18. The method according to claim 17, further comprising diffusing the processing medium in the showerhead by delivering the processing medium onto a diffuser consisting of a plate disposed within the showerhead, the plate having passageways extending straight therethrough, and wherein the cleaning plasma is also delivered to the diffuser, whereby the cleaning plasma cleans the diffuser in addition to the showerhead and the interior of the process chamber.
19. The method according to claim 16, wherein the injecting of the processing medium into the process chamber comprises delivering the processing medium into a showerhead disposed at the upper portion of the process chamber, and the injecting of the cleaning plasma into the process chamber also comprises delivering the cleaning plasma into the showerhead, whereby the cleaning plasma cleans the showerhead in addition to the interior of the process chamber.
20. The method according to claim 15, wherein the injecting of the processing medium into the process chamber comprises delivering TEOS to the showerhead.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A semiconductor integrated circuit comprising:
a phase-locked loop (PLL) circuit configured to generate an oscillation output signal synchronized with a reference clock, the PLL circuit including:
a phase-frequency detector;
a charge pump;
a loop filter;
an oscillator; and
a voltage-to-current converter configured to convert a control voltage output from the loop filter and to control an oscillation frequency of the oscillator into a current;
a plurality of clock and data recovery (CDR) circuits configured to adjust a phase of the oscillation output signal with respect to a phase of serial data; and
a path for distributing the converted current to the plurality of CDR circuits.
2. The semiconductor integrated circuit according to claim 1, wherein each one of the plurality of CDR circuits includes an oscillator having an oscillation frequency that is controlled on the basis of the distributed current.
3. The semiconductor integrated circuit according to claim 1, wherein each one of the plurality of CDR circuits includes a current-to-voltage converter configured to convert the distributed current into a voltage and a voltage-controlled oscillator having an oscillation frequency that is controlled on the basis of the converted voltage.
4. The semiconductor integrated circuit according to claim 1, wherein the PLL circuit includes a current-controlled oscillator whose oscillation frequency is controlled on the basis of the current converted by the voltage-to-current converter.
5. The semiconductor integrated circuit according to claim 1, wherein the PLL circuit includes a voltage-controlled oscillator having an oscillation frequency that is controlled on the basis of the control voltage output from the loop filter.
6. The semiconductor integrated circuit according to claim 1, wherein the voltage-to-current converter includes a comparator configured to compare the control voltage with a predetermined voltage, and a plurality of constant-current power supplies configured to supply currents to the plurality of CDR circuits on the basis of comparison performed by the comparator.
7. The semiconductor integrated circuit according to claim 2, wherein each one of the plurality of CDR circuits includes a phase control block configured to perform adjustment on the basis of the distributed current such that a phase of a clock generated in the oscillator in the CDR circuit is coincident with a phase of the serial data, and a phase detector configured to compare the phases of the adjusted clock and the serial data and control the phase control block.
8. The semiconductor integrated circuit according to claim 7, further comprising:
a deserializer configured to convert the serial data into parallel data by using the adjusted clock output from the CDR circuit.
9. The semiconductor integrated circuit according to claim 2, wherein each one of the plurality of CDR circuits constitutes a fine loop including a phase detector, a charge pump, a loop filter, a voltage-to-current converter, and the oscillator, and the fine loop is configured to perform an adjustment on the basis of the distributed current and a current converted by the voltage-to-current converter in the fine loop such that a phase of a clock generated in the oscillator is coincident with a phase of the serial data.
10. The semiconductor integrated circuit according to claim 9, further comprising:
a deserializer configured to convert the serial data into parallel data by using the adjusted clock output from the CDR circuit.