All The Claims

We claim:

1. A connecting structure comprising:
a driving transmission (11) and a roll (100) connected through it, which driving transmission (11) includes an input shaft (12) in the drive, whereby the drive is transmitted through the input shaft (12) to toothed gears and further to the roll jacket (100a) of the driven roll (100) to rotate this, and which roll (100) includes a central static shaft (100b) and a bearing (G) to support it, wherein in order to allow axial and radial motions of the roll’s (100) roll jacket when the driving transmission (11) is located in the fixed position, a seal (25) including a sliding ring (30) is fitted between the driving transmission (11) and the roll (100).
2. Connecting structure according to claim 1, wherein the drive is transferred through the teeth (13) of the input shaft (12) to a central toothed gear (16) by way of its teeth (16a), from which toothed gear (16) the drive is transferred further to a sleeve shaft (20), whereby the internal teeth (16b) of the toothed gear (16) are functionally connected with the circumferential teeth (21a) of the sleeve shaft (20), and the drive is transmitted further from the sleeve shaft (20) through second outer circumferential teeth (21b) to a flange plate (22), whereby the teeth (23) of the flange plate (22) are functionally connected with the teeth (21b) of the sleeve shaft (20), and in that the flange plate (22) is connected to the roll jacket (100a) of the driven roll (100) rotating it, that the sliding ring (30) is fitted into the body (27) of the seal case, which body is located in the end face of toothed gear (16), and that the sliding ring (30) is located in the seal cavity (28) of seal case (27), which cavity is preferably an annular groove and in its side surfaces includes grooves (U1, U2), in which lateral seals (29a1,29a2) are located and which will be situated against the side surfaces of the sliding ring (30).
3. Connecting structure according to claim 1, wherein a free space (D) remains between the sliding ring (30) and the bottom (t) of the seal cavity (28), in which space lubricantgrease may be placed, whereby when the seal case body (27) is rotating lubricant will be moved with the aid of centrifugal force towards the sliding ring (30) and the seals (29a1,29a2) in order to bring about lubrication between the sliding ring (30) and the structures connected with it.
4. Connecting structure according to claim 1, wherein the sliding ring (30) in a peripheral groove (U3) in its end face includes a seal (31), preferably a rubber seal, which is situated against the stop face (24c1), whereby the stop face (24c1) is located in a ring plate (24) of the flange plate (22) connected with the shaft (100), and the ring plate (24) includes a body part (24a) located at right angles against the central axis (X) of the shaft (100) and a body part (24b) in the direction of the central axis (X), whereby the stop face (24c1) is formed in the body part (24b) and it is chosen so that a sufficient travelling distance is made possible for the axial motion (L2) of the roll’s (100) roll jacket (100a).
5. Connecting structure according to claim 1, wherein the sliding ring (30) is an annular part and it is located in the roll (100) around the shaft (100b), whereby with the aid of the free space (D) in the seal cavity (28) the sliding ring (30) of seal (25) is allowed to move in the radial direction (L1) and radial and axial motions (L1 and L2) of the roll’s (100) roll jacket (100a) are allowed.
6. Connecting structure according to claim 1, wherein a leakage oil space (33) after the seal (25) includes a leakage oil channel (34), through which the leakage oil flow can be observed either visually or by using a measuring device, whereby when the leakage oil flow exceeds a certain predetermined limit value, an alarm indicating the said excess can be given to the machine operator.
7. Connecting structure according to claim 1, wherein the sliding ring (30) is of a plastic material.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method for manufacturing a light emitting diode chip, comprising:
providing a sapphire substrate, the sapphire substrate having a plurality of protrusions on an upper surface thereof;
forming an un-doped GaN layer on the upper surface of the sapphire substrate, the un-doped GaN layer totally covering the protrusions;
forming a plurality of semiconductor islands on an upper surface of the un-doped GaN layer by self-organized growth, gaps being formed between two adjacent semiconductor islands to expose a part of the upper surface of the un-doped GaN layer;
forming an n-type GaN layer on the exposed part of the upper surface of the un-doped GaN layer, the n-type GaN layer being laterally grown to totally cover the semiconductor islands;
forming an active layer on an upper surface of the n-type GaN layer; and
forming a p-type GaN layer on the active layer.
2. The method of claim 1, wherein the semiconductor islands formed by self-organized growth are made of SiNx.
3. The method of claim 2, wherein in the self-organized growth of the semiconductor islands, SiH4 gas and NH3 gas are introduced to the surface of the un-doped GaN layer, and the SiH4 gas reacts with the NH3 gas to form the semiconductor islands made of SiNx.
4. The method of claim 1, wherein the semiconductor islands formed by self-organized growth are made of MgNx.
5. The method of claim 4, wherein in the self-organized growth of the semiconductor islands, Cp2Mg gas and NH3 gas are introduced to the surface of the un-doped GaN layer, and the Cp2Mg gas reacts with the NH3 gas to form the semiconductor islands made of MgNx.
6. The method of claim 1, wherein the semiconductor islands each have a height in a range from 50 nm to 300 nm.
7. The method of claim 6, wherein the semiconductor islands each have a height about 100 nm.
8. The method of claim 1, wherein the semiconductor islands each have a width less than 50 nm.
9. The method of claim 8, wherein the semiconductor islands each have a width about 10 nm.
10. The method of claim 1, wherein the active layer is a multiple quantum well (MQW) layer.
11. A method for manufacturing a light emitting diode chip, comprising:
providing a sapphire substrate, the sapphire substrate having a plurality of protrusions on an upper surface thereof;
forming an un-doped GaN layer on the upper surface of the sapphire substrate, the un-doped GaN layer totally covering the protrusions;
forming a plurality of semiconductor islands on an upper surface of the un-doped GaN layer by self-organized growth, gaps being formed between two adjacent semiconductor islands to expose a part of the upper surface of the un-doped GaN layer;
forming an n-type GaN layer on the exposed part of the upper surface of the un-doped GaN layer, the n-type GaN layer filled in the gaps between two adjacent semiconductor islands and totally covering the semiconductor islands;
forming an active layer on an upper surface of the n-type GaN layer; and
forming a p-type GaN layer on the active layer.
12. The method of claim 11, wherein the semiconductor islands formed by self-organized growth are made of SiNx.
13. The method of claim 12, wherein in the self-organized growth of the semiconductor islands, SiH4 gas and NH3 gas are introduced to the surface of the un-doped GaN layer, and the SiH4 gas reacts with the NH3 gas to form the semiconductor islands made of SiNx.
14. The method of claim 11, wherein the semiconductor islands formed by self-organized growth are made of MgNx.
15. The method of claim 14, wherein in the self-organized growth of the semiconductor islands, Cp2Mg gas and NH3 gas are introduced to the surface of the un-doped GaN layer, and the Cp2Mg gas reacts with the NH3 gas to form the semiconductor islands made of MgNx.
16. The method of claim 11, wherein the semiconductor islands each have a height in a range from 50 nm to 300 nm.
17. The method of claim 16, wherein the semiconductor islands each have a height about 100 nm.
18. The method of claim 11, wherein the semiconductor islands each have a width less than 50 nm.
19. The method of claim 18, wherein the semiconductor islands each have a width about 10 nm.
20. The method of claim 11, wherein the active layer is a multiple quantum well (MQW) layer.

1. A light emitting device comprising:
a first electrode;
a first composite layer over the first electrode;
a second composite layer over the first composite layer; and
a second electrode over the second composite layer,
wherein the first composite layer comprises a first metal, oxygen, and carbon, and the second composite layer comprises a second metal, oxygen, and carbon, and
wherein an average concentration of the first metal in the first composite layer is higher than an average concentration of the second metal in the second composite layer.
2. The light emitting device according to claim 1, wherein the first metal and the second metal are derived from a first metal oxide and a second metal oxide, respectively.
3. The light emitting device according to claim 2, wherein each of the first metal oxide and the second metal oxide is one or plural kinds of titanium oxide, vanadium oxide, chromium oxide, zirconium oxide, niobium oxide, molybdenum oxide, hafnium oxide, tantalum oxide, tungsten oxide, and rhenium oxide.
4. An electronic apparatus comprising the light emitting device according to claim 1.
5. The light emitting device according to claim 1, further comprising:
a third composite layer over the second composite layer, and between the second composite layer and the second electrode,
wherein the third composite layer comprises a third metal, oxygen, and carbon.
6. The light emitting device according to claim 5, wherein the average concentration of the second metal in the second composite layer is higher than an average concentration of the third metal in the third composite layer.
7. The light emitting device according to claim 5, wherein the first metal, the second metal, and the third metal are derived from a first metal oxide, a second metal oxide, and a third metal oxide, respectively.
8. The light emitting device according to claim 7, wherein each of the first metal oxide, the second metal oxide, and the third metal oxide is one or plural kinds of titanium oxide, vanadium oxide, chromium oxide, zirconium oxide, niobium oxide, molybdenum oxide, hafnium oxide, tantalum oxide, tungsten oxide, and rhenium oxide.
9. An electronic apparatus comprising the light emitting device according to claim 5.
10. A light emitting device comprising:
a first electrode;
a first composite layer over the first electrode;
a second composite layer over the first composite layer; and
a second electrode over the second composite layer,
wherein the first composite layer comprises a first metal, oxygen, and carbon, and the second composite layer comprises a second metal, oxygen, and carbon,
wherein an average concentration of the first metal in the first composite layer is higher than an average concentration of the second metal in the second composite layer, and
wherein at least one of the first composite layer and the second composite layer comprises an alternating stack of laminations of a first region and a second region, the first region containing a larger amount of the first or second metal and the second region containing a larger amount of the carbon.
11. The light emitting device according to claim 10, wherein a concentration of the first metal in the first region is equal to or higher than a concentration of the first metal in the second region in the first composite layer.
12. The light emitting device according to claim 10, wherein a highest concentration of the first metal in the first region is the same or at most eight times as a lowest concentration of the first metal in the second region in the first composite layer.
13. The light emitting device according to claim 10, wherein a concentration of the second metal in the first region is equal to or higher than a concentration of the second metal in the second region in the second composite layer.
14. The light emitting device according to claim 10, wherein a highest concentration of the second metal in the first region is the same or at most eight times as a lowest concentration of the second metal in the second region in the second composite layer.
15. The light emitting device according to claim 10, wherein the first metal and the second metal are derived from a first metal oxide and a second metal oxide, respectively.
16. The light emitting device according to claim 15, wherein each of the first metal oxide and the second metal oxide is one or plural kinds of titanium oxide, vanadium oxide, chromium oxide, zirconium oxide, niobium oxide, molybdenum oxide, hafnium oxide, tantalum oxide, tungsten oxide, and rhenium oxide.
17. An electronic apparatus comprising the light emitting device according to claim 10.
18. The light emitting device according to claim 10, further comprising:
a third composite layer over the second composite layer, and between the second composite layer and the second electrode,
wherein the third composite layer comprises a third metal, oxygen, and carbon.
19. The light emitting device according to claim 18, wherein the average concentration of the second metal in the second composite layer is higher than an average concentration of the third metal in the third composite layer.
20. The light emitting device according to claim 18, wherein a concentration of the first metal in the first region is equal to or higher than a concentration of the first metal in the second region in the first composite layer.
21. The light emitting device according to claim 18, wherein a highest concentration of the first metal in the first region is the same or at most eight times as a lowest concentration of the first metal in the second region in the first composite layer.
22. The light emitting device according to claim 18, wherein a concentration of the second metal in the first region is equal to or higher than a concentration of the second metal in the second region in the second composite layer.
23. The light emitting device according to claim 18, wherein a highest concentration of the second metal in the first region is the same or at most eight times as a lowest concentration of the second metal in the second region in the second composite layer.
24. The light emitting device according to claim 18, wherein a concentration of the third metal in the first region is equal to or higher than a concentration of the third metal in the second region in the third composite layer.
25. The light emitting device according to claim 18, wherein a highest concentration of the third metal in the first region is the same or at most eight times as a lowest concentration of the third metal in the second region in the third composite layer.
26. The light emitting device according to claim 18, wherein the first metal, the second metal, and the third metal are derived from a first metal oxide, a second metal oxide, and a third metal oxide, respectively.
27. The light emitting device according to claim 26, wherein each of the first metal oxide, the second metal oxide, and the third metal oxide is one or plural kinds of titanium oxide, vanadium oxide, chromium oxide, zirconium oxide, niobium oxide, molybdenum oxide, hafnium oxide, tantalum oxide, tungsten oxide, and rhenium oxide.
28. An electronic apparatus comprising the light emitting device according to claim 18.
29. A light emitting device comprising:
a first electrode;
a first composite layer over the first electrode;
a second composite layer over the first composite layer; and
a second electrode over the second composite layer,
wherein the first composite layer comprises a first metal, oxygen, and carbon, and the second composite layer comprises a second metal, oxygen, and carbon,
wherein an average concentration of the first metal in the first composite layer is higher than an average concentration of the second metal in the second composite layer,
wherein at least one of the first composite layer and the second composite layer comprises an alternating stack of laminations of a first and a second region, the first region containing a larger amount of the first or second metal and the second region containing a larger amount of the carbon, and
wherein each concentration of the first metal in the first composite layer and the second metal in the second composite layer changes periodically in the stacked direction.
30. The light emitting device according to claim 29, wherein a concentration of the first metal in the first region is equal to or higher than a concentration of the first metal in the second region in the first composite layer.
31. The light emitting device according to claim 29, wherein a highest concentration of the first metal in the first region is the same or at most eight times as a lowest concentration of the first metal in the second region in the first composite layer.
32. The light emitting device according to claim 29, wherein a concentration of the second metal in the first region is equal to or higher than a concentration of the second metal in the second region in the second composite layer.
33. The light emitting device according to claim 29, wherein a highest concentration of the second metal in the first region is the same or at most eight times as a lowest concentration of the second metal in the second region in the second composite layer.
34. The light emitting device according to claim 29, wherein the first metal and the second metal are derived from a first metal oxide and a second metal oxide, respectively.
35. The light emitting device according to claim 34, wherein each of the first metal oxide and the second metal oxide is one or plural kinds of titanium oxide, vanadium oxide, chromium oxide, zirconium oxide, niobium oxide, molybdenum oxide, hafnium oxide, tantalum oxide, tungsten oxide, and rhenium oxide.
36. The light emitting device according to claim 29, wherein one cycle of a periodic change is 12 nm or less.
37. An electronic apparatus comprising the light emitting device according to claim 29.
38. The light emitting device according to claim 29, further comprising:
a third composite layer over the second composite layer, and between the second composite layer and the second electrode,
wherein the third composite layer comprises a third metal, oxygen, and carbon, and
wherein a concentration of the third metal changes periodically in the stacked direction.
39. The light emitting device according to claim 38, wherein the average concentration of the second metal in the second composite layer is higher than an average concentration of the third metal in the third composite layer.
40. The light emitting device according to claim 38, wherein a concentration of the first metal in the first region is equal to or higher than a concentration of the first metal in the second region in the first composite layer.
41. The light emitting device according to claim 38, wherein a highest concentration of the first metal in the first region is the same or at most eight times as a lowest concentration of the first metal in the second region in the first composite layer.
42. The light emitting device according to claim 38, wherein a concentration of the second metal in the first region is equal to or higher than a concentration of the second metal in the second region in the second composite layer.
43. The light emitting device according to claim 38, wherein a highest concentration of the second metal in the first region is the same or at most eight times as a lowest concentration of the second metal in the second region in the second composite layer.
44. The light emitting device according to claim 38, wherein a concentration of the third metal in the first region is equal to or higher than a concentration of the third metal in the second region in the third composite layer.
45. The light emitting device according to claim 38, wherein a highest concentration of the third metal in the first region is the same or at most eight times as a lowest concentration of the third metal in the second region in the third composite layer.
46. The light emitting device according to claim 38, wherein the first metal, the second metal, and the third metal are derived from a first metal oxide, a second metal oxide, and a third metal oxide, respectively.
47. The light emitting device according to claim 46, wherein each of the first metal oxide, the second metal oxide, and the third metal oxide is one or plural kinds of titanium oxide, vanadium oxide, chromium oxide, zirconium oxide, niobium oxide, molybdenum oxide, hafnium oxide, tantalum oxide, tungsten oxide, and rhenium oxide.
48. The light emitting device according to claim 38, wherein one cycle of a periodic change is 12 nm or less.
49. An electronic apparatus comprising the light emitting device according to claim 38.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

What is claimed is:

1. A probe card assembly for electrically communicating test data between a semiconductor test apparatus and a semiconductor device under test, said probe card assembly comprising:
a substrate configured to electrically contact said semiconductor tester apparatus,
a plurality of probes configured to electrically contact said semiconductor device under test, said plurality of probes located to a first side of said substrate, and
a daughter card secured to a second side of said substrate in spaced relationship to said substrate, said daughter card being substantially coplanar to said substrate.
2. The probe card assembly of claim 1 further comprising an electric circuit at least a portion of which is disposed on said daughter card.
3. The probe card assembly of claim 2, wherein said electric circuit includes active circuit elements.
4. The probe card assembly of claim 2, wherein said electric circuit is configured to enhance test capabilities of said semiconductor test apparatus.
5. The probe card assembly of claim 2, wherein said electric circuit is configured to customize at least a portion of said test data to test needs of said semiconductor device under test.
6. The probe card assembly of claim 5, wherein said test data comprises test signals generated by said semiconductor test apparatus and said electric circuit customizes at least a portion of said test signals.
7. The probe card assembly of claim 5, wherein said test data comprises response signals generated by said semiconductor device under test and said electric circuit customizes at least a portion of said response signals.
8. The probe card assembly of claim 1 further comprising a plurality of said daughter cards.
9. The probe card assembly of claim 8, wherein said plurality of daughter cards are disposed in stacked relationship to each other.
10. The probe card assembly of claim 8 further comprising an electric circuit at least a portion of which is disposed on each of said plurality of daughter cards.
11. The probe card assembly of claim 10, wherein said electric circuit includes active circuit elements.
12. The probe card assembly of claim 10, wherein said electric circuit is configured to enhance test capabilities of said semiconductor test apparatus.
13. The probe card assembly of claim 10, wherein said electric circuit is configured to customize at least a portion of said test data to test needs of said semiconductor device under test.
14. The probe card assembly of claim 13, wherein said test data comprises test signals generated by said semiconductor test apparatus and said electric circuit customizes at least a portion of said test signals.
15. The probe card assembly of claim 13, wherein said test data comprises response signals generated by said semiconductor device under test and said electric circuit customizes at least a portion of said response signals.
16. The probe card assembly of claim 8, wherein said plurality of daughter cards includes at least three daughter cards.
17. The probe card assembly of claim 16 further comprising an electric circuit at least a portion of which is disposed on each of said at least three daughter cards.
18. The probe card assembly of claim 16, wherein said at least three daughter cards are disposed in stacked relationship to each other.
19. A method of making a probe card assembly, said method comprising:
providing a substrate including a plurality of tester contacts,
securing a plurality of probes to a first side of said substrate, said probes configured to electrically contact a semiconductor device under test, and
securing a daughter card to a second side of said substrate in spaced relationship to said substrate, said daughter card being substantially coplanar to said substrate.
20. The method of claim 19 further comprising:
providing an electric circuit, and
disposing at least a portion of said electric circuit on said daughter card.
21. The method of claim 20, wherein said electric circuit includes active circuit elements.
22. The method of claim 20, wherein said electric circuit is configured to enhance test capabilities of said semiconductor test apparatus.
23. The method of claim 20, wherein said electric circuit is configured to customize test data to test needs of said semiconductor device under test.
24. The method of claim 23, wherein said test data comprises test signals to be input into said semiconductor device under test and said electric circuit customizes at least a portion of said test signals.
25. The method of claim 23, wherein said test data comprises response signals generated by said semiconductor device under test and said electric circuit customizes at least a portion of said response signals.
26. The method of claim 19 further comprising securing a plurality of said daughter cards to said substrate.
27. The method of claim 26 further comprising securing said plurality of daughter cards to said substrate in stacked relationship to each other.
28. The method of claim 26 further comprising:
providing an electric circuit, and
disposing at least a portion of said electric circuit on each of said plurality of daughter cards.
29. The method of claim 28, wherein said electric circuit includes active circuit elements.
30. The method of claim 28, wherein said electric circuit is configured to enhance test capabilities of said semiconductor test apparatus.
31. The method of claim 28, wherein said electric circuit is configured to customize test data to test needs of said semiconductor device under test.
32. The method of claim 31, wherein said test data comprises test signals to be input into said semiconductor device under test and said electric circuit customizes at least a portion of said test signals.
33. The method of claim 31, wherein said test data comprises response signals generated by said semiconductor device under test and said electric circuit customizes at least a portion of said response signals.
34. The method of claim 26, wherein said plurality of daughter cards includes at least three daughter cards.
35. The method of claim 34 further comprising:
providing an electric circuit, and
disposing at least a portion of said electric circuit on each of said at least three daughter cards.
36. The method of claim 34 further comprising securing each of said at least three daughter cards to said substrate in stacked relationship to each other.
37. A probe card assembly made using the process of claim 19.
38. A probe card assembly made using the process of claim 20.
39. A probe card assembly made using the process of claim 22.
40. A probe card assembly made using the process of claim 26.
41. A probe card assembly made using the process of claim 30.
42. A probe card assembly comprising:
printed circuit means for electrically communicating with a semiconductor tester apparatus,
contact means for electrically communicating with a semiconductor device under test, said contact means being secured to a first surface of said printed circuit means, and
daughter card means for physically supporting at least a portion of an electric circuit, said daughter card means secured to a second surface of said printed circuit means and being substantially coplanar to said printed circuit means.
43. The probe card assembly of claim 42, wherein said daughter card means comprises a plurality of daughter cards in stacked relationship to each other, each of said plurality of daughter cards being substantially coplanar to said printed circuit means.
44. The probe card assembly of claim 43, wherein said plurality of daughter cards includes at least three daughter cards.
45. The probe card assembly of claim 42, wherein said electric circuit comprises processing means for processing test data for testing said semiconductor device under test.
46. The probe card assembly of claim 45, wherein said processing means enhances test capabilities of said semiconductor test apparatus.
47. The probe card assembly of claim 45, wherein said processing means customizes said test data to meet test needs of said semiconductor device under test.
48. The probe card assembly of claim 47, wherein said test data comprises test signals to be input into said semiconductor device under test and said processing means customizes at least a portion of said test signals.
49. The probe card assembly of claim 47, wherein said test data comprises response signals generated by said semiconductor device under test and said processing means customizes at least a portion of said response signals.
50. A probe card assembly for electrically communicating test data between a semiconductor test apparatus and a semiconductor device under test, said probe card assembly comprising:
a printed circuit board configured to electrically contact said semiconductor tester apparatus,
a plurality of probes configured to electrically contact said semiconductor device,
a daughter card secured to said printed circuit board in spaced relationship to said printed circuit board, said daughter card being substantially coplanar to said printed circuit board, and
an electric circuit configured to enhance test capabilities of said semiconductor test apparatus, at least a portion of said electric circuit being disposed on said daughter card.
51. The probe card assembly of claim 50 further comprising a plurality of said daughter cards.
52. The probe card assembly of claim 51, wherein said daughter cards are disposed in stacked relationship to each other.
53. The probe card assembly of claim 51, wherein said plurality of daughter cards includes at least two daughter cards.
54. The probe card assembly of claim 51, wherein said plurality of daughter cards includes at least three daughter cards.
55. The probe card assembly of claim 50, wherein said electric circuit enhances test capabilities of said semiconductor test apparatus by processing at least a portion of said test data.
56. The probe card assembly of claim 55, wherein said test data comprises test signals generated by said semiconductor tester apparatus and said electric circuit processes at least a portion of said test signals.
57. The probe card assembly of claim 55, wherein said test data comprises response signals generated by said semiconductor device and said electric circuit processes at least a portion of said response signals.