All The Claims

1. A track assembly for a machine comprising:
a first chain assembly:
a track pin;
a second chain assembly wherein the track pin couples the second chain assembly with the first chain assembly, the first and second chain assemblies each including an inner track link and an outer track link, wherein the inner track link includes a shoulder;
a rotatable bushing positioned about the track pin;
a sleeve bearing disposed within a first bore of the inner track link and positioned about the track pin, wherein the sleeve bearing is disposed to transfer axial loads to the shoulder;
a first seal member disposed between the inner track link and the rotatable bushing;
a second seal member disposed between the inner and outer track links;
a first thrust ring positioned about the track pin and engaged with the rotatable bushing;
a second thrust ring disposed about the track pin and engaged with the sleeve bearing; and
a first contact member engaged with the first seal member and a second contact member fastened to either the inner track link or the outer track link and engaged with the second seal member, the first and second contact members configured to inhibit wear of the first and second seal members.
2. The track assembly of claim 1, wherein the first and second contact members are formed of corrosion and abrasion resistant material.
3. The track assembly of claim 1, wherein the first contact member is fastened to an end face of the rotatable bushing.
4. The track assembly of claim 1, wherein the second contact member is fastened to the inner track link.
5. The track assembly of claim 1, wherein the second contact member is fastened to the outer track link.
6. The track assembly of claim 1, wherein the second seal member is disposed within the first bore of the inner track link.
7. The track assembly of claim 1, wherein the second seal member is disposed within a bore of the outer track link.
8. The track assembly of claim 1, wherein the first seal member is disposed within a second bore of the inner track link, the second bore axially aligned with the first bore.
9. The track assembly of claim 1, wherein the first thrust ring is configured to push against the end face of the rotatable bushing and the second thrust ring is configured to push against an end face of the sleeve bearing.
10. A method of protecting components of a machine track assembly during operation, the machine track assembly including an outer track link, an inner track link, a track pin, a rotatable bushing positioned about the track pin, a first seal member disposed between the inner track link and the rotatable bushing, and a second seal member disposed between the inner and outer track links, wherein the inner track link includes a shoulder, the method comprising:
disposing a sleeve bearing about the track pin, wherein the sleeve bearing is disposed to transfer axial loads to the shoulder; and
protecting the first and second seal members at least in part by:
assembling a first thrust ring about the track pin and engaging the first thrust ring with the rotatable bushing;
assembling a second thrust ring about the track pin and engaging the second thrust ring with the sleeve bearing;
engaging a first contact member with the first seal member;
fastening a second contact member to the inner track link or the outer track link; and
engaging the second contact member with the second seal member.
11. The method of claim 10, wherein disposing the sleeve bearing about the track pin further includes inserting the sleeve bearing within a first bore of the inner track link.
12. The method of claim 10, wherein engaging a first contact member with the first seal member includes fastening the first contact member to an end face of the rotatable bushing.
13. The method of claim 10, wherein engaging a second contact member with the second seal member includes fastening the second contact member to the inner track link.
14. The method of claim 10, wherein engaging a second contact member with the second seal member includes fastening the second contact member to the outer track link.
15. A track-type machine comprising:
a frame; and
a track mounted on the frame, the track including a first chain assembly;
a plurality of track pins;
a second chain assembly, wherein the plurality of track pins couple the first chain assembly with the second chain assembly, the first and second chain assemblies including a plurality of inner track links and a plurality of outer track links, wherein the inner track links each include a shoulder;
a rotatable bushing positioned about each track pin;
a sleeve bearing disposed within a first bore of each inner track link and positioned about each track pin, wherein the sleeve bearing is disposed to transfer axial loads to the shoulder;
a first seal member disposed between each inner track link and the rotatable bushing;
a second seal member disposed between each inner and outer track link;
a first thrust ring positioned about each track pin and engaged with the rotatable bushing;
a second thrust ring disposed about each track pin and engaged with the sleeve bearing; and
a first contact member engaged with the first seal member and a second contact member engaged with the second seal member, the first and second contact members configured to inhibit wear of the first and second seal members;
wherein the first seal member is coupled to a bore of the inner track link and the second seal member is coupled to a bore of the inner track link.
16. The track-type machine of claim 15, wherein the first contact member is fastened to an end face of the rotatable bushing.
17. The track-type machine of claim 15, wherein the second contact member is fastened to each outer track link.
18. The track-type machine of claim 15, wherein the first thrust ring is configured to push against the end face of the rotatable bushing and the second thrust ring is configured to push against an end face of the sleeve bearing.
19. The track assembly of claim 15, wherein the outer track link is positioned about a collar fastened to the track pin, and the second contact member is fastened to the collar.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. In a signal processing device, a method for serially calculating a Fast Hadamard Transform of size N of a first order of a sampled signal from a first channel, the method comprising:
serially storing a plurality of sampled Hadamard Transform signals of a size M of a second order, the size M of the second order being less than the size N of the first order;
computing a sum of two computations from a first sampled Hadamard Transform signal of size M and a second sampled Hadamard Transform signal from the plurality of sampled Hadamard Transform signals of the second order;
storing the sum;
computing a difference of two computations from the first sampled Hadamard Transform signal of size M and the second sampled Hadamard Transform signal from the plurality of sampled Hadamard Transform signals of the second order;
storing the difference; and
combing the sum and the difference to form a sampled Hadamard Transform signal of size N of the sampled signal from the first channel,
wherein the sampled signal from the first channel is representative of a wireless communication transmitted to the signal processing device.
2. The method of claim 1, wherein the sampled signal contains 2N samples where N is an integer.
3. The method of claim 1, wherein the sum of computations from the first sampled Hadamard Transform signal of the second order and of the second sampled Hadamard Transform signal of the second order is computed during the same clock cycle and the difference of computations from the first sampled Hadamard Transform signal of the second order and the second sampled Hadamard Transform signal of the second order is computed during a second clock cycle.
4. The method of claim 1, wherein the sum of computations from the first sampled Hadamard Transform signal of the second order and of the second sampled Hadamard Transform signal of the second order is computed during the same clock cycle and the difference of computations from the first sampled Hadamard Transform signal of the second order and the second sampled Hadamard Transform signal of the second order is computed during the same clock cycle.
5. The method of claim 1, wherein the size N of the first order is of the form 2K and the size M of the second order is of the form 2J, wherein K is greater than J.
6. The method of claim 1, wherein computing the difference of computations from the first sampled Hadamard Transform signal of the second order and the second sampled Hadamard Transform signal of the second order comprises the step of
computing a sum of the first sampled Hadamard Transform signal of the second order and a two’s complement of the second sampled Hadamard Transform signal of the second order.
7. The method of claim 1, wherein sampled Hadamard Transform signals of size order one (N=1) are samples from the sampled signal.
8. The method of claim 1, wherein the sampled Hadamard Transform signals of the second order are serially calculated using a method comprising the steps of:
serially storing a plurality of sampled Hadamard Transform signals of a third order, the third order being less than the second order;
computing a sum of a first sampled Hadamard Transform signal and a second sampled Hadamard Transform signal from the plurality of sampled Hadamard Transform signals of the third order;
storing the sum;
computing a difference of the first sampled Hadamard Transform signal and the second sampled Hadamard Transform signal from the plurality of sampled Hadamard Transform signals of the third order; and
storing the difference.
9. The method of claim 8, wherein computing a difference of the first sampled Hadamard Transform signal of the third order and the second sampled Hadamard Transform signal the third order comprises the step of computing a sum of the first sampled Hadamard Transform signal of the third order and a two’s complement of the second sampled Hadamard Transform signal of the third order.
10. The method of claim 8, wherein sampled Hadamard Transform signals of order one (1) are samples from the sampled signal.
11. The method of claim 8, wherein the sampled signal contains 2N samples where N is an integer.
12. The method of claim 8, wherein the sum of the first sampled Hadamard Transform signal of the third order and the second sampled Hadamard Transform signal of the third order is computed during a first clock cycle and the difference of the first sampled Hadamard Transform signal of the third order and the second sampled Hadamard Transform signal of the third order is computed during a second clock cycle.
13. The method of claim 8, wherein the sum of the first sampled Hadamard Transform signal of the third order and the second sampled Hadamard Transform signal of the third order is computed during the same clock cycle and the difference of the first sampled Hadamard Transform signal of the third order and the second sampled Hadamard Transform signal of the third order is computed during the same clock cycle.
14. The method of claim 8, wherein the first order is of the form 2K and the second order is of the form 2J and the third order is of the form 2I, wherein K is greater than J which is greater than I.
15. The method of claim 1, wherein the steps of computing and storing sums and differences are applied repeatedly to produce sampled Fast Hadamard Transform signals of successively greater size order.
16. The method of claim 15, wherein the steps of computing and storing sums and differences are first applied to samples of the sampled signal.
17. The method of claim 1, wherein each of the sampled Hadamard Transform signals is bit-reverse-ordered to produce a transformation of the sampled Hadamard Transform signal.
18. The method of claim 17, wherein all terms of each of the transformations of the sampled Hadamard Transform signals have a one to one correspondence to terms of the sampled Hadamard Transform signals.
19. The method of claim 17, wherein all rows of each of the transformations of the sampled Hadamard Transform signals have a one-to-one correspondence to rows of sampled Hadamard Transform signals.
20. The method of claim 1, wherein the size N is of the form 2K and the size M is of the form 2J, wherein K=1 and J=0.
21. The method of claim 1, wherein the size N is of the form 2K and the size M is of the form 2J, wherein K=2 and J=1.
22. An apparatus for serially calculating a Fast Hadamard Transform of a sampled signal from a first channel, comprising:
a first shift register for serially receiving samples of the signal;
a first two’s complement generator for producing a two’s complement of a first sample of the signal;
a first multiplexer for selecting between a first sample of the signal and the two’s complement of the signal to produce a multiplexer output; and
a first adder for generating a sum of a second sample of the signal and the multiplexer output.
23. The apparatus of claim 22, wherein the sampled signal contains 2N samples where N is an integer.
24. The apparatus of claim 22, wherein the first adder generates a sum of a first sample of the signal and the second sample of a signal during a first clock cycle and wherein the first adder generates a difference of a first sample of the signal and the second sample of the signal during a second clock cycle.
25. The apparatus of claim 22, wherein the first adder generates a sum of a first sample of the signal and the second sample of a signal during the same clock cycle and wherein the first adder generates a difference of a first sample of the signal and the second sample of the signal during the same clock cycle.
26. The apparatus of claim 25, wherein the sum and the difference are passed to a second shift register.
27. The apparatus of claim 22, wherein the first shift register is a random access memory.
28. The apparatus of claim 22, wherein the first shift register is a FIFO.
29. The apparatus of claim 22, wherein the first adder is shared with a second channel.
30. The apparatus of claim 22 further comprising:
a second shift register for serially receiving the sum from the first adder;
a second two’s complement generator for producing a two’s complement of a signal stored in the second shift register;
a second multiplexer for selecting between a signal stored in the second shift register and the two’s complement of said signal to produce a multiplexer output; and
a second adder for generating a sum of another signal stored in the second shift register and the multiplexer output.
31. In a signal processing device, a method for serially calculating a Fast Hadamard Transform of a sampled signal from a first channel, the method comprising:
serially storing samples of the signal;
computing a first sum of a first sample of the signal and a last sample of the signal;
storing the first sum;
computing a second sum of a first sample of the signal and a two’s complement of the last sample of the signal;
storing the second sum; and
combining the first sum and the second sum to form a sampled Hadamard Transform signal of size N of the sampled signal from the first channel,
wherein the sampled signal from the first channel is representative of a wireless communication transmitted to the signal processing device.
32. An apparatus for serially calculating a Fast Hadamard Transform of order size 2N of a sampled signal from a first channel, comprising:
a first shift register for serially receiving computations from Hadamard Transforms of order size 2N-1;
a first two’s complement generator for producing a two’s complement of a first computation from a first Hadamard Transform of order size 2N-1 that is stored in the first shift register; and
a first adder for generating a sum of a second computation from a Hadamard Transform of order size 2N-1 and the first Hadamard Transform of the order size 2N-1, the first adder also generating a sum of the second computation of the Hadamard Transform of order size 2N-1 and a two’s complements of the first computation of a Hadamard Transform of order size 2N-1.
33. The apparatus of claim 32, further comprising a first multiplexer for selecting between the first Hadamard Transform of order size 2N-1 and the two’s complements of the first Hadamard Transform of the order size 2N.
34. The apparatus of claim 32, further comprising a second shift register for serially receiving Hadamard Transforms of order size 2N.
35. The apparatus of claim 32, wherein the sampled signal contains 2N samples where N is an integer.
36. The apparatus of claim 32, wherein the sum of the second Hadamard Transform of order size 2N-1 and the first Hadamard Transform of order size 2N-1 is generated during a first clock cycle and wherein the sum of the second Hadamard Transform of order size 2N-1 and the two’s complements of the first Hadamard Transform of order size 2N-1 is generated during a second clock cycle.
37. The apparatus of claim 32, wherein the sum of the second Hadamard Transform of order size 2N-1 and the first Hadamard Transform of order size 2N-1 is generated during the same clock cycle and wherein the sum of the second Hadamard Transform of order size 2N-1 and the two’s complements of the first Hadamard Transform of order size 2N-1 is generated during the same clock cycle.
38. The apparatus of claim 32, wherein the first shift register is a random access memory.
39. The apparatus of claim 32, wherein the first shift register is a FIFO register.
40. The apparatus of claim 32, wherein the first adder is shared with another channel.
41. In a signal processing device, a method for serially calculating a Fast Hadamard Transform of a sampled signal from a first channel, the method comprising:
serially storing samples of the signal;
computing a first sum of a second sample of the signal and a first sample of the signal;
storing the first sum;
computing a second sum of the second sample of the signal and a two’s complement of the first sample of the signal;
storing the second sum; and
combining the first sum and the second sum to form a sampled Hadamard Transform signal of size N of the sampled signal from the first channel,
wherein the sampled signal from the first channel is representative of a wireless communication transmitted to the signal processing device.
42. The method of claim 41, further comprising storing the first and second sums in a memory.
43. The method of claim 41, wherein the sampled signal contains 2N samples where N is an integer.
44. The method of claim 41, wherein the first sum is computed during a first clock cycle and the second sum is computed during a second clock cycle.
45. The method of claim 41, wherein the first sum is computed during the same clock cycle and the second sum is computed during the same clock cycle.

1. An article of manufacture comprising:
shared memory;
program memory to store a plurality of instructions;
a counter to be clocked by a signal derived from a stratum traceable clock (STC) reference;
a processor to execute the plurality of instructions stored in the program memory and thereby (1) process voice payload into voice packets for one or more channels, the voice payload having been obtained from a plurality of network packets sent by a sender machine through a network, and (2) buffer the voice packets before writing them to the shared memory, wherein one or more of the buffered voice packets are written by the processor in response to and only if an interrupt is received from the counter;
a digital signal processor (DSP) system to read the plurality of voice packets from the shared memory before processing them; and
an interface to a bus, to transmit voice data of one or more channels, from the voice packets processed by the DSP system, over the bus and according to a bus clock, wherein the bus clock is derived from the STC reference signal.
2. The article of manufacture of claim 1 wherein the interface is to a time division multiplexed (TDM) bus, and the bus clock is a TDM bus clock.
3. The article of manufacture of claim 2 wherein the shared memory implements a first in first out (FIFO) structure, for storing the voice packets, that can be accessed independently by both the processor and the DSP system.
4. The article of manufacture of claim 3 wherein the shared memory is made of static RAM, and the program memory is made of dynamic RAM.
5. The article of manufacture of claim 1 wherein the counter and the processor are on the same chip.
6. The article of manufacture of claim 1 wherein the program memory includes further instructions which, when executed by the processor, cause the network packets to be processed at an application layer.
7. The article of manufacture of claim 6 wherein the program memory includes further instructions which, when executed by the processor, cause the network packets to be processed at an asynchronous transfer mode (ATM) adaptation layer.
8. The article of manufacture of claim 7 wherein the program memory includes further instructions which, when executed by the processor, cause the network packets to be disassembled to recover octets for individual voice tributaries.
9. The article of manufacture of claim 1 wherein some of the voice packets to be stored in the shared memory contain compressed speech data, and wherein the DSP system is to decompress such speech data before transmission over the bus.
10. The article of manufacture of claim 1 wherein the DSP system is to process the voice packets by decoding the packets, including one or more of format changing, decompression, and echo cancellation, before transmission over the bus.
11. The article of manufacture of claim 1 wherein the program memory includes further instructions which, when executed by the processor, cause the counter to be programmed to periodically interrupt the processor at a base rate, such that voice data for a given channel is transferred into the bus at essentially the same rate as voice data for the same channel is collected off a bus in the sender machine.
12. The article of manufacture of claim 1 further comprising:
a bridge coupled between the processor and the shared memory, to forward the voice packets from the processor to the shared memory and forward the interrupt from the counter to the processor.
13. The article of manufacture of claim 12 further comprising:
an embedded controller coupled to the bridge and containing a timer module, the counter being part of the timer module.
14. The article of manufacture of claim 13 wherein the signal that clocks the counter is provided by the DSP system, based upon the bus clock.
15. The article of manufacture of claim 1 further comprising:
a bridge coupled to forward the voice packets from the processor to the shared memory, and wherein the signal that clocks the counter is derived from the bus clock.
16. An article of manufacture comprising:
a machine-readable medium having instructions stored therein which when executed by a set of processors cause
(a) a counter to be programmed to repeatedly generate an interrupt to a first one of the processors at a base rate, the base rate being obtained by clocking the counter with a stratum traceable clock, STC-derived signal,
(b) voice payload, received from a sender machine through a packet-based network, to be processed by the first processor into a plurality of voice packets, and
(c) one or more of the voice packets to be repeatedly written from a buffer to a memory shared by the first processor and a second one of the processors, at a rate derived from the base rate.
17. The article of manufacture of claim 16 wherein the machine-readable medium includes further instructions which, when executed by the set of processors, cause the second processor to process one or more of the voice packets obtained from the shared memory before transmitting them over a bus according to a STC-derived clock.
18. The article of manufacture of claim 17 wherein the base rate is such that voice data in the voice packets, for a given channel, is transferred into the bus at essentially the same rate as voice data for the same channel is collected off a bus in the sender machine.
19. The article of manufacture of claim 18 wherein the machine-readable medium includes volatile and non-volatile semiconductor memory to store the instructions.
20. The article of manufacture of claim 16 wherein the instructions further provide a real time operating system for the first processor, the operating system having a first variable that is updated by an interrupt service routine, in response to each interrupt.
21. The article of manufacture of claim 20 wherein the instructions update a respective credit variable for each voice channel in response to the first variable being changed, the updating of the respective credit variable being a function of a packet size for each channel.
22. The article of manufacture of claim 21 wherein the instructions forward packets from a buffer to the shared memory, based upon the buffer contents satisfying predetermined thresholds between completely full and completely empty.
23. A method comprising:
programming a counter to repeatedly generate an interrupt to a first processor at a base rate, the base rate being obtained by clocking the counter with a stratum traceable clock, STC-derived signal;
processing voice payload, received from a sender machine through a packet-based network, into a plurality of voice packets; and
repeatedly writing one or more of the voice packets from a buffer to a memory shared by the first processor and a second processor, at a rate derived from the base rate.
24. The method of claim 23 further comprising:
processing one or more of the voice packets obtained from the shared memory, before transmitting them over a bus according to a STC-derived clock.
25. The method of claim 24 wherein the base rate is such that voice data in the voice packets, for a given channel, is transferred into the bus at essentially the same rate as voice data for the same channel is collected off a bus in the sender machine.
26. The method of claim 23 further comprising:
updating a first variable of a real time operating system in response to each interrupt.
27. The method of claim 26 further comprising:
updating a respective credit variable for each voice channel in response to the first variable being changed, the updating of the respective credit variable being a function of a packet size for each channel.
28. The method of claim 27 further comprising:
forwarding packets from the buffer to the shared memory, based upon the buffer contents satisfying predetermined thresholds between completely full and completely empty.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A computer implemented method for parallel data redundancy removal, the computer implemented method comprising:
computing a plurality of values for a record in a plurality of records stored in a storage device;
distributing the plurality of values for the record to corresponding queues in a plurality of queues, wherein each of the plurality of queues is associated with a corresponding section of a Bloom filter;
determining whether each value distributed to the corresponding queues for the record is indicated by a corresponding value in the corresponding section of the Bloom filter; and
identifying the record as a redundant record in response to a determination that each value distributed to the corresponding queues for the record is indicated by a corresponding value in the corresponding section of the Bloom filter.
2. The computer implemented method of claim 1, wherein the computing the plurality of values is performed in parallel by threads for multiple records in the plurality of records, and the distributing the plurality of values is performed in parallel by the threads for the multiple records to corresponding queues in the plurality of queues.
3. The computer implemented method of claim 1, further comprising:
determining whether the redundant record duplicates another record in a repository associated with the Bloom filter; and
removing the redundant record from the plurality of records in response to a determination that the redundant record duplicates another record in the repository.
4. The computer implemented method of claim 1, further comprising:
identifying the record as a unique record in response to a determination that each value distributed to the corresponding queues for the record is not indicated by the corresponding value in the corresponding section of the Bloom filter; and
storing the unique record in a repository associated with the Bloom filter.
5. The computer implemented method of claim 4, wherein storing the unique record in the repository comprises setting an indicator in the corresponding value in the corresponding section of the Bloom filter for each value distributed to the corresponding queues for the unique record.
6. The computer implemented method of claim 1, further comprising:
identifying any records in a preliminary plurality of records that are redundant relative to other records in the preliminary plurality of records;
removing any identified redundant records of the preliminary plurality of records from the preliminary plurality of records to create the plurality of records.
7. The computer implemented method of claim 6, wherein identifying any records in the preliminary plurality of records that are redundant relative to other records in the preliminary plurality of records comprises:
assigning a unique identifier to a record in the preliminary plurality of records;
computing a hash value for the record in the preliminary plurality of records based on the corresponding unique identifier;
storing the hash value to a corresponding hash table in a plurality of hash tables; and
merging the plurality of hash tables to identify at least one record of multiple records that correspond to values that are identical for the at least one record in different hash tables as redundant relative to other records in the preliminary plurality of records.
8. The computer implemented method of claim 6, further comprising:
computing a value for a record in an initial plurality of records based on a plurality of fields associated with each record in the initial plurality of records;
distributing the record in the initial plurality of records to a corresponding buffer in a plurality of buffers based on the value for the record in the initial plurality of records, wherein each of the plurality of buffers is associated with a corresponding Bloom filter;
assigning records of a buffer in the plurality of buffers as the preliminary plurality of records;
pre-fetching a second Bloom filter corresponding to the buffer to cache; and
assigning the second Bloom filter corresponding to the buffer as the Bloom filter.
9. A computer usable program product comprising a computer usable storage medium including computer usable code for parallel data redundancy removal, the computer usable code comprising:
computer usable code for computing a plurality of values for a record in a plurality of records stored in a storage device;
computer usable code for distributing the plurality of values for the record to corresponding queues in a plurality of queues, wherein each of the plurality of queues is associated with a corresponding section of a Bloom filter;
computer usable code for determining whether each value distributed to the corresponding queues for the record is indicated by a corresponding value in the corresponding section of the Bloom filter; and
computer usable code for identifying the record as a redundant record in response to a determination that each value distributed to the corresponding queues for the record is indicated by the corresponding value in the corresponding section of the Bloom filter.
10. The computer usable program product of claim 9, wherein the computing the plurality of values is performed in parallel by threads for multiple records in the plurality of records by threads, and the distributing the plurality of values is performed in parallel by the threads for the multiple records to corresponding queues in the plurality of queues by the threads.
11. The computer usable program product of claim 9, further comprising:
computer usable code for determining whether the redundant record duplicates one of the records in a repository associated with the Bloom filter; and
computer usable code for removing the redundant record from the plurality of records in response to a determination that the redundant record duplicates another record in the repository.
12. The computer usable program product of claim 9, further comprising:
computer usable code for identifying the record as a unique record in response to a determination that each value distributed to the corresponding queues for the record is not indicated by the corresponding value in the corresponding section of the Bloom filter; and
computer usable code for storing the unique record in a repository associated with the Bloom filter.
13. The computer usable program product of claim 12, wherein computer usable code for storing the unique record in the repository comprises computer usable code for setting an indicator in the corresponding value in the corresponding section of the Bloom filter for each value distributed to the corresponding queues for the unique record.
14. The computer usable program product of claim 9, further comprising:
computer usable code for identifying any records in a preliminary plurality of records that are redundant relative to other records in the preliminary plurality of records;
computer usable code for removing any identified redundant records in the preliminary plurality of records from the preliminary plurality of records to create the plurality of records.
15. The computer usable program product of claim 14, wherein computer usable code for identifying any records in the preliminary plurality of records that are redundant relative to other records of the preliminary plurality of records comprises:
computer usable code for assigning a unique identifier to a record in the preliminary plurality of records;
computer usable code for computing a hash value for the record in the preliminary plurality of records based on the corresponding unique identifier;
computer usable code for storing the hash value to a corresponding hash table in a plurality of hash tables; and
computer usable code for merging the plurality of hash tables to identify at least one record of multiple records that correspond to values that are identical for the at least one record in different hash tables as redundant relative to other records in the preliminary plurality of records.
16. The computer usable program product of claim 14, further comprising:
computer usable code for computing a value for a record in an initial plurality of records based on a plurality of fields associated with the record in the initial plurality of records;
computer usable code for distributing the record in the initial plurality of records to a corresponding buffer in a plurality of buffers based on the value for the record in the initial plurality of records, wherein each of the plurality of buffers is associated with a corresponding Bloom filter;
computer usable code for assigning records of a buffer in the plurality of buffers as the preliminary plurality of records;
computer usable code for pre-fetching a second Bloom filter corresponding to the buffer to cache; and
computer usable code for assigning the second Bloom filter corresponding to the buffer as the Bloom filter.
17. The computer usable program product of claim 9, wherein the computer usable code is stored in a computer readable storage medium in a data processing system, and wherein the computer usable code is transferred over a network from a remote data processing system.
18. The computer usable program product of claim 9, wherein the computer usable code is stored in a computer readable storage medium in a server data processing system, and wherein the computer usable code is downloaded over a network to a remote data processing system for use in a computer readable storage medium associated with the remote data processing system.
19. A data processing system for parallel data redundancy removal, the data processing system comprising:
a storage device including a storage medium, wherein the storage device stores computer usable program code; and
a processor, wherein the processor executes the computer usable program code, and wherein the computer usable program code comprises:
computer usable code for computing a plurality of values for a record in a plurality of records;
computer usable code for distributing the plurality of values for the record to corresponding queues in a plurality of queues, wherein each of the plurality of queues is associated with a corresponding section of a Bloom filter;
computer usable code for determining whether each value distributed to the corresponding queues for the record is indicated by a corresponding value in the corresponding section of the Bloom filter; and
computer usable code for identifying the record as a redundant record in response to a determination that each value distributed to the corresponding queues for the record is indicated by the corresponding value in the corresponding section of the Bloom filter.
20. The data processing system of claim 19, wherein the computing the plurality of values is performed in parallel by threads for multiple records in the plurality of records by threads, and the distributing the plurality of values is performed in parallel by the threads for the multiple records to corresponding queues in the plurality of queues by the threads.