1. A SRAM cell structure comprising:
a first N type switch having a control terminal connected to a word line and a first terminal connected to a bit line;
a second N type switch having a control terminal connected to the word line and a first terminal connected to an inverted bit line;
a first storage node having a first terminal connected to a second terminal of the first N type switch and a floating second terminal; and
a second storage node having a first terminal connected to a second terminal of the second N type switch and a floating second terminal.
2. The SRAM cell structure according to claim 1 wherein the first N type switch is a first NMOS transistor, which has a gate electrode connected to the word line, a drain electrode connected to the bit line and a source electrode connected to the first terminal of the first storage node.
3. The SRAM cell structure according to claim 1 wherein the second first N type switch is a second NMOS transistor, which has a gate electrode connected to the word line, a drain electrode connected to the inverted bit line and a source electrode connected to the first terminal of the second storage node.
4. The SRAM cell structure according to claim 1 wherein the first storage node is a NMOS capacitor including a third NMOS transistor, and the second storage node is a NMOS capacitor including a fourth NMOS transistor.
5. The SRAM cell structure according to claim 4 wherein the gate electrodes of the third NMOS transistor and the fourth NMOS transistor are connected to an external voltage.
6. The SRAM cell structure according to claim 4 wherein the drain electrode of the third NMOS transistor is connected to the second terminal of the first N type switch, and the drain electrode of the third NMOS transistor is floating.
7. The SRAM cell structure according to claim 4 wherein the drain electrode of the fourth NMOS transistor is connected to the second terminal of the second N type switch, and the drain electrode of the fourth NMOS transistor is floating.
8. The SRAM cell structure according to claim 1 wherein complementary data are stored in the first storage node and the second storage node.
9. A static random access memory comprising:
a main control circuit for receiving multiple address signals, a clock signal and a readwrite signal, wherein the address signals includes column address signals and row address signals;
a column decoder connected to the main control circuit, wherein the column address signals are transmitted to the column decoder for controlling a bit line;
a row decoder connected to the main control circuit, wherein the row address signals are transmitted to the row decoder for controlling a word line;
a memory cell array connected to the column decoder and the row decoder;
a sense amplifier and inputoutput control circuit connected to the memory cell array; and
a hidden refresh unit connected to the main control circuit, wherein when the static random access memory is in a normal operation without refresh mode, the hidden refresh unit performs only a normal writeread operation within one clock cycle, and when the static random access memory is in a normal operation with refresh mode, the hidden refresh unit performs a writeread operation followed by a refresh operation on the memory cell array within one clock cycle.
10. The static random access memory according to claim 9 wherein the memory cell array includes multiple memory cells, and each memory cell includes:
a first N type switch having a control terminal connected to a word line and a first terminal connected to a bit line;
a second N type switch having a control terminal connected to the word line and a first terminal connected to an inverted bit line;
a first storage node having a first terminal connected to a second terminal of the first N type switch; and
a second storage node having a first terminal connected to a second terminal of the second N type switch.
11. The static random access memory according to claim 10 wherein the first N type switch is a first NMOS transistor, which has a gate electrode connected to the word line, a drain electrode connected to the bit line and a source electrode connected to the first terminal of the first storage node.
12. The static random access memory according to claim 10 wherein the second first N type switch is a second NMOS transistor, which has a gate electrode connected to the word line, a drain electrode connected to the inverted bit line and a source electrode connected to the first terminal of the second storage node.
13. The static random access memory according to claim 10 wherein the first storage node has a floating second terminal, and the second storage node has a floating second terminal.
14. The static random access memory according to claim 10 wherein the first storage node is a NMOS capacitor including a third NMOS transistor, and the second storage node is a NMOS capacitor including a fourth NMOS transistor.
15. The static random access memory according to claim 14 wherein the gate electrodes of the third NMOS transistor and the fourth NMOS transistor are connected to an external voltage.
16. The static random access memory according to claim 14 wherein the drain electrode of the third NMOS transistor is connected to the second terminal of the first N type switch, and the drain electrode of the third NMOS transistor is floating.
17. The static random access memory according to claim 14 wherein the drain electrode of the fourth NMOS transistor is connected to the second terminal of the second N type switch, and the drain electrode of the fourth NMOS transistor is floating.
18. The static random access memory according to claim 10 wherein complementary data are stored in the first storage node and the second storage node.
19. The static random access memory according to claim 9 wherein the hidden refresh unit includes:
an oscillator for generating an oscillation clock signal having a lower frequency than the clock signal; and
a flag register connected to the oscillator for receiving the oscillation clock signal, wherein in response to a first voltage level of the oscillation clock, the flag register is set and generates a setting signal to the main control circuit, in response to the setting signal, the main control circuit automatically generates a refresh enabling signal and a corresponding refresh address to the row decoder so as to perform the refresh operation, and the refresh enabling signal is transmitted to the flag register to reset the flag register.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method of importing scanned image data into a production workflow, comprising:
receiving an configuration file having information describing a plurality of image processing plugins;
registering zero or more plugins for each a plurality of event triggers specified in the configuration file;
sequentially initiating the plurality of event triggers to invoke respective registered plugins; and
processing the scanned images using the invoked plugins.
2. The method of claim 1, further comprising loading to memory configuration parameters for a production scanning job.
3. The method of claim 2, further comprising receiving source image directory information that identifies a source directory from which images are to be imported for processing.
4. The method of claim 3, further comprising receiving destination directory information that identifies a destination directory to which processed images will be exported.
5. The method of claim 4, further comprising loading into memory metadata related to images to be processed.
6. The method of claim 1, further comprising invoking at least one Import plugin that generates a list of image objects that represent images to be processed.
7. The method of claim 6, further comprising invoking at least one Pre-Scan plugin that performs operations that do not require image data.
8. The method of claim 7, further comprising invoking at least on In-Scan plugin that processes an image to extract data specified in the In-Scan plugin definition.
9. The method of claim 8, further comprising invoking at least one Post-Scan plugin that evaluates data extracted by the In-Scan plugin and copies source image data into a destination directory.
10. The method of claim 1, wherein the plurality of event triggers comprises one or more of an Import trigger, a Pre-scan trigger, an In-scan trigger, and a Post-scan trigger.
11. The method of claim 1, wherein the configuration file associates plugins with event triggers and an order in which plugins associated with a common trigger are to be invoke relative to each other when the common trigger occurs.
12. A system that facilitates importing scanned image data into a production workflow, comprising:
a processor that receives a configuration file that describes a plurality of image processing plugins, and generates trigger event messages;
a memory that stores the configuration file; and
a plugin handler that receives a trigger event messages from the processor and invokes one or more plugins registered to the trigger event message.
13. The system of claim 12, wherein the trigger event message is at least one of an Import trigger event, a Pre-scan trigger event, an In-scan trigger event, and a Post-scan trigger event.
14. The system of claim 13, wherein the plugin handler invokes at least one Import plugin that generates a list of image objects that represent images to be processed.
15. The system of claim 14, wherein the plugin handler invokes at least one Pre-Scan plugin that performs operations that do not require image data.
16. The system of claim 15, wherein the plugin handler invokes at least on In-Scan plugin that processes an image to extract data specified in the In-Scan plugin definition.
17. The system of claim 16, wherein the In-Scan plugin definition specifies a type of data to be extracted comprising at least one of TIFF-formatted data, jpeg-formatted data, pdf-formatted data, ftp-formatted data, and ZIP-formatted data.
18. The system of claim 16, wherein the plugin handler invokes at least one Post-Scan plugin that evaluates data extracted by the In-Scan plugin and copies source image data into a destination directory.
19. The system of claim 12, wherein the plugin handler invokes plugins having a common event trigger in an order specified in the configuration file when the common trigger occurs.
20. A scanning platform, comprising:
a scanner that generates electronic images of documents for information retrieval;
a memory that stores a received configuration file, which defines an action for at least one plugin that allows the plugin to execute custom code that is at least one of a script or compiled code; and
a plugin handler that recognizes an event trigger and invokes one or more plugins registered to the event trigger to process image data.