All The Claims

1. A method for producing a color filter comprising:
a light shielding part forming step of forming a light shielding part containing a light shielding material and a resin so as to have a film thickness within a predetermined range on a base material;
a photocatalyst containing layer forming step of forming a photocatalyst containing layer which contains a photocatalyst and an organopolysiloxane so as to cover the base material and the light shielding part;
a wettability changed pattern forming step of radiating energy to the photocatalyst containing layer along a predetermined direction, thereby forming a wettability changed pattern having a decreased contact angle with respect to a liquid on the surface of the photocatalyst containing layer; and
a colored layer forming step of applying a colored layer forming coating solution onto the wettability changed pattern, in a consistent supply amount for each of pieces of the pattern, by an ink jet method, and then drying the colored layer forming coating solution while adjusting the volatilization rate of a solvent included in the colored layer forming coating solution, by arranging partitions in the vicinities of the colored layer in regions near the outside of the color filter to prevent the solvent from volatilizing outwards, so as to obtain a colored layer having a more even shape, thereby forming a colored layer.
2. The method for producing a color filter according to claim 1, wherein the colored layer forming coating solution is dried in the colored layer forming step as follows:
regarding ten pixels out of its pixels,
a film thickness of a maximum film thickness portion where a film thickness from a surface of the base material to a surface of the colored layer in the opening portion is maximum, and a film thickness of a minimum film thickness portion where the film thickness from the surface of the base material to the surface of the colored layer in the opening portion is minimum are measured in each pixel, and
a ratio \u03b1 between an average A of the film thicknesses of the maximum film thickness portions and an average B of the film thicknesses of the minimum film thickness portions in the ten pixels (=BA) is in the range of 0.5 to 1.0.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. Power generator apparatus for converting an alternating current (AC) input to a direct current (DC) output, the apparatus comprising:
a clock generator;
a power switching device gated by the clock generator and coupled to the alternating current (AC) input to generate regulated DC output power;
a memory device storing digitized reference data, wherein said stored digitized reference data is a time sequence representation of a string of duty cycles which the power switching device must operate in accordance with the characteristics of the AC input voltage to pulse-width modulate the duty cycle; and
means for comparing the alternating current (AC) input and DC output to effect power circuit function between operating in a first phase at a first frequency and operating in a second phase at a second frequency;
said reference data in said memory device being used to continuously pulse-width modulate (PWM) a duty cycle of a gating signal from the clock generator to the power switch during said second phase.
2. The power generator apparatus according to claim 1 including means for switching from a fixed duty ratio to a continuously pulse-width modulated (PWM) duty ratio of the gating signal and in transitioning from a first frequency to a second frequency.
3. The power generator apparatus according to claim 1 wherein the AC input current is substantially in phase and in waveshape relative to the AC input voltage such that the power factor presented back to the utility is near unity.
4. The power generator apparatus according to claim 1 wherein said first phase at said first frequency is operating in flyback mode and said second phase is operating in both flyback and forward conversion mode.
5. The power generator apparatus according to claim 1 wherein both said first and said second phases are operated in flyback mode.
6. The power generator apparatus according to claim 1 wherein the duty cycle of said first phase at said first frequency is modulated by an error signal comprising the difference between a first voltage which is the regulated output voltage Vo and a second reference voltage VREF such that the duty cycle is varied to maintain a constant output voltage under varying loads.
7. The power generator apparatus according to claim 1, wherein the power switching device is operated at a maximum of 50% duty ratio at full load during the first phase.
8. The power generator apparatus according to claim 1 wherein the input to output voltage ratio is in a range of 5:1 or more.
9. The power generator apparatus according to claim 2 wherein the means for switching in transitioning from the first frequency to the second frequency in the second phase includes means for comparing a rectified input AC voltage and a reference point FCOP to minimize distortion and maintain near unity power factor.
10. The power generator apparatus of claim 2, in which the switching means includes controls operable such that said first phase of operation is when the value of the output voltage reflected back to the input is higher than the absolute value of the instantaneous AC input voltage and said second phase of operation is when the value of the output voltage reflected back to the input is lower than or equal to the absolute value of the instantaneous AC input voltage, wherein during said second phase the operating frequency transitioning from said first frequency to said second frequency is higher than said first frequency.
11. The power generator apparatus according to claim 1, wherein the switching frequency for operating said first phase is equal to approximately 12.5 kHz for 50 Hz to 60 Hz utility.
12. The power generator apparatus according to claim 1, wherein the switching frequency for operating said first phase is equal to approximately 80 kHz for 400 Hz utility.
13. The power generator apparatus of claim 1, wherein said second frequency is approximately twice the said first frequency.
14. The power generator apparatus of claim 1, wherein said first phase of operation is approximately centered around a zero-crossing of the AC input waveform and wherein said second phase of operation is present in the rest of the input AC cycle complementary thereto.
15. The apparatus of claim 1 further comprising:
a transformer including a primary winding in series with the power switching device and a secondary winding;
plural diodes operatively coupled to said primary winding to effect rectification of the AC input;
plural diodes operatively coupled to said secondary winding to perform a rectification function on the output of the secondary winding;
an inductor operatively coupled to the output of said plural diodes operatively coupled to said secondary winding; and
a capacitor across the output to be connected in parallel with the load.
16. The apparatus of claim 15 wherein the rectification function on the output of the secondary winding of the transformer is accomplished through using either Schottky diodes or synchronous rectification.
17. The apparatus of claim 15 wherein said inductor on the secondary having terminals connected to the cathode of each of the top bridge rectifier diodes; and the cathode of the top bridge rectifier diode attached to the negative polarity of the secondary winding of the transformer further connecting to the output capacitor to equally share in delivering energy to the load by the transformer and the secondary inductor in phase 2 operation.
18. The apparatus according to claim 17 in which the transformer and inductor are mutually sized to share energy equally to reduce weight and volume of the transformer and the inductor.
19. Power generator apparatus for converting an alternating current (AC) input to a regulated direct current (DC) output, the apparatus comprising:
a power generator circuit including a single power switching device coupled to said AC input for generating regulated DC output power;
a clock generator providing a clock signal;
means for comparing the AC input and DC output to effect power circuit function by varying the clock rate between operating in a first phase at a first fixed frequency and operating in a second phase at a second fixed frequency;
means for switching from the first fixed frequency to the second fixed frequency, wherein the switching means includes controls operable such that said first phase of operation is when the value of the output voltage reflected back to the input is higher than the absolute value of the instantaneous AC input voltage and said second phase of operation is when the value of the output voltage reflected back to the input is lower than or equal to the absolute value of the instantaneous AC input voltage;
a memory device storing at least representative portions of digitized reference data; and
control means using said data to continuously pulse-width modulate the duty cycle of the clock signal to said power switching device during said second phase.
20. The power generator apparatus of claim 19 wherein the second operating frequency of the second phase is higher than the operating frequency of the first phase leading to reduced peak currents and stresses in the power generator circuit.
21. The power generator apparatus of claim 20 including a transformer wherein the second operating frequency of the second phase is higher than the operating frequency of the first phase leading to reduction in system weight and volume.
22. The power generator apparatus of claim 19 in which the clock generator is operative to employ two discrete frequencies in its operation within any given AC cycle to spread the noise spectrum and reduce the magnitude of its total harmonic content and EMIRFI effects.
23. The power generator apparatus according to claim 19 further comprising:
a transformer including a primary winding and a secondary winding;
plural diodes operatively coupled to said primary winding;
plural diodes operatively coupled to said secondary winding to effect rectification;
a single power switching device operatively coupled to said plural diodes of said primary winding;
an inductor operatively coupled to said secondary winding and said plural diodes; and
a capacitor connected at the output in parallel with the load.
24. The apparatus of claim 23 wherein said inductor on the secondary having terminals connected to the cathode of each of the top bridge rectifier diodes; and the cathode of the top bridge rectifier diode attached to the negative polarity of the secondary winding of the transformer further connecting to the output capacitor to equally share in delivering energy to the load by the transformer and the inductor in the second phase of operation.
25. The power generator apparatus according to claim 23 wherein the duty cycle of said first phase at said first frequency is maintained constant corresponding to a given load and the second phase is continuously pulse-width modulated.
26. The power generator apparatus according to claim 23, wherein the second frequency is approximately an integer multiple of the first frequency.
27. The power generator apparatus according to claim 23, wherein the first phase of operation is approximately centered around a zero-crossing of the AC input waveform and wherein the second phase of operation is complementary thereto.
28. The power generator apparatus according to claim 19 in which the control means utilizes duty cycle control in conjunction with two discrete operating frequencies wherein the duty cycle in the first phase of operation is fixed for a fixed load and varies when the load varies.
29. The power generator apparatus according to claim 28 further comprising:
a transformer including a primary winding and a secondary winding;
plural diodes operatively coupled to said primary winding;
plural diodes operatively coupled to said secondary winding;
a single power switching device operatively coupled to said plural diodes of said primary winding;
an inductor operatively coupled to said secondary winding and said plural diodes; and
a capacitor connected at the output in parallel with the load; wherein
the converter apparatus operating in flyback mode with a fixed duty cycle corresponding to the given load, when the output voltage reflected back to the input is higher than the absolute value of the instantaneous AC input voltage and the converter apparatus operating in a combination of flyback and forward conversion modes, with pulse-width modulated duty cycle, when the output voltage reflected back to the input is lower than or equal to the absolute value of the instantaneous AC input voltage.
30. The power generator apparatus according to claim 29 wherein the total harmonic content (THC) in the AC input current is between 1% to 2%.
31. The power generator apparatus according to claim 19 wherein the control means is integrated into an integrated circuit or a compact hybrid circuit to define a compact intelligent module.
32. The power generator apparatus according to claim 19 wherein the control means employs a control scheme which continuously compares the AC input with the regulated output to effect power control function between operating in a first phase at a first frequency when the output reflected back to the input is higher than the absolute value of the AC input and operating in a second phase wherein the operating frequency transitioning from said first frequency to a second frequency when the output reflected back to the input is lower than the instantaneous AC input within a cycle.
33. The power generator according to claim 32 wherein the first phase is operated in flyback mode and the second phase is operated in a combination of flyback mode and forward mode.
34. The power generator according to claim 32 wherein said apparatus is continuously operated in the flyback mode.
35. The power converter apparatus according to claim 21 wherein the input to output transformation is adjusted to have high current and low voltage capability suitable for charging batteries.
36. A method for AC-to-DC power conversion comprising:
inputting AC Power at a predetermined AC frequency and voltage Vac;
full-wave rectifying the input AC power to produce a full-wave rectified voltage Vi having an amplitude proportional to absolute value Vac;
applying voltage Vi across a primary of a transformer in series with a gate-controlled switch to produce a current IM;
coupling a secondary of the transformer to an output rectifying bridge to produce a regulated output voltage Vo across an output capacitor Co to a load;
comparing input voltage Vi with a voltage Vo\u2032 where Vo\u2032=Vo(N1N2) and N1N2 is the inverse turns ratio of the transformer;
if Vi is less than Vo\u2032, then clocking the gate-controlled switch at a first fixed frequency f1, so that current IM is a discontinuous flyback current; and
if Vi is greater than Vo\u2032, then clocking the gate-controlled switch at a second fixed frequency f2, where f2 is unequal to f1 and the current IM is a discontinuous flyback and forward current.
37. A method according to claim 36, in which f2 is greater than f1.
38. A method according to claim 36, in which f2 is approximately an integer multiple of f1.
39. A method according to claim 36, in which, when clocking at f1 and for an invariant load, the switch is clocked at a fixed duty ratio.
40. A method according to claim 39 in which the duty cycle has a maximum of 50 percent.
41. A method according to claim 36, in which, when clocking at f1, and for a load which is increasing, the switch is clocked at a proportionately increasing duty ratio.
42. A method according to claim 41 in which the duty cycle has a maximum of 50 percent.
43. A method according to claim 36, in which, when clocking at f1, as Vi increases, the current IM has an average in the discontinuous flyback current which increases proportionately to voltage Vi.
44. A method according to claim 36, in which, when clocking at f2, the switch is clocked at a duty cycle which is continuously pulse-width modulated with pulses whose duty ratio D is proportionate to the square root of 1(A+BVI) where A and B are constants dependent on primary and secondary inductance values, the transformer turns ratio and the output voltage.
45. A method according to claim 44, in which the maximum duty ratio is 50 percent.
46. A method according to claim 36, in which the output rectifying bridge includes an inductor positioned in series with the secondary of the positive polarity terminal of the transformer through a diode to store and discharge energy during a forward mode of operation of the bridge.
47. A method according to claim 46, in which an inductance L of the inductor is proportioned to an inductance L1 of the primary of the transformer to apportion energy supplied to the load between the inductor and the transformer.
48. A method according to claim 46, in which the frequency f2 is selected in proportion to one or more of the size and rating of the transformer.
49. A method according to claim 36, in which the comparing step between Vi and Vo\u2032 during each cycle of the input AC power alternates the clocking frequency between two discrete values f1 and f2 to synthesize the regulated output voltage Vo in relation to a reference voltage.
50. A method according to claim 46, in which the load is a reactive load and the inductor and transformer are proportioned so that a power factor as seen by the input AC power is close to unity.
51. A method according to claim 36 including, during valleys of the rectified input AC voltage, operating in flyback mode with a fixed duty cycle and a fixed first frequency at a given load with a maximum duty cycle of 50% at full load, and when the rectified input AC voltage exceeds the reflected output voltage, operating in flyback as well as the forward conversion mode at the second fixed frequency which is a multiple of the first frequency while modulating the duty cycle continuously.
52. A method according to claim 36, in which, when operating at the second frequency f2 the switch is clocked at a duty cycle which is continuously pulse-width modulated with pulses whose duty ratio D is in accordance to Equation (39)
D
=
V
m

\u2062
Sin
\u2062
\u2062
\u03b8
8
\u2062

{
2.5
\u2062

V
m

\u2062
Sin
\u2062
\u2062
\u03b8

–

2
\u2062

(
N
1
N
2
)

\u2062

V
0
}
.
53. Power generator apparatus for converting an alternating current (AC) input to a direct current (DC) output, the apparatus comprising:
a clock generator;
a power switching device gated by the clock generator and coupled to the alternating current (AC) input to generate regulated DC output power;
a memory device storing digitized reference data; and
means for comparing the alternating current (AC) input and DC output to effect power circuit function between operating in a first phase at a first frequency and operating in a second phase at a second frequency, wherein said first phase at said first frequency is operating in flyback mode and said second phase is operating in both flyback and forward conversion mode;
said reference data in said memory device being used to continuously pulse-width modulate (PWM) a duty cycle of a gating signal from the clock generator to the power switch during said second phase.
54. Power generator apparatus for converting an alternating current (AC) input to a direct current (DC) output, the apparatus comprising:
a clock generator;
a power switching device gated by the clock generator and coupled to the alternating current (AC) input to generate regulated DC output power;
a memory device storing digitized reference data; and
means for comparing the alternating current (AC) input and DC output to effect power circuit function between operating in a first phase at a first frequency and operating in a second phase at a second frequency; and
means for switching from a fixed duty ratio to a continuously pulse-width modulated (PWM) duty ratio of the gating signal and in transitioning from a first frequency to a second frequency, wherein the means for switching in transitioning from the first frequency to the second frequency in the second phase includes means for comparing a rectified input AC voltage and a reference point FCOP to minimize distortion and maintain near unity power factor;
said reference data in said memory device being used to continuously pulse-width modulate (PWM) a duty cycle of a gating signal from the clock generator to the power switch during said second phase.
55. Power generator apparatus for converting an alternating current (AC) input to a direct current (DC) output, the apparatus comprising:
a clock generator;
a power switching device gated by the clock generator and coupled to the alternating current (AC) input to generate regulated DC output power;
a memory device storing digitized reference data;
means for comparing the alternating current (AC) input and DC output to effect power circuit function between operating in a first phase at a first frequency and operating in a second phase at a second frequency; and
means for switching from a fixed duty ratio to a continuously pulse-width modulated (PWM) duty ratio of the gating signal and in transitioning from a first frequency to a second frequency, the switching means including controls operable such that said first phase of operation is when the value of the output voltage reflected back to the input is higher than the absolute value of the instantaneous AC input voltage and said second phase of operation is when the value of the output voltage reflected back to the input is lower than or equal to the absolute value of the instantaneous AC input voltage, wherein during said second phase the operating frequency transitioning from said first frequency to said second frequency is higher than said first frequency;
said reference data in said memory device being used to continuously pulse-width modulate (PWM) a duty cycle of a gating signal from the clock generator to the power switch during said second phase.
56. Power generator apparatus for converting an alternating current (AC) input to a direct current (DC) output, the apparatus comprising:
a clock generator;
a power switching device gated by the clock generator and coupled to the alternating current (AC) input to generate regulated DC output power;
a memory device storing digitized reference data;
means for comparing the alternating current (AC) input and DC output to effect power circuit function between operating in a first phase at a first frequency and operating in a second phase at a second frequency;
said reference data in said memory device being used to continuously pulse-width modulate (PWM) a duty cycle of a gating signal from the clock generator to the power switch during said second phase;
a transformer including a primary winding in series with the power switching device and a secondary winding;
plural diodes operatively coupled to said primary winding to effect rectification of the AC input;
plural diodes operatively coupled to said secondary winding to perform a rectification function on the output of the secondary winding;
an inductor operatively coupled to the output of said plural diodes operatively coupled to said secondary winding; and
a capacitor across the output to be connected in parallel with the load.

1. A system comprising:
a processor;
a dynamic pinning remote direct memory access helper on the processor core; and
a network interface controller comprising:
a network interface to connect the network interface controller to a second network interface controller on a remote computing node;
a system bus interface to connect the network interface controller to the processor via a system bus;
buffers usable as cacheable memory regions for the processor; and
a direct memory access engine communicatively coupled to the dynamic pinning remote direct memory access helper via the system bus interface and to receive a request for data,

the dynamic pinning remote direct memory access helper to:
decompose the data to be transferred through a remote direct memory access into at least first and second remote sections, each of the first and second sections being less than an entire memory page;
pin the first remote section until a first portion of the data from the first remote section is transferred to the remote computing node;
after the first portion of the data is transferred, release the first remote section;
after releasing the first remote section, pin the second remote section until a second portion of the data from the second remote section is transferred to the remote computing node; and
after the second portion of the data is transferred, release the second remote section, wherein the first section is pinned at a first time and for a first duration sufficient to transfer the first section, and the second section is pinned at a second time for a second duration sufficient to transfer the second section.
2. The system of claim 1, wherein the system is implemented on a single chip and the processor comprises a processor core.
3. The system of claim 1, wherein the dynamic pinning remote direct memory access helper is to create local sections to receive second data decomposed into third and fourth remote sections on the remote computing node, and to sequentially pin and release each of third and fourth local sections separately as the second data is sequentially transferred into the third and fourth local sections; and
the direct memory access engine is to perform a second remote direct memory access for each local section.
4. A system comprising:
a dynamic pinning remote direct memory access helper in a kernel on a processor,
for a request for data, the dynamic pinning remote direct memory access helper to:
create at least first and second local sections to receive the data decomposed into at least first and second remote sections on a remote computing node,
pin the first local section until a first portion of the data from the first remote section is received,
after the first portion of the data is received, release the first local section,
after releasing the first local section, pin the second local section until a second portion of the data from the second remote section is received, and
after the second portion of the data is received, release the second local section; and

a direct memory access engine to perform a remote direct memory access for each local section via the network interface until all of the data is received.
5. The system of claim 4, further comprising:
a swapper in the kernel, wherein when a head of a remaining local section is not resident in memory, the swapper is to swap the head into memory.
6. The system of claim 4, further comprising a virtual network interface controller layer to provide a datagram service to receive frames of data for each local section.
7. The system of claim 4, further comprising a registered virtual buffer mapped to physical memory, each local section being in the virtual buffer.
8. The chip of claim 7, further comprising:
system memory, at least one of the sections being a remote section of a send side node, the network interface controller to perform the remote direct memory access by retrieving the remote section from addresses in the system memory and transferring the remote section from the network interface controller to a network interface controller in a receive side node via a network.
9. The chip of claim 7, further comprising:
system memory, at least one of the sections being a local section of a receive side node, and the region of memory is received at the network interface controller and stored in the local section.
10. The chip of claim 7, further comprising:
a kernel on the processor core, the kernel including the dynamic pinning remote direct memory access helper.
11. The system of claim 4, wherein:
the dynamic pinning remote direct memory access helper is to decompose second data to be transferred through a second remote direct memory access into third and fourth remote sections and to dynamically pin and release the third and fourth remote sections separately as the second data is transferred into the third and fourth remote sections; and
the direct memory access engine is to perform the second remote direct memory access for each remote section via the network interface until the second data is transferred.
12. The system of claim 4, wherein the system is implemented on a single chip and the processor comprises a processor core.
13. A chip comprising:
a processor core;
a dynamic pinning remote direct memory access helper on the processor core; and
a network interface controller communicatively coupled to the dynamic pinning remote direct memory access helper, the network interface controller to perform a remote direct memory access of a region of memory for a request for data, the dynamic pinning remote direct memory access helper to:
decompose the region of memory into at least first and second sections,
pin the first section until a first portion of the region of memory is accessed;
after the first portion of the region of memory is accessed, release the first section;
after releasing the first section, pin the second section until a second portin of the region of memory is accessed; and
after the second portion of the region of memory is accessed, release the second section.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A system for monitoring relative movement of a surface area, comprising:
a host computer;
a grid of sensors at known distances from each other, spaced within the surface area;
wherein the host computer is operable to wirelessly and individually instruct each sensor to operate in an interrogator mode or a responder mode;
wherein each sensor has radar circuitry for sending and receiving a continuous wave signal, such that it may send the signal to, and receive the signal back from, a neighboring sensor, when the former sensor is in interrogate mode;
wherein each sensor has delay circuitry for delaying and returning a signal received from a neighboring sensor, when the former sensor is in responder mode;
wherein each sensor has control circuitry for determining whether the sensor is in interrogator or responder mode and for calculating phase difference measurements of a returned signal.
2. The system of claim 1, wherein each sensor has an omni-directional antenna.
3. The system of claim 1, wherein the known distances are known to within one-half of the wavelength of the continuous wave.
4. The system of claim 1, wherein the control unit of each sensor is further operable to transmit distance measurement data to the host computer.
5. The system of claim 1, wherein each sensor further has initialization circuitry for using a pulse burst radar process to determine the inter-sensor distances with an accuracy of less than the carrier wavelength.
6. The system of claim 1, wherein the host computer and sensors wirelessly communicate using a wireless LAN communications standard.
7. The system of claim 1, wherein the inter-sensor spacing is sufficiently close such that they are operational at 1 mW of power of less.
8. The system of claim 1, wherein the host computer and sensors are operational at a single carrier frequency.
9. A method of monitoring relative movement of a surface area, comprising:
placing a grid of sensors at known distances from each other, spaced within the defined area;
using a host computer to wirelessly and individually instruct each sensor to operate in an interrogator mode or a responder mode;
wherein each sensor has radar circuitry for sending and receiving a continuous wave signal, such that it may send the signal to, and receive the signal back from a neighboring sensor, when the former sensor is in interrogator mode;
wherein each sensor has delay circuitry for delaying and returning a signal received from a neighboring sensor, when the former sensor is in responder mode;
wherein each sensor has control circuitry for determining whether the sensor is in interrogator or responder mode and for calculating phase difference measurements of the returned signal.
10. The method of claim 9, wherein each sensor has an omni-directional antenna.
11. The method of claim 9, wherein the known distances are known to within one-half of the wavelength of the continuous wave.
12. The method of claim 9, wherein the control unit of each sensor is further operable to transmit distance measurement data to the host computer.
13. The method of claim 9, wherein each sensor further has initialization circuitry for using a pulse burst radar process to determine the inter-sensor distances with an accuracy of less than the carrier wavelength.
14. The method of claim 9, wherein the host computer and sensors wirelessly communicate using a wireless LAN communications standard.
15. The method of claim 9, wherein the inter-sensor spacing is sufficiently close such that they are operational at 1 mW of power of less.
16. The method of claim 9, wherein the host computer and sensors are operational at a single carrier frequency.