All The Claims

1. A current amplifier circuit comprising:
first and second current input terminals to receive a first current;
an operational amplifier having a non-inverting input terminal coupled to a bias voltage and the second current input terminal, an inverting input terminal coupled to the first current input terminal, and an output terminal to provide an output of the operational amplifier;
a current mirror amplifier having an amplification factor, an input terminal and an output terminal and configured to provide an amplified output current that is the product of the first current and the amplification factor of the current mirror amplifier; and
a transistor connected between the inverting input terminal of the operational amplifier and the input terminal of the current mirror amplifier, wherein the transistor is controlled by the output of the operational amplifier.
2. The current amplifier of claim 1, wherein the operational amplifier is comprised of MOS transistors.
3. The current amplifier of claims 1, wherein the current mirror amplifier is comprised of MOS transistors.
4. The current amplifier circuit of claim 1, wherein the current mirror amplifier comprises a Wilson current mirror.
5. The current amplifier of claim 1, wherein the transistor is an MOS transistor.
6. The current amplifier of claim 1, further comprising a photodiode coupled to the first and second current input terminals to generate the first current.
7. The current amplifier of claim 1, further comprising a CD read head coupled to the first and second current input terminals to generate the first current.
8. The current amplifier of claim 7, further comprising CD signal processing circuitry, wherein the current amplifier and the CD signal processing circuitry are integrated onto an integrated circuit.
9. A current amplifier comprising:
a differential amplifier having MOS input transistors of a first conductivity type, a non-inverting input terminal coupled to a bias voltage, an inverting input terminal coupled to an input current, and an output terminal;
a first MOS transistor of a second conductivity type and a second MOS transistor of the first conductivity type, the first and second MOS transistors each having a control gate, wherein the control gate of the first MOS transistor is coupled to the output terminal of the differential amplifier, the first MOS transistor is connected between a first reference voltage and the control gate of the second MOS transistor, and the second MOS transistor is connected between the inverting input terminal of the differential amplifier and a second reference voltage; and
a current mirror amplifier having an input terminal coupled to the control gate of the second MOS transistor, and an output terminal to provide an amplified output current.
10. The current amplifier of claim 9 wherein the current mirror amplifier comprises a Wilson current mirror.
11. The current amplifier of claim 9 wherein the MOS input transistors of the differential amplifier are n-channel transistors, the first MOS transistor is a p-channel transistor, the first reference voltage is a supply voltage and the second reference voltage is a ground.
12. The current amplifier of claim 9, further comprising a photodiode to generate the input current for the differential amplifier.
13. The current amplifier of claim 9, further comprising a CD read head to generate the input current for the differential amplifier.
14. A current amplifier comprising:
a first input terminal to receive a current;
a second input terminal to receive a bias voltage;
a first MOS transistor of a first conductivity type having a control gate coupled to the first input terminal;
a second MOS transistor of the first conductivity type having a control gate coupled to the second input terminal;
a constant current source having a first terminal and a second terminal, wherein the first MOS transistor is connected between the first terminal of the constant current source and a first node;
a third and a fourth MOS transistor of a second conductivity type and each having a control gate, wherein the second MOS transistor is connected between the first terminal of the constant current source and the control gates of the third and fourth MOS transistors, the third MOS transistor is connected between the first node and a reference voltage, and the fourth MOS transistor is connected between the control gate of the fourth MOS transistor and the reference voltage;
a fifth MOS transistor of the second conductivity type and having a control gate, wherein the control gate of the fifth MOS transistor is coupled to the first node;
a sixth MOS transistor of the first conductivity type, wherein the fifth MOS transistor is connected between the control gate of the sixth MOS transistor and the reference voltage, and the sixth MOS transistor is connected between the first input terminal and the second terminal of the constant current source; and
a current mirror amplifier having an input terminal coupled to the gate of the sixth MOS transistor and an output terminal.
15. The current amplifier of claim 14, wherein the first and second MOS transistors are n-channel MOS transistors.
16. The current amplifier of claim 14, wherein the current mirror amplifier comprises a Wilson current mirror.
17. A current amplifier comprising:
first and second current input terminals to receive a first current to be amplified;
an operational amplifier having a low impedance inverting input terminal coupled to the first current input terminal, a non-inverting input terminal coupled to the second current input terminal, and an output terminal;
a feedback loop comprising a transistor, the feedback loop being connected between the output terminal and the inverting input terminal of the operational amplifier; and
a current mirror having an amplification factor, an input terminal to receive a current conducted through the transistor in the feedback loop and an output terminal to provide an amplified output current that is the product of the first current to be amplified and the amplification factor of the current mirror, the input terminal of the current mirror being coupled to the transistor.
18. The current amplifier of claim 17, wherein the operational amplifier is comprised of MOS transistors.
19. The current amplifier of claim 17, wherein the current mirror amplifier comprises a Wilson current mirror.
20. A current amplifier comprising:
a current input terminal to receive a current to be amplified;
a voltage amplifier circuit having a first input terminal coupled to the current input terminal, a second input terminal and an output terminal;
a feedback loop having overall negative feedback coupled between the output terminal and the first input terminal of the voltage amplifier circuit; and
a current amplifier circuit coupled to the feedback loop through a continuous current path, the continuous current path conducting a current proportional to the current to be amplified, and having an output terminal providing an output current proportional to the current to be amplified.
21. The current amplifier of claim 20 wherein the feedback loop comprises a p-channel MOS transistor.
22. The current amplifier of claim 20 wherein the feedback loop comprises an n-channel MOS transistor.
23. The current amplifier of claim 20 wherein the current amplifier circuit comprises a CMOS transistor.
24. The current amplifier of claim 20 wherein the current amplifier circuit composes a current mirror.
25. The current amplifier of claim 24 wherein the current mirror is a Wilson current mirror.
26. A method of amplifying a current signal, the method comprising:
conducting the current signal between first and second inputs of an amplifier;
receiving a bias voltage signal at the second amplifier input;
providing negative feedback to the first amplifier input using a first transistor and a second transistor;
conducting a current of a predetermined multiple of the current of the current signal through the second transistor; and
generating an amplified current using an output transistor coupled to the second transistor, the amplified output current being a predetermined multiple of the current conducted through the second transistor.
27. The method of claim 26, wherein the step of generating an amplified current comprises mirroring in the output transistor the current flow through the second transistor.
28. The method of claim 26, comprising generating the current signal in response to data patterns detected in a compact disk by a read head.
29. The method of claim 26, further comprising integrating a signal processing circuit and a current amplifier circuit in a single integrated circuit.
30. A current amplifier circuit comprising:
first and second input terminals to receive a first current to be amplified;
an operational amplifier having a non-inverting input terminal coupled to a reference voltage and to the second input terminal, an inverting input terminal coupled to the first input terminal and an output terminal;
a current input circuit coupled to the first and second input terminals;
a feedback circuit having a control terminal coupled to the output terminal of the operational amplifier, a first terminal coupled to the inverting input terminal of the operational amplifier and a second terminal; and
a current mirror circuit having its input connected to the second terminal of the feedback circuit and having an output terminal providing an output of the current amplifier circuit, wherein the feedback circuit is configured to maintain a substantially zero bias voltage across the current input circuit and the output of the current amplifier is proportional to the first current to be amplified.
31. The current amplifier circuit of claim 30 wherein the feedback circuit includes an MOS transistor having a gate coupled to the output terminal of the operational amplifier, a first sourcedrain coupled to the inverting input terminal of the operational amplifier and a second sourcedrain coupled to the input of the current mirror circuit.
32. The current amplifier circuit of claim 30 wherein the current input circuit includes a photo diode having one terminal coupled to the first input terminal.
33. The current amplifier circuit of claim 32 wherein the photo diode has a second terminal coupled to the second input terminal.
34. A current amplifier circuit comprising:
an operational amplifier having an inverting input terminal coupled to a reference voltage, a non-inverting input terminal and an output terminal;
a current input circuit coupled to the inverting and the non-inverting input terminals of the operational amplifier;
a negative feedback circuit having a control terminal coupled to the output terminal of the operational amplifier, a first conduction terminal coupled to the non-inverting input of the operational amplifier and a second conduction terminal; and
an output circuit having a control terminal coupled to the control terminal of the feedback circuit, a first terminal coupled to the second conduction terminal of the feedback circuit and an output terminal providing an output current of the current amplifier circuit proportional to a current generated by the current input circuit.
35. A method of amplifying a current signal, the method comprising:
receiving a current signal from a photo-sensitive device;
conducting the current signal between a low impedance amplifier input and a second amplifier input;
receiving a bias voltage at the second amplifier input;
providing negative feedback to the low impedance amplifier input by conducting a current substantially equal to the current of the current signal through a first transistor so as to maintain a substantially zero bias voltage across the photo-sensitive device; and
generating an amplified current using an output transistor coupled to the first transistor, the amplified output current being a predetermined multiple of the current conducted through the first transistor.
36. A method of amplifying a current signal, the method comprising:
receiving a current signal from a photo-sensitive device;
conducting the current signal between a low impedance amplifier input and a second amplifier input;
receiving a bias voltage at the second amplifier input;
providing negative feedback to the low impedance amplifier input by conducting a current substantially equal to the current of the current signal through a first transistor so as to maintain a substantially zero bias voltage across the photo-sensitive device; and
generating an amplified current using a current mirror coupled to the first transistor, the amplified output current being a predetermined multiple of the current conducted through the first transistor.
37. A current amplifier circuit comprising:
first and second input terminals for coupling to a photo-sensitive device;
an operational amplifier having a non-inverting input terminal coupled to a bias voltage and to the first input terminal, an inverting input terminal coupled to the second input terminal, and an output terminal to provide an output of the operational amplifier;
a current mirror amplifier having an input terminal and an output terminal to provide an amplified output current proportional to a current conducted between the first and second input terminals; and
a transistor connected between the inverting input terminal of the operational amplifier and the input terminal of the current mirror amplifier, wherein the transistor is controlled by the output of the operational amplifier and the current amplifier circuit is configured to maintain a substantially zero bias voltage across the photo-sensitive device.
38. A current amplifier comprising:
a differential amplifier having MOS input transistors of a first conductivity type, a non-inverting input terminal coupled to a bias voltage, an inverting input terminal coupled to an input current, and an output terminal;
a first MOS transistor of a second conductivity type and a second MOS transistor of the first conductivity type, the first and second MOS transistors each having a control gate, wherein the control gate of the first MOS transistor is coupled to the output terminal of the differential amplifier, the first MOS transistor is connected between a first reference voltage and the control gate of the second MOS transistor, and the second MOS transistor is connected between the inverting input terminal of the differential amplifier and a second reference voltage; and
a current mirror amplifier having an input terminal coupled to the control gate of the second MOS transistor, and an output terminal to provide an output current proportional to the input current.
39. A method of amplifying a current signal, the method comprising:
coupling a photo-sensitive device across first and second input terminals of an operational amplifier;
maintaining a substantially zero bias voltage across the photo-sensitive device by applying negative feedback through a feedback loop to the first terminal of the operational amplifier; and
conducting a current substantially equal to current conducted through the photo-sensitive device through a first transistor of a current mirror circuit, wherein the first transistor of the current mirror circuit is coupled to the first terminal of the operational amplifier through a continuous current path.
40. The method of claim 39, wherein a control terminal of the first transistor is coupled to an output terminal of the operational amplifier and a current carrying terminal of the first transistor is coupled to the first terminal of the operational amplifier.
41. The method of claim 39, further comprising amplifying the current conducted through the first transistor.
42. The method of claim 39, wherein the feedback loop comprises a second transistor and a current substantially equal to the current conducted through the first transistor is conducted through the second transistor.
43. A current amplifier circuit comprising:
first and second input terminals for receiving an input current from a photo-sensitive device;
an operational amplifier having a first input coupled to a bias voltage and the first input terminal, a second input coupled to the second input terminal, and an output to provide an output of the operational amplifier; and
a current mirror having an input terminal coupled through a continuous current path to the second input of the operational amplifier, a control terminal coupled to the output of the operational amplifier, and an output terminal to provide an amplified output current proportional to the input current, wherein the current amplifier circuit is configured to maintain a substantially zero bias voltage across the photo-sensitive device.
44. The current amplifier circuit of claim 43 wherein the control terminal of the current mirror is directly connected to the output of the operational amplifier.
45. The current amplifier circuit of claim 43 wherein the input terminal of the current mirror is directly connected to the second input of the operational amplifier.
46. The current amplifier of claim 45 wherein the control terminal of the current mirror is directly connected to the output of the operational amplifier.
47. The current amplifier circuit of claim 43, further comprising a transistor connected between the input terminal of the current mirror and the second input of the operational amplifier, wherein a control terminal of the transistor is connected to the output of the operational amplifier and the control terminal of the current mirror is coupled to the input terminal of the current mirror.
48. The current amplifier circuit of claim 43 wherein the photo-sensitive device comprises a photo-diode.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A printing apparatus comprising:
a heat roller for transferring heat to a toner image formed on a printing medium;
a first temperature sensor for sensing a temperature of the heat roller;
a first heat source, which is installed inside the heat roller for heating the heat roller;
a second heat source, which is installed inside the heat roller and has a lower heat capacity than the first heat source for heating the heat roller;
a pressure roller, which is installed to face the heat roller and press the printing medium toward the heat roller; and
a control unit for controlling the first heat source and the second heat source based on the temperature sensed by the first temperature sensor, wherein the control unit is configured to turn off the first heat source and to turn on the second heat source upon determination that the temperature sensed by the first temperature sensor is higher than a first predetermined temperature.
2. The printing apparatus of claim 1, further comprising:
a third heat source, which is installed inside the pressure roller for heating the pressure roller, wherein the control unit further controls the third heat source.
3. The printing apparatus of claim 2, further comprising:
a second temperature sensor for sensing a temperature of the pressure roller, wherein the control unit controls the third heat source based on the temperature sensed by the second temperature sensor.
4. The printing apparatus of claim 2, wherein the control unit is further configured to:
turn on the third heat source at a predetermined short interval after the control unit turns on the first heat source.
5. The printing apparatus of claim 4, wherein the predetermined short interval is less than about 500 ms.
6. The printing apparatus of claim 2, wherein the control unit is further configured to turn on the first heat source and turn off the second heat source in a warm-up mode.
7. The printing apparatus of claim 6, wherein the control unit is further configured to:
control the first, second, and third heat sources in at least two steps, such that the temperature of the heat roller can reach a second predetermined temperature which is higher than a normal temperature in a first step, and the temperature of the heat roller can reach the first predetermined temperature which is higher than the second predetermined temperature and is high enough to fuse and fix toner in a second step.
8. The printing apparatus of claim 7, wherein the control unit is further configured to:
turn on the first heat source using a first signal with a high duty ratio if the temperature of the heat roller ranges from the normal temperature to the second predetermined temperature; and
turn on the first heat source using a second signal with a duty ratio lower than that of the first signal if the temperature of the heat roller ranges from the second predetermined temperature to the first predetermined temperature.
9. The printing apparatus of claim 8, wherein the duty ratio of the first signal is about 100%, and the duty ratio of the second signal is about 33%.
10. The printing apparatus of claim 7, wherein the control unit is further configured to:
turn on the second heat source in a print mode in which the printing apparatus performs a printing operation; and
turn on the second heat source in a stand-by mode in which a print signal is waited for.
11. The printing apparatus of claim 10, wherein the control unit is further configured to:
control the first, second and third heat sources in the print mode and the stand-by mode so that the first through third heat sources can maintain the first predetermined temperature.
12. The printing apparatus of claim 11, wherein the control unit is further configured to:
turn on at least one of the first heat source and the third heat source in the print mode and the stand-by mode while the temperature of the heat roller is lower than the first predetermined temperature.
13. The printing apparatus of claim 12, wherein the control unit is further configured to:
turn on the third heat source at a predetermined short interval after the control unit turns on the first heat source.
14. The printing apparatus of claim 13, wherein the predetermined short interval is less than about 500 ms.
15. The printing apparatus of claim 10, wherein the control unit is further configured to:
control the second heat source using a third signal with a duty ratio of about 50% to turn on the second heat source.
16. The printing apparatus of claim 1, further comprising a driving motor for driving the heat roller and the pressure roller.
17. The printing apparatus of claim 16, wherein the driving motor is configured to stop in a warm-up mode until the temperature of the heat roller reaches a second predetermined temperature that is higher than a normal temperature.
18. The printing apparatus of claim 16, wherein the driving motor is configured to stop in a stand-by mode in which a print signal is waited for.
19. A fusing apparatus comprising:
a heat roller for transferring heat to a toner image formed on a printing medium;
a first heat source, which is installed inside the heat roller for heating the heat roller;
a second heat source, which is installed inside the heat roller and has a lower heat capacity than the first heat source for heating the heat roller; and
a pressure roller, which is installed to face the heat roller and press the printing medium toward the heat roller,
wherein the first heat source is turned off and the second heat source is turned on upon determination that the temperature of the heat roller is higher than a predetermined temperature.
20. The fusing apparatus of claim 19, further comprising a third heat source, which is installed inside the pressure roller for heating the pressure roller.
21. A method of controlling a fusing temperature in a printing apparatus, which includes a heat roller for transferring heat to a toner image formed on a printing medium and a pressure roller facing the heat roller for pressing the printing medium toward the heat roller to fuse the toner image to the printing medium, the method comprising the steps of:
sensing a temperature of the heat roller;
determining whether the temperature of the heat roller is a first predetermined temperature which is higher than a normal temperature, or is a second predetermined temperature which is higher than the first predetermined temperature and is high enough to fuse and fix toner; and
controlling a first heat source which is installed inside the heat roller, and a second heat source which is installed inside the heat roller and has a lower heat capacity than the first heat source, according to the determined temperature of the heat roller, wherein the first heat source is turned off and the second heat source is turned on upon determination that the temperature sensed by the first temperature sensor is higher than the second predetermined temperature.
22. The method of claim 21, further comprising the step of:
turning on the first heat source and turning off the second heat source in a warm-up mode.
23. The method of claim 21, further comprising the step of:
controlling the first heat source and the second heat source such that the first heat source and the second heat source are not turned on simultaneously in a print mode in which the printing apparatus performs a printing operation or in a stand-by mode in which a print signal is waited for.
24. The method of claim 21, further comprising the steps of:
controlling the first heat source using a signal with a higher duty ratio if the temperature of the heat roller ranges from the normal temperature to the first predetermined temperature; and
controlling the first heat source using a signal with a lower duty ratio if the temperature of the heat roller ranges from the first predetermined temperature to the second predetermined temperature.
25. The method of claim 21, further comprising the step of:
controlling a third heat source which is installed inside the pressure roller to heat the pressure roller, wherein the third heat source is turned on in a warm-up mode.
26. The method of claim 25, further comprising the step of:
turning on the first heat source and the third heat source in a print mode and a stand-by mode while the temperature of the heat roller is lower than the second predetermined temperature, wherein the third heat source is turned on at a predetermined short interval after the first heat source is turned on.
27. The method of claim 21, further comprising the step of:
controlling a driving motor which drives the heat roller and the pressure roller to stop until the temperature of the heat roller reaches the first predetermined temperature which is higher than the normal temperature or when in a stand-by mode in which a print signal is waited for.

What is claimed is:

1. An RF connector of a coaxial cable comprising:
an inner conductor;
an outer conductor surrounding the inner conductor;
a dielectric cylinder located between the inner and outer conductors;
an outer radial barb projecting radially inwardly from the outer conductor into the spacer; and
an axial barb projecting axially from the outer conductor into the spacer.
2. The RF connector of claim 1, wherein the axial barb has a right triangle shape.
3. The RF connector of claim 1, wherein the outer radial barb has a right triangle shape.
4. The RF connector of claim 1, further comprising an inner radial barb projecting radially outwardly from the inner conductor into the spacer.
5. The RF connector of claim 4, wherein the inner radial barb has a right triangle shape.
6. The RF connector of claim 1, wherein the outer conductor has a shoulder from which the axial barb projects.
7. The RF connector of claim 1, wherein the height of at least one of the outer radial barb and axial barb is in a range of 0.008 to 0.012 inches.
8. The RF connector of claim 1, wherein an inclined surface of the axial barb faces outwardly.
9. The RF connector of claim 1, wherein an inclined surface of the axial barb faces the outer radial barb.
10. The RF connector of claim 1, wherein the outer conductor has a shoulder portion defining a step surface on which the axial barb is located, and a vertical surface of the outer radial barb is parallel to the step surface of the shoulder portion.
11. The RF connector of claim 10, wherein the axial barb has an inclined surface which faces outwardly.
12. The RF connector of claim 11, wherein the inclined surface of said axial barb is inclined with respect to said step surface.
13. The RF connector of claim 10, wherein the vertical surface of the outer radial barb faces said step surface.
14. The RF connector of claim 13, wherein the axial barb has an inclined surface which faces outwardly.
15. The RF connector of claim 13, wherein the inclined surface of said axial barb is inclined with respect to said step surface.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A communication interface comprising:
a USB port configured to be able to receive a data bus of an electronic device to be connected to the communication interface, the USB port including:
a power Vbus line;
a data transmission mode status line;
a ground line; and
a first and second data line for receiving data from an electronic device connected to the interface via the USB port,

wherein the first and second data lines form part of a common transmission path for enabling an electronic device connected to the USB port to be in communication with a further electronic device using either:
a first data transmission mode, comprising single-ended asynchronous data transmission; or
a second data transmission mode, comprising USB differential transmission of data;
first communication circuitry configured to allow for communication between a connected electronic device and a further electronic device using said first data transmission mode;
second communication circuitry configured to allow for communication between a connected electronic device and a further electronic device using said second data transmission mode;
first detection circuitry configured to detect the data transmission mode status of a connected electronic device using the data transmission mode status line of the USB port;
second detection circuitry configured to detect the power activity of a connected electronic device using the power Vbus line of the USB port; and
switching circuitry configured to selectively connect the first or second communication circuitry to the common transmission path to allow for data transmission between a connected electronic device and a further electronic device in either the first or second data transmission mode using the same interface based on the first and second detection circuitries,
wherein the switching circuitry is configured to selectively connect said first or second communication circuitry by:
identifying the data transmission mode status of the connected electronic device using the first detection circuitry;
identifying the power activity of the connected electronic device using the second detection circuitry;
verifying the data transmission mode of the connected device using the combined findings of the first and second detection circuitries; and

connecting the first or second communication circuitry, corresponding to the verified data transmission mode, to the first and second data lines of the common transmission path to allow for data transmission between the connected electronic device and a further electronic device in said verified data transmission mode using the same interface.
2. An interface according to claim 1, wherein said first and second data lines are configured to be used to transmit and receive data using said second mode of data transmission.
3. An interface according to claim 1, wherein said first data line is configured to be used to receive data and said second data line is configured to be used to transmit data using said first mode of data transmission.
4. An interface according to claim 1, wherein said first data line is configured to be used to receive and transmit data using said first mode of data transmission.
5. An interface according to claim 1, wherein said second data line is configured to be used to receive and transmit data using said first mode of data transmission.
6. An interface according to claim 1, wherein said first and second data lines are configured to be connectable to a data bus.
7. An interface according to claim 1, wherein the USB port conforms to a B-type USB specification.
8. An interface according to claim 1, wherein the first mode of data transmission uses a first set of voltage levels.
9. An interface according to claim 8, wherein the second mode of data transmission uses a second, different set of voltage levels.
10. An interface according to claim 9, wherein said switching circuitry comprises circuitry for shifting the first and second set of voltage levels to another set of voltage level.
11. An interface according to claim 1, wherein said first communication circuitry is configured for full-duplex communication.
12. An interface according to claim 1, wherein said first communication circuitry is configured for half-duplex communication.
13. An electronic device including an interface according to claim 1.
14. An interface according to claim 1, wherein the first and second lines are configured to be used for data transmission tofrom two different devices.
15. An interface according to claim 1 wherein the interface is configured such that one of said first and second data lines is used only to receive data and the other of said first and second data lines is used only to transmit data using said first data transmission mode, and wherein each of said first and second data lines is used both to transmit and receive data using said second data transmission mode.
16. An interface according to claim 1, wherein the first data line is configured to be used for half-duplex data transmission between the electronic device and a first connected device and the second data line is configured to be used for half-duplex data transmission between the electronic device and a second, different connected device.
17. An interface according to claim 1, wherein the USB port is configured to be used without the need for an adapter.
18. An ASIC comprising an interface according to claim 1.
19. A method comprising:
selectively connecting first or second communication circuitry of a communication interface to a common transmission path to enable an electronic device connected to a USB ort of the communication interface to be in communication with a further electronic device, the communication to be enabled using either:
a first data transmission mode, comprising single-ended asynchronous data transmission, the first communication circuitry being configured to allow for communication between a connected electronic device and a further electronic device using said first data transmission mode; or
a second data transmission mode, comprising USB differential transmission of data, the second communication circuitry being configured to allow for communication between a connected electronic device and a further electronic device using said second data transmission mode, wherein the USB port is configured to be able to receive a data bus of an electronic device to be connected to the communication interface, the USB port including:
a power Vbus line;
a data transmission mode status line;
a ground line; and
a first and second data line for receiving data from an electronic device connected to interface via the USB port,
wherein the first and second data lines form part of the common transmission path to enable communication between the devices across the interface,
wherein selectively connecting the first or second communication circuitry comprises:
identifying the data transmission mode status of an electronic device connected to the interface using the data transmission mode status line of the USB port;
identifying the power activity of the connected electronic device using the second detection circuitry using the power Vbus line of the USB port;
verifying the data transmission mode of the connected device using the combined findings of the identifying steps; and

performing switching to selectively connect the first or second communication circuitry, corresponding to the verified data transmission mode, to the first and second data lines of the common transmission path to allow for data transmission between the connected electronic device and a further electronic device in said verified data transmission mode using the same interface.