All The Claims

What is claimed is:

1. An implantable body fluid shunt device for providing fluid communication between body vessels of a patient, said device comprising:
a generally elongated shunt body having proximal and distal ends, said shunt body being formed of a rigid, biocompatible material;
said shunt body having:
a first proximal aperture and at least one second aperture longitudinally spaced along said shunt body from said first aperture; and
a diversion tube having a predetermined shape providing fluid communication between said first aperture and said at least one second aperture;

wherein, in use, said device is implanted in a patient such that said first aperture is disposed within a first vessel, and said at least one second aperture is disposed in a second vessel.
2. The implantable shunt device of claim 1, wherein said shunt body further comprises a spike portion at a distal end thereof.
3. The implantable shunt device of claim 1, wherein said shunt body further comprises expansible retention members at a distal end thereof.
4. The implantable shunt device of claim 1, wherein said device provides transmyocardial blood perfusion, and wherein said second aperture is adjacent said distal end of said shunt body and in use is disposed within the left ventricle of a patient.
5. The implantable shunt device of claim 4, wherein the first aperture is adjacent said proximal end of said shunt body and in use is disposed within a coronary artery of a patient.
6. The implantable shunt device of claim 2, wherein the second aperture in use is situated within the coronary artery of a patient and wherein said spike portion is disposed within the myocardium.
7. The implantable shunt device of claim 6, wherein the first aperture is adjacent said proximal end of said shunt body, wherein said first aperture is disposed within a venous or arterial graft.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. An image detection apparatus comprising:
a plurality of image layers comprising a first image layer and a plurality of secondary image layers, each of the plurality of image layers comprising:
a plurality of radiation sensitive units configured to absorb radiation from a radiation source, the radiation comprising radiation incident to the plurality of layers of radiation sensitive units;
a plurality of converters coupled to the plurality of radiation sensitive units, the plurality of converters being operable to convert the radiation absorbed from the radiation source into a plurality of particles;
a plurality of sensors coupled to the plurality of radiation sensitive units and coupled to the plurality of converters, the plurality of sensors being sensitized to the plurality of particles and configured to generate charged particles from the plurality of particles; and
an electronic circuit for processing the charged particles from the plurality of sensors to generate a digital image;
wherein the radiation from the radiation source has a corresponding energy level,
wherein the first image layer is sensitive to radiation at a first energy level, and the plurality of secondary image layers are sensitive to radiation at a second energy level different from the first energy level,
further wherein the plurality of converters in each of the plurality of secondary image layers has a corresponding pixel resolution, and the pixel resolution of each of the plurality of converters is different from the pixel resolution of the plurality of converters in other image layers of the plurality of secondary image layers.
2. The apparatus of claim 1 wherein the plurality of image layers is arranged in a two-dimensional array.
3. The apparatus of claim 1 wherein the plurality of image layers is vertically stacked.
4. The apparatus of claim 1 wherein the radiation comprises visible light.
5. The apparatus of claim 1 wherein the radiation comprises X-ray radiation.
6. The apparatus of claim 1 wherein the charged particles comprise electron hole pairs.
7. The apparatus of claim 1 wherein at least one of the plurality of sensors comprises a photo-diode array.
8. The apparatus of claim 1 wherein at least one of the plurality of sensors comprises an amorphous silicon (a-Si) photo diode array.
9. The apparatus of claim 1 wherein at least one of the plurality of sensors comprises an amorphous silicon (a-Si) transistor array.
10. The apparatus of claim 1, wherein at least one of the plurality of sensors comprises an organic semiconductor photo diode array.
11. The apparatus of claim 1, wherein at least one of the plurality of sensors comprises an organic semiconductor transistor array.
12. The apparatus of claim 1 wherein at least one of the plurality of converters comprises a layer of scintillators.
13. The apparatus of claim 12 wherein the plurality of converters for a top layer of the plurality of image layers comprises a layer of scintillators.
14. The apparatus of claim 1 wherein at least one of the plurality of sensors comprises an amorphous silicon (a-Si) thin film transistor array.
15. The apparatus of claim 1 wherein a sensor of the plurality of sensors is sensitive to light.
16. The apparatus of claim 1 wherein a converter of the plurality of converters is sensitive to light.
17. The apparatus of claim 1 further comprising a plurality of anti-scatter grids.
18. The apparatus of claim 1 wherein the radiation from the radiation source is comprised of a plurality of particles, the plurality of particles consisting of at least one of the group of particles which includes: electrons, protons, ions and photons.
19. The apparatus of claim 1, wherein the electronic circuit comprises an application specific integrated circuit (ASIC).
20. A method for generating an image in a digital imaging system comprising:
receiving an incident radiation beam in a plurality of image layers comprising a first image layer and a plurality of secondary image layers, each image layer being implemented to include a plurality of radiation sensitive units, a plurality of converters, and a plurality of sensors,
converting, in a plurality of converters comprised in the first image layer, a first portion of the incident radiation beam into a first plurality of particles, the remaining portion of the incident radiation beam comprising pass through radiation;
generating, in a plurality of sensors comprised in the first image layer, a plurality of charged particles from the first plurality of particles;
converting, in the plurality of secondary image layers, the pass through radiation into a second plurality of particles;
generating a second plurality of charged particles from the second plurality of particles in the plurality of sensors in the plurality of secondary image layers; and
processing the first and second pluralities of charged particles to generate a digital image in an electronic circuit,
wherein the first image layer is sensitive to radiation at a first energy level, and the plurality of secondary image layers are sensitive to radiation at a second energy level different from the first energy level,
wherein the plurality of converters in each image layer of the plurality of secondary image layers has a resolution that is different than that of plurality of converters in other image layers of the plurality of secondary mage layers.
21. The method of claim 20 wherein the incident radiation comprises X-rays.
22. The method of claim 20 further comprising reducing object scatter by implementing a plurality of anti-scatter grids.
23. The method of claim 20 wherein the incident radiation comprises visible light.
24. The method of claim 20 wherein the first and second pluralities of charged particles comprise a plurality of electron hole pairs.
25. The method of claim 20 wherein the incident radiation beam is comprised of a plurality of particles, the plurality of particles being comprised of at least one of the group of particles which includes: electrons, protons, ions and photons
26. The method of claim 20 wherein at least one of the plurality of sensors comprises a photo-diode array.
27. The method of claim 26, wherein the photo-diode array is an amorphous silicon (a-Si) photo diode array.
28. The method of claim 20 wherein the at least one of the plurality of converters comprises a plurality of scintillators
29. The method of claim 20 wherein at least one of the plurality of sensors comprises an amorphous silicon (a-Si) thin film transistor array.
30. The method of claim 20, wherein at least one of the plurality of sensors comprises an organic semiconductor photo diode array.
31. The method of claim 20, wherein at least one of the plurality of sensors comprises an organic semiconductor transistor array.
32. The method of claim 20 wherein the electronic circuit comprises an application-specific integrated circuit (ASIC).
33. A method for generating an image from a radiation beam, the method comprising:
receiving a plurality of radiation particles in an imaging device;
converting the plurality of radiation particles into a plurality of photons;
converting the plurality of photons into a plurality of electron hole-pairs;
transferring the plurality of electron hole-pairs to a readout circuit;
generating an output in the readout circuit from the plurality of electron hole-pairs; and
processing the output from the readout circuit to generate a data image,
wherein the imaging device comprises a first paired layer and a plurality of secondary paired layers, each pair of layers comprising a converting layer and a sensor layer corresponding to the converting layer, and radiation sensitive units,
wherein the radiation sensitive units comprising the first paired layer are sensitive to an energy level different than the radiation sensitive units comprising the plurality of secondary paired layers,
further wherein the converting layers comprising the plurality of secondary paired layers have varying resolutions.
34. (canceled)
35. The method of claim 44 33, wherein a converting layer comprises a scintillator layer.
36. The method of claim 35, wherein the converting the plurality of radiation particles into a plurality of photons is performed in the scintillator layer.
37. The method of claim 34, wherein at least one layer of the first paired layer and the plurality of secondary paired layers comprises an amorphous silicon (a-Si) photo diode array.
38. The method of claim 37, wherein the converting the plurality of photons into a plurality of electron hole-pairs is performed by the amorphous silicon (a-Si) photo diode array.
39. The method of claim 34, wherein a at least one paired layer of the plurality of secondary paired layers comprises an amorphous silicon (a-Si) thin film transistor array.
40. The method of claim 39, wherein the transferring the plurality of electron hole-pairs to a readout circuit is performed through the amorphous silicon (a-Si) thin film transistor array.
41. The method of claim 34, wherein at least one layer of the first paired layer and the plurality of secondary paired layers comprises an organic semiconductor transistor array.
42. The method of claim 41, wherein the converting of the plurality of photons into a plurality of electron hole-pairs is performed by the organic semiconductor photo diode array.
43. the method of claim 34, wherein a at least one layer of the first paired layer and the plurality of paired layers comprises an organic semiconductor transistor array.
44. The method of claim 43, wherein the transferring of the plurality of electron hole-pairs to a readout circuit is performed through the organic semiconductor transistor array.
45. The method of claim 34, wherein the readout circuit comprises an application-specific integrated circuit (ASIC).
46. The image detection apparatus of claim 1, further comprising a plurality of sub-imagers, each of the plurality of sub-imagers being coupled and corresponding to one of:
the first image layer and a secondary image layer of the plurality of image layers, and configured to generate sub-images corresponding to the radiation received in the corresponding image layer.
47. The image detection apparatus of claim 46, wherein the electronic circuit re-samples and interpolates the sub-images from the plurality of sub-imagers to generate the digital image.
48. The image detection apparatus of claim 47, wherein the electronic circuit selectively collects sub-images from the plurality of sub-imagers to re-sample and interpolate.
49. The method of claim 20, wherein processing the first and second pluralities of charged particles to generate a digital image in an electronic circuit comprises re-sampling and interpolating a plurality of sub-images, the plurality of sub-images being generated by sub-imagers coupled to each of the plurality of image layers.
50. The method of claim 49, wherein the plurality of sub-images are selectively collected by the electronic circuit from the plurality of sub-imagers.
51. The method of claim 33, wherein generating an output in the readout circuit from the plurality of electron hole-pairs comprises generating a plurality of sub-images, the plurality of sub-images being generated by sub-imagers coupled to each of the plurality of image layers.
52. The method of claim 51, wherein processing the output from the readout circuit to generate a data image comprises selectively collecting the sub-images from the plurality of sub-imagers.
53. The method of claim 51, wherein processing the output from the readout circuit to generate a data image comprises re-sampling and interpolating a plurality of sub-images.

1. A system comprising:
an interconnect bus having a plurality of signal traces;
a first integrated circuit having:
a transmitter controller, and
a transmitter interface circuit coupled to the transmitter controller to receive first data synchronously with a system clock signal, to generate a bus clock signal, to convert the first data into second data synchronous with transitions of the bus clock signal and to output the second data to the interconnect bus; and

a second integrated circuit having:
a receiver controller configured to generate at least one control signal indicative of a bit-lane correspondence between the first integrated circuit and the second integrated circuit, and
a receiver interface circuit coupled to the interconnect bus to retrieve the second data and coupled to the receiver controller to receive the at least one control signal, wherein the receiver interface circuit restores the first data according to the at least one control signal.
2. The system of claim 1, wherein the transmitter controller generates predetermined test data and provides a pseudo-random sequence to the transmitter interface circuit for transmission to the second integrated circuit.
3. The system of claim 2, wherein the receiver controller generates like predetermined test data, compares the like predetermined test data to data received by the receiver interface circuit, and determines a transmission error rate of the interconnect bus.
4. The system of claim 1, wherein the receiver controller comprises a circuit to deduce a bit-lane correspondence between the outputs of the transmitter interface circuit and inputs of the receiver interface circuit.
5. The system of claim 4, wherein the receiver controller comprises a circuit to deduce a phase offset between a rising transition of the bus clock signal and a rising transition of the system clock signal.
6. The system of claim 5, wherein the receiver controller generates the control signal according to the bit-lane correspondence and the phase offset.
7. The system of claim 1, wherein the receiver controller compares at least one portion of the second data to a plurality of predetermined patterns each corresponding to one of a plurality of bit-lane correspondences.
8. The system of claim 1, wherein the receiver controller compares at least one portion of the second data to at least two predetermined patterns corresponding to at least two phase offsets between a rising transition of the bus clock signal and a rising transition of the system clock signal.
9. A system comprising:
an interconnect bus having a plurality of signal traces;
a first integrated circuit having:
a transmitter controller,
a transmitter interface circuit coupled to the transmitter controller to receive first data synchronously with a system clock signal, to generate a bus clock signal, to convert the first data into second data synchronous with transitions of the bus clock signal and to output the second data to the interconnect bus; and

a second integrated circuit having:
a receiver controller configured to generate control signals indicative of a phase offset between a rising transition of the bus clock signal and a rising transition of the system clock signal from the second data, and
a receiver interface circuit coupled to the interconnect bus to retrieve the second data and configured to restore the first data according to the control signals.
10. The system of claim 9, wherein the transmitter controller generates predetermined test data and provides a pseudo-random sequence to the transmitter interface circuit for transmission to the second integrated circuit.
11. The system of claim 10, wherein the receiver controller generates like predetermined test data, compares the like predetermined test data to data received by the receiver interface circuit, and determines a transmission error rate of the interconnect bus.
12. The system of claim 9, wherein the receiver controller comprises a circuit to deduce a bit-lane correspondence between the outputs of the transmitter interface circuit and the inputs of the receiver interface circuit.
13. The system of claim 12, wherein the receiver controller generates the control signals consistent with the bit-lane correspondence and the phase offset.
14. The system of claim 9, wherein the receiver controller compares at least one portion of the second data to a plurality of predetermined patterns each corresponding to one of a plurality of bit-lane correspondences.
15. The system of claim 9, wherein the receiver controller compares at least one portion of the second data to at least two predetermined patterns corresponding to at least two phase offsets between a rising transition of the bus clock signal and a rising transition of the system clock signal.
16. A method for communicating data from a first integrated circuit to a second integrated circuit across an interconnect bus within a system, the method comprising:
upon receiving a reset signal, the first integrated circuit and the second integrated circuit performing a set up process that comprises deducing a bit-lane correspondence of the interconnect bus;
transmitting data from the first integrated circuit to the second integrated across the interconnect bus; and
reconstructing the data at the second integrated circuit according to the deduced bit-lane correspondence.
17. The method of claim 16, wherein the deducing step comprises:
generating predetermined test data at the first integrated circuit;
transmitting the predetermined test data to the second integrated circuit; and
at the second integrated circuit, comparing at least a portion of received data to a plurality of predetermined patterns each corresponding to one of a plurality of bit-lane correspondences of the interconnect bus.
18. The method of claim 16, wherein the setup process comprises deducing a phase offset between a rising transition of a clock signal of the interconnect bus and a rising transition of a system clock of the first integrated circuit.
19. The method of claim 16, wherein the set up process comprises:
generating predetermined test data at the first integrated circuit;
transmitting the predetermined test data to the second integrated circuit;
at the second integrated circuit, comparing at least a portion of received data to at least two predetermined patterns each corresponding to one of at least two phase offsets between a rising transition of the clock signal of the interconnect bus and a rising transition of a system clock of the first integrated circuit.
20. The method of claim 16, wherein the set up process comprises:
generating predetermined test data at the first integrated circuit;
transmitting the predetermined test data to the second integrated circuit;
at the second integrated circuit, generating like predetermined test data and comparing data received by the second integrated circuit to the like predetermined test data to determine a transmission error rate of the interconnect bus.
21. A method for communicating data from a first integrated circuit to a second integrated circuit across an interconnect bus within a system, the method comprising:
upon receiving a reset signal, the first integrated circuit and the second integrated circuit performing a set up process that comprises deducing a phase offset between a rising transition of a clock signal of the interconnect bus and a rising transition of a system clock of the first integrated circuit;
transmitting data from the first integrated circuit to the second integrated across the interconnect bus; and
reconstructing the data at the second integrated circuit according to the deduced phase offset.
22. The method of claim 21, wherein the deducing step comprises:
generating predetermined test data at the first integrated circuit;
transmitting the predetermined test data to the second integrated circuit;
at the second integrated circuit, comparing at least a portion of received data to at least two predetermined patterns each corresponding to one of at least two phase offsets between a rising transition of the clock signal of the interconnect bus and a rising transition of a system clock of the first integrated circuit.
23. The method of claim 21, wherein the set up process comprises:
generating predetermined test data at the first integrated circuit;
transmitting the predetermined test data to the second integrated circuit;
at the second integrated circuit, generating like predetermined test data and comparing data received by the second integrated circuit to the like predetermined test data to determine a transmission error rate of the interconnect bus.
24. An integrated circuit, comprising:
means for coupling to another integrated circuit via an interconnect bus;
means for deducing a bit-lane correspondence of the interconnect bus;
means for receiving data from the other integrated circuit via the interconnect bus; and
means for reconstructing data transmitted by the other integrated circuit according to the deduced bit-lane correspondence.
25. The integrated circuit of claim 24, wherein the means for deducing comprises:
means for comparing at least a portion of the received data to a plurality of predetermined patterns each corresponding to one of a plurality of bit-lane correspondences of the interconnect bus.
26. The integrated circuit of claim 24, comprising
second means for deducing a phase offset between a rising transition of a clock signal of the interconnect bus and a rising transition of a system clock of the first integrated circuit.
27. The integrated circuit of claim 26, wherein the second means for deducing comprises:
means for comparing at least a portion of the received data to at least two predetermined patterns each corresponding to one of at least two phase offsets between a rising transition of the clock signal of the interconnect bus and a rising transition of a system clock of the first integrated circuit.
28. The integrated circuit of claim 24, comprising:
means for generating predetermined test data; and
means for comparing the received data to the predetermined test data to determine a transmission error rate of the interconnect bus.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A non-transitory computer readable medium, comprising:
a computer program code including executable instructions, which, when executed by a terminal device, cause the terminal device to perform a method for cell reselection as follows:
receiving, when in a cell of a Long Term Evolution (LTE) system, a message including a dedicated priority list from the LTE system; and
performing, when camping on a cell of a non-LTE system, the cell reselection in accordance with the received dedicated priority list before a valid time of the dedicated priority list expires.
2. The non-transitory computer readable medium of claim 1, wherein the message received from the LTE system includes a dedicated signaling, the dedicated priority list being included in the dedicated signaling.
3. The non-transitory computer readable medium of claim 1, wherein the dedicated signaling including the dedicated priority list includes a Radio Resource Control (RRC) Connection Release message.
4. The non-transitory computer readable medium of claim 1, wherein the method further comprises: performing, when camping on the cell of the non-LTE system, the cell reselection in accordance with a public priority list after the valid time of the dedicated priority list expires.
5. The non-transitory computer readable medium of claim 4, wherein the public priority list is obtained from the LTE system or the non-LTE system.
6. The non-transitory computer readable medium of claim 5, wherein the public priority list is obtained through system broadcast information.
7. The non-transitory computer readable medium of claim 1, wherein the method further comprises: deleting the dedicated priority list when the valid time of the dedicated priority list expires.
8. The non-transitory computer readable medium of claim 1, wherein the valid time of the dedicated priority list is controlled through a timer.
9. The non-transitory computer readable medium of claim 1, wherein the valid time of the dedicated priority list is obtained through a dedicated signaling from the LTE system.
10. The non-transitory computer readable medium of claim 9, wherein the dedicated signaling includes a Radio Resource Control (RRC) Connection Release message, the valid time being included in the RRC Connection Release message.
11. The non-transitory computer readable medium of claim 1, wherein the valid time is included in a dedicated signaling.
12. The non-transitory computer readable medium of claim 1, wherein the dedicated priority list comprises priority information of different frequencies or priority information of different radio access technologies (RATs).
13. The non-transitory computer readable medium of claim 12, wherein the priority information comprises priority information of frequencies of the different RATs.
14. The non-transitory computer readable medium of claim 1, wherein the dedicated priority list comprises frequency priority information of the LTE system and the non-LTE system.
15. An apparatus comprising:
a non-transitory storage medium including executable instructions; and
a processor;
wherein the executable instructions, when executed by the processor, cause the apparatus to:
receive, when in a cell of a Long Term Evolution (LTE) system, a message including a dedicated priority list from the LTE system; and
perform, when camping on a cell of a non-LTE system, cell reselection in accordance with the received dedicated priority list before a valid time of the dedicated priority list expires.
16. The apparatus of claim 15, wherein the message received from the LTE system includes a dedicated signaling, the dedicated priority list being included in the dedicated signaling.
17. The apparatus of claim 15, wherein the dedicated signaling containing the dedicated priority list includes a Radio Resource Control (RRC) Connection Release message.
18. The apparatus of claim 15, wherein the valid time of the dedicated priority list is controlled through a timer.
19. The apparatus of claim 15, wherein, in a situation where the apparatus camps on the cell of the non-LTE system and after the valid time of the dedicated priority list expires, the executable instructions, when executed by the processor, cause the processor to perform the cell reselection in accordance with a public priority list obtained from the LTE network or the non-LTE network.
20. The apparatus of claim 15, wherein the dedicated priority list comprises priority information of different frequencies or of different radio access technologies (RATs).