All The Claims

1. A semiconductor device comprising:
a semiconductor base of a first conductivity type;
a first conductive coupling region of the first conductivity type provided on the semiconductor base;
a second conductive coupling region of the first conductivity type provided on the semiconductor base so as to surround the first conductive coupling region;
a first electrode group having a plurality of electrodes that is provided on the first conductive coupling region; and
a second electrode group having a plurality of electrodes that is provided on the second conductive coupling region.
2. The semiconductor device according to claim 1, wherein the semiconductor base is one well region provided on a semiconductor substrate, and the semiconductor base between the first conductive coupling region and the second conductive coupling region functions as a resistor.
3. The semiconductor device according to claim 1, wherein the semiconductor base is one well region provided on a semiconductor substrate, and has a pattern that is at least fourfold symmetric about a center of the first conductive coupling region, the semiconductor base between the first conductive coupling region and the second conductive coupling region functioning as a resistor.
4. The semiconductor device according to claim 1, wherein a peripheral electrode of the first electrode group in a predetermined number is arranged closest to an edge of the first conductive coupling region in each of four regions, and an electrode of the second electrode group in a predetermined number is arranged in each of four regions so as to face the peripheral electrode of the first electrode group.
5. The semiconductor device according to claim 1, wherein the first electrode group is distributed in a whole region from a center of the first conductive coupling region to a predetermined region, a peripheral electrode of the first electrode group in a predetermined number being arranged closest to an edge of the first conductive coupling region in each of four regions, and an electrode of the second electrode group in a predetermined number being arranged in each of four regions so as to face at least the peripheral electrode of the first electrode group in a predetermined number.
6. The semiconductor device according to claim 1, wherein the first conductive coupling region has a planar shape obtained by removing four corner parts from a quadrangle and having at least four sides, the first electrode group being prepared so that an electrode in a predetermined number is arranged along the four sides, and an electrode of the second electrode group in a predetermined number being arranged so as to face at least the electrode of the first electrode group in a predetermined number.
7. The semiconductor device according to claim 1, wherein a distance between the first conductive coupling region and the second conductive coupling region in a region in which the first electrode group faces the second electrode group is smaller than a distance between the first conductive coupling region and the second conductive coupling region in other regions.
8. A semiconductor device comprising:
a semiconductor base of a first conductivity type;
a first insulating film provided on the semiconductor base;
a first conductive coupling region of the first conductivity type in a center part and a second conductive coupling region of the first conductivity type surrounding the first conductive coupling region, the first and second conductive coupling regions being isolated from each other by the first insulating film;
a second insulating film provided on the first conductive coupling region and the second conductive coupling region;
a first electrode group having a plurality of electrodes that is provided on the first conductive coupling region via a plurality of openings in the second insulating film;
a second electrode group having a plurality of electrodes that is provided on the second conductive coupling region via a plurality of openings in the second insulating film;
a first wiring pattern coupled to a plurality of predetermined electrodes of the first electrode group; and
a second wiring pattern coupled to a plurality of predetermined electrodes of the second electrode group.
9. The semiconductor device according to claim 8, wherein a silicide metal layer is formed in the first conductive coupling region and the second conductive coupling region except for a predetermined region adjacent to the first insulating film.
10. The semiconductor device according to claim 8, wherein the semiconductor base is one well region provided on a semiconductor substrate, and the semiconductor base between the first conductive coupling region and the second conductive coupling region functions as a resistor.
11. The semiconductor device according to claim 8, wherein the semiconductor base is one well region provided on a semiconductor substrate, and has a pattern that is at least fourfold symmetric about a center of the first conductive coupling region, the semiconductor base between the first conductive coupling region and the second conductive coupling region functioning as a resistor.
12. The semiconductor device according to claim 8, wherein a peripheral electrode of the first electrode group in a predetermined number is arranged closest to an edge of the first conductive coupling region in each of four regions, and an electrode of the second electrode group in a predetermined number is arranged in each of four regions so as to face the peripheral electrode of the first electrode group.
13. The semiconductor device according to claim 8, wherein the first electrode group is distributed in a whole region from a center of the first conductive coupling region to a predetermined region, a peripheral electrode of the first electrode group in a predetermined number being arranged closest to an edge of the first conductive coupling region in each of four regions, and an electrode of the second electrode group in a predetermined number being arranged in each of four regions so as to face at least the peripheral electrode of the first electrode group in a predetermined number.
14. The semiconductor device according to claim 8, wherein the first conductive coupling region has a planar shape obtained by removing four corner parts from a quadrangle and having at least four sides, the first electrode group being prepared so that an electrode in a predetermined number is arranged along the four sides, and an electrode of the second electrode group in a predetermined number being arranged so as to face at least the electrode of the first electrode group in a predetermined number.
15. The semiconductor device according to claim 8, wherein a distance between the first conductive coupling region and the second conductive coupling region in a region in which the first electrode group faces the second electrode group is smaller than a distance between the first conductive coupling region and the second conductive coupling region in other regions.
16. A method for manufacturing a semiconductor device, comprising:
forming an annular first insulating film on a semiconductor base;
forming, with using the first insulating film as a mask, a first conductive coupling region of a first conductivity type in a center part of the semiconductor base and a second conductive coupling region of the first conductivity type in a periphery of the first conductive coupling region;
forming a second insulating film on the first conductive coupling region and the second conductive coupling region; and
forming a first electrode group and a second electrode group that have a plurality of electrodes on the first conductive coupling region and the second conductive coupling region, respectively, via a plurality of openings in the second insulating film.
17. The method for manufacturing a semiconductor device according to claim 16, further comprising forming a first wiring pattern coupled to a plurality of predetermined electrodes of the first electrode group and a second wiring pattern coupled to a plurality of predetermined electrodes of the second electrode group.
18. The method for manufacturing a semiconductor device according to claim 16, wherein the semiconductor base is one well region provided on a semiconductor substrate, and forms a resistor, between the first conductive coupling region and the second conductive coupling region, that is at least fourfold symmetric about a center of the first conductive coupling region.
19. The method for manufacturing a semiconductor device according to claim 16, wherein an inner circumference of the first insulating film has an octagon shape that has at least longitudinal four sides, and an outer circumference forms regions of four sides facing the four sides, a width between the inner and outer circumferences in the regions of four sides being smaller than a width between the inner and outer circumferences in four corner regions.
20. The method for manufacturing a semiconductor device according to claim 16, further comprising, prior to the step of forming the second insulating film:
forming a protective layer for preventing silicidation that covers a predetermined region, of the first conductive coupling region and the second conductive coupling region, adjacent to at least the first insulating film; and
forming a silicide metal layer on the first conductive coupling region and the second conductive coupling region except for the predetermined region.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A hair removal device comprising: a handle having a first interior wall and a second opposing interior wall that has a tapered surface; a cover removably mounted to the handle; and a dispensing unit removably mounted within the handle, the dispensing unit comprising a reservoir having a second connector, the reservoir containing a liquid, and a pump having a first connector, wherein the first connector and the second connector are spaced apart in a first position and in contact in a second position, wherein mounting the cover to the handle forces the dispensing unit into the handle while urging the second connector to slide along the tapered surface from the first position to the second position wherein the pump is not in liquid communication with the reservoir in the first position and the pump is in liquid communication with the reservoir in the second position.
2. The hair removal device of claim 1 wherein the first and second interior walls are segmented.
3. The hair removal device of claim 1 wherein the reservoir is a laminated foil sachet that is heat sealed around one of the connectors.
4. The hair removal device of claim 1 further comprising a reservoir conduit slidably engaged with one of the connectors, the reservoir conduit having one or more apertures.
5. The hair removal device of claim 1 further comprising a reservoir conduit positioned within one of the connectors, the reservoir conduit having one or more apertures.
6. The hair removal device according to any one of claims 1 to 5 wherein the dispensing unit becomes locked once moved to the second position.
7. The hair removal device according to any one of claims 1 to 5 wherein the first and second connectors each have a shoulder and the shoulders are spaced apart in the first position and the shoulders are in contact in the second position.
8. The hair removal device of claim of claim 4 or 5 wherein the one or more apertures of the reservoir conduit are blocked by one of the connectors in the first position preventing liquid communication between the reservoir and the pump.
9. The hair removal device of claim 4 or 5 wherein the one or more apertures of the reservoir conduit are liquid communication with the reservoir in the second position allowing liquid communication between the reservoir and the pump.
10. The hair removal device according to any one of claims 1 to 5 wherein the dispensing unit and or the handle provide an audible feedback when the dispensing unit is placed in the second position.

1. A computer-accessible storage medium having program instructions stored therein that, in response to execution by a computer system, cause the computer system to perform operations including:
generating a statistical distribution of a first design parameter of a memory circuit;
generating a statistical distribution of a second design parameter of the memory circuit;
determining a first probability density function of the statistical distribution of the first design parameter;
determining a second probability density function of the statistical distribution of the second design parameter;
combining the first probability density function and the second probability density function to form a composite probability density function;
calculating a probability, dependent upon the composite probability density function, of a performance parameter of the memory circuit achieving a pre-determined performance value; and
optimizing a third design parameter of the memory circuit such that the probability is equal to a pre-determined goal.
2. The computer-accessible storage medium of claim 1, wherein generating the statistical distribution of the first design parameter or the second design parameter comprises running a Monte Carlo circuit simulation.
3. The computer-accessible storage medium of claim 1, wherein determining the first probability density function or the second probability density function comprises performing a curve fit.
4. The computer-accessible storage medium of claim 1, wherein combining the first probability density function and the second probability density function comprises multiplying the first probability density function and the second probability density function.
5. The computer-accessible storage medium of claim 1, wherein calculating the probability comprises numerically integrating the composite probability density function.
6. A method comprising:
performing by one or more computers:
determining a first probability density function corresponding to a statistical variation of a first design parameter of a circuit;
determining a second probability density function corresponding to a statistical variation of a second design parameter of the circuit;
combining the first probability density function and the second probability density function into a composite probability density function; and
optimizing a third design parameter of the circuit dependent upon the composite probability density function.
7. The method of claim 6, wherein the circuit comprises a memory circuit.
8. The method of claim 7, wherein the first design parameter comprises a bit line differential voltage, wherein the second design parameter comprises a minimum sense amplifier differential voltage, and wherein the third design parameter comprises a bit line development time.
9. The method of claim 7, wherein the first probability density function corresponds to a normally distributed probability density function.
10. The method of claim 7, wherein the second probability density function corresponds to an extreme value probability density function.
11. A system comprising:
one or more memories that, during operation, store instructions, and
one or more processors that, during operation, receive instructions from the one or more memories and execute the instructions to cause the system to perform operations comprising:
generating a first statistical distribution of the operation of a first part of a circuit;
generating a second statistical distribution of the operation of a second part of the circuit; and
optimizing a third part of the circuit dependent upon the first statistical distribution and the second statistical distribution.
12. The system of claim 11, wherein the first part of the circuit comprises a bit line of a memory circuit, wherein the second part of the circuit comprises a sense amplifier of the memory circuit, and wherein the third part of the circuit comprises a timing and control unit of the memory circuit.
13. The system of claim 12, wherein optimizing the third part of the circuit comprises one or more of: generating a first probability density function dependent upon the first statistical distribution, or generating a second probability density function dependent upon the second statistical distribution.
14. The system of claim 13, wherein optimizing the third part of the circuit further comprises multiplying the first probability density function by the second probability density function.
15. The system of claim 14, wherein optimizing the third part of the circuit further comprises modifying a development time dependent upon the product of the first probability density function and the second probability density function.
16. A computer-accessible storage medium having program instructions stored therein that, in response to execution by a computer system, cause the computer system to perform operations including:
generating a distribution of a minimum sense amplifier input signal voltage of a memory circuit;
generating a distribution of a bit line output signal voltage of the memory circuit;
converting the distribution of the minimum sense amplifier input signal voltage to a sense amplifier probability density function;
converting the distribution of the bit line output signal voltage to a bit line probability density function;
combining the sense amplifier probability density function and the bit line probability density function into a composite probability density function;
calculating, dependent upon the composite probability density function, a probability of a misread; and
optimizing a bit line output signal voltage development time such that the probability of a misread achieves a pre-determined probability goal.
17. The computer-accessible storage medium of claim 16, wherein calculating the probability of a misread comprises calculating a probability of the bit line output signal voltage achieving an output voltage.
18. The computer-accessible storage medium of claim 17, wherein calculating the probability of a misread further comprises, calculating a probability of the minimum sense amplifier input voltage matching the output voltage.
19. The computer-accessible storage medium of claim 18, wherein calculating the probability of a misread further comprises multiplying the probability of the bit line output signal voltage achieving an output voltage by the probability of the minimum sense amplifier input voltage matching the output voltage.
20. The computer-accessible storage medium of claim 19, wherein the probability of a misread is dependent upon a number of sense amplifiers included in the memory circuit.
21. A method comprising:
performing by one or more computers:
simulating a sense amplifier of a memory circuit to generate a statistical data of the minimum input voltage of the sense amplifier;
simulating a data storage cell of the memory circuit to generate a statistical data of the output voltage of the data storage cell;
determining a sense amplifier probability density function based in part upon the statistical data of the minimum input voltage of the sense amplifier;
determining a data storage cell probability density function based in part upon the statistical data of the output voltage of the data storage cell; and
calculating a probability of a read failure based in part upon the sense amplifier probability density function and the data storage cell probability density function.
22. The method of claim 21, wherein determining the sense amplifier probability density function comprises curve fitting the statistical data of the minimum input voltage of the sense amplifier.
23. The method of claim 22, wherein the sense amplifier probability density function is dependent upon one or more of a number of sense amplifiers or a number of redundant sense amplifiers.
24. The method of claim 21, wherein determining the data storage cell probability density function comprises curve fitting the statistical data of the output voltage of the data storage cell.
25. The method of claim 24, wherein the data storage cell probability density function is dependent upon one or more of a number of data storage cells or a number of redundant data storage cells.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A clock generation apparatus comprising:
AD conversion means for converting an input analog signal into a digital signal;
arithmetic means for generating a threshold used as a reference when binarizing the digital signal to generate a binary signal and a synchronous clock for sampling the binary signal, on the basis of the digital signal;
binarization means for comparing the digital signal with the threshold generated by the arithmetic means, and outputting a result of the comparison as the binary signal; and
latch means for latching the binary signal with the synchronous clock and outputting a synchronous signal, wherein
the arithmetic means comprises:
threshold detection means for detecting a maximum value and a minimum value of the digital signal in a predetermined period, and outputting an average of the maximum value and the minimum value as the threshold;
rise time detection means for detecting a rise time as a time of intersection of the threshold and a line connecting two values of the digital signal, one of the two values being lower that the threshold and another of the two values being higher than the threshold, when the digital signal changes from the lower value to the higher value;
fall time detection means for detecting a fall time as a time of intersection of the threshold and a line connecting two values of the digital signal, one of the two values being higher than the threshold and another of the two values being lower than the threshold, when the digital signal changes from the higher value to the lower value;
input rate detection means for obtaining time intervals between adjacent rise and fall times during a predetermined period, and outputting a minimum value of the time intervals as an input rate of the input analog signal; and
synchronous clock output means for obtaining a half timing of the input rate after an edge of the input analog signal is detected on the basis of the input rate and the rise and fall times and outputting a first one of the synchronous clock at that timing, and obtaining a timing of the input rate after the first synchronous clock is output and outputting a second or later one of the synchronous clock at that timing.
2. A clock generation apparatus comprising:
AD conversion means for converting an input analog signal into a digital signal;
arithmetic means for generating a threshold used as a reference when binarizing the digital signal to generate a binary signal and a synchronous clock for sampling the binary signal, on the basis of the digital signal;
binarization means for comparing the digital signal with the threshold generated by the arithmetic means, and outputting a result of the comparison as the binary signal; and
latch means for latching the binary signal with the synchronous clock and outputting a synchronous signal; wherein
the arithmetic means comprises:
threshold detection means for detecting integrals of the digital signal in a predetermined period, and outputting an average of the integrals as the threshold;
rise time detection means for detecting a rise time as a time of intersection of the threshold and a line connecting two values of the digital signal, one of the two values being lower than the threshold and another of the two values being higher than the threshold, when the digital signal changes from the lower value to the higher value;
fall time detection means for detecting a fall time as a time of intersection of the threshold and a line connecting two values of the digital signal, one of the two values being higher than the threshold and another of the two values being lower than the threshold, when the digital signal changes from the higher value to the lower value;
input rate detection means for obtaining time intervals between adjacent rise and fall times during a predetermined period, and outputting a minimum value of the time intervals as an input rate of the input analog signal; and
synchronous clock output means for obtaining a half timing of the input rate after an edge of the input analog signal is detected on the basis of the input rate and the rise and fall times and outputting a first one of the synchronous clock at that timing, and obtaining a timing of the input rate after the first synchronous clock is output and outputting a second or later one of the synchronous clock at that timing.
3. The clock generation apparatus of claim 1, further comprising:
an oversampling digital filter for interpolating adjacent digital signals.
4. The clock generation apparatus of claim 2, further comprising:
an oversampling digital filter for interpolating adjacent digital signals.