All The Claims

1. An integrated circuit, comprising:
a first finfet transistor of a first transistor type;
a first finfet transistor of a second transistor type;
a second finfet transistor of the first transistor type;
a second finfet transistor of the second transistor type,
each of the first and second finfet transistors of the first transistor type and each of the first and second finfet transistors of the second transistor type having a respective gate electrode extending lengthwise in a parallel direction, the gate electrodes of the first finfet transistor of the first transistor type and the first finfet transistor of the second transistor type having their lengthwise centerlines substantially aligned to a common gate electrode track extending in the parallel direction, the gate electrodes of the second finfet transistor of the first transistor type and the second finfet transistor of the second transistor type positioned on opposite sides of the common gate electrode track,
each of the first and second finfet transistors of the first transistor type formed in part by a respective diffusion fin of a first diffusion type electrically connected to a common node,
each of the first and second finfet transistors of the second transistor type formed in part by a respective diffusion fin of a second diffusion type electrically connected to the common node, the diffusion fins of the first diffusion type collectively separated from the diffusion fins of the second diffusion type in the parallel direction by an inner non-diffusion region,
the gate electrodes of both the first finfet transistor of the first transistor type and the first finfet transistor of the second transistor type formed by a first conductive structure so as to be electrically connected to each other through the first conductive structure, the gate electrode of the second finfet transistor of the first transistor type formed by a second conductive structure, the gate electrode of the second finfet transistor of the second transistor type formed by a third conductive structure, each of the first, second, and third conductive structures including portions extending over the inner non-diffusion region;
a first conductive contacting structure connected to the portion of the second conductive structure that extends over the inner non-diffusion region; and
a second conductive contacting structure connected to the portion of the third conductive structure that extends over the inner non-diffusion region, each of the first and second conductive contacting structures respectively defined as either a gate contact or a local interconnect structure.
2. An integrated circuit as recited in claim 1, wherein at least one end of the second conductive structure and at least one end of the third conductive structure are aligned to a first common position in the parallel direction.
3. An integrated circuit as recited in claim 2, wherein at least a portion of the first conductive contacting structure and at least a portion of the second conductive contacting structure are aligned to a second common position in the parallel direction.
4. An integrated circuit as recited in claim 3, further comprising:
a third finfet transistor of the first transistor type;
a third finfet transistor of the second transistor type;
a fourth finfet transistor of the first transistor type; and
a fourth finfet transistor of the second transistor type,
each of the third and fourth finfet transistors of the first transistor type and each of the third and fourth finfet transistors of the second transistor type having a respective gate electrode extending lengthwise in the parallel direction,
each gate electrode of the third and fourth finfet transistors of the first transistor type and each gate electrode of the third and fourth finfet transistors of the second transistor type formed as part of a corresponding linear-shaped conductive structure, and
each of the first, second, and third conductive structures having a linear shape.
5. An integrated circuit as recited in claim 4, further comprising:
a non-transistor linear-shaped gate level feature, wherein each linear-shaped conductive structure that forms at least one gate electrode of the first, second, third, and fourth finfet transistors of the first transistor type and the first, second, third, and fourth finfet transistors of the second transistor type is positioned according to a gate pitch defined as an equal center-to-center spacing measured in a second direction between adjacent gate level features, the second direction perpendicular to the parallel direction, and wherein the non-transistor linear-shaped gate level feature is also positioned according to the gate pitch.
6. An integrated circuit as recited in claim 1, wherein the second conductive structure is electrically connected to the third conductive structure through an electrical connection that extends in part through a single interconnect level.
7. An integrated circuit as recited in claim 6, further comprising:
a third finfet transistor of the first transistor type;
a third finfet transistor of the second transistor type;
a fourth finfet transistor of the first transistor type; and
a fourth finfet transistor of the second transistor type,
each of the third and fourth finfet transistors of the first transistor type and each of the third and fourth finfet transistors of the second transistor type having a respective gate electrode extending lengthwise in the parallel direction,
each gate electrode of the first, second, third, and fourth finfet transistors of the first transistor type and of the first, second, third, and fourth finfet transistors of the second transistor type positioned according to a gate pitch defined as an equal center-to-center spacing measured in a second direction between adjacent gate electrodes, the second direction perpendicular to the parallel direction.
8. An integrated circuit as recited in claim 7, wherein at least a portion of the first conductive contacting structure and at least a portion of the second conductive contacting structure are aligned to a common position in the parallel direction.
9. An integrated circuit as recited in claim 8, wherein the part of the electrical connection that extends through the single interconnect level is formed by a linear-shaped interconnect conductive structure.
10. An integrated circuit as recited in claim 9, wherein each gate electrode of the third and fourth finfet transistors of the first transistor type and each gate electrode of the third and fourth finfet transistors of the second transistor type is formed as part of a corresponding linear-shaped conductive structure, and wherein each of the first, second, and third conductive structures is linear-shaped.
11. An integrated circuit as recited in claim 1, further comprising:
a non-transistor gate level feature positioned next to and spaced apart from multiple diffusion fins of the first diffusion type, and the non-transistor gate level feature positioned next to and spaced apart from multiple diffusion fins of the second diffusion type.
12. An integrated circuit as recited in claim 11, further comprising:
a third finfet transistor of the first transistor type;
a third finfet transistor of the second transistor type;
a fourth finfet transistor of the first transistor type; and
a fourth finfet transistor of the second transistor type,
each of the third and fourth finfet transistors of the first transistor type and each of the third and fourth finfet transistors of the second transistor type having a respective gate electrode extending lengthwise in the parallel direction,
each gate electrode of the third and fourth finfet transistors of the first transistor type and each gate electrode of the third and fourth finfet transistors of the second transistor type formed as part of a corresponding linear-shaped conductive structure, and
each of the first, second, and third conductive structures having a linear shape, and
wherein the non-transistor gate level feature is linear-shaped.
13. An integrated circuit as recited in claim 12, wherein each of the first and second finfet transistors of the first transistor type is formed in part by a shared diffusion fin of the first diffusion type, and wherein each of the first and second finfet transistors of the second transistor type is formed in part by a shared diffusion fin of the second diffusion type, the shared diffusion fins of the first and second diffusion types electrically connected to the common node.
14. An integrated circuit as recited in claim 13, wherein each linear-shaped conductive structure that forms at least one gate electrode of the first, second, third, and fourth finfet transistors of the first transistor type and the first, second, third, and fourth finfet transistors of the second transistor type is positioned according to a gate pitch defined as an equal center-to-center spacing measured in a second direction between adjacent gate level features, the second direction perpendicular to the parallel direction, and wherein the non-transistor linear-shaped gate level feature is also positioned according to the gate pitch.
15. An integrated circuit as recited in claim 14, wherein a centerline-to-centerline distance as measured in the second direction between the gate electrodes of the first and second finfet transistors of the first transistor type is substantially equal to a centerline-to-centerline distance as measured in the second direction between the gate electrodes of the first and second finfet transistors of the second transistor type.
16. An integrated circuit as recited in claim 1, wherein each of the first and second finfet transistors of the first transistor type is formed in part by a shared diffusion fin of the first diffusion type, and wherein each of the first and second finfet transistors of the second transistor type is formed in part by a shared diffusion fin of the second diffusion type, the shared diffusion fins of the first and second diffusion types electrically connected to the common node.
17. An integrated circuit as recited in claim 16, further comprising:
a non-transistor gate level feature positioned next to and spaced apart from multiple diffusion fins of the first diffusion type, and the non-transistor gate level feature positioned next to and spaced apart from multiple diffusion fins of the second diffusion type.
18. An integrated circuit as recited in claim 17, wherein the second conductive structure is electrically connected to the third conductive structure through an electrical connection that extends in part through a single interconnect level.
19. An integrated circuit as recited in claim 18, further comprising:
a third finfet transistor of the first transistor type;
a third finfet transistor of the second transistor type;
a fourth finfet transistor of the first transistor type;
a fourth finfet transistor of the second transistor type,
each of the third and fourth finfet transistors of the first transistor type and each of the third and fourth finfet transistors of the second transistor type having a respective gate electrode extending lengthwise in the parallel direction,
each gate electrode of the third and fourth finfet transistors of the first transistor type and each gate electrode of the third and fourth finfet transistors of the second transistor type formed as part of a corresponding linear-shaped conductive structure, and
each of the first, second, and third conductive structures having a linear shape; and
a non-transistor linear-shaped gate level feature.
20. An integrated circuit as recited in claim 19, wherein the part of the electrical connection that extends through the single interconnect level is formed by a linear-shaped interconnect conductive structure.
21. An integrated circuit as recited in claim 1, further comprising:
a gate level feature that forms a gate electrode of a finfet transistor of the first transistor type and that extends between at least two diffusion fins of the second diffusion type.
22. An integrated circuit as recited in claim 21, wherein each of the first and second finfet transistors of the first transistor type is formed in part by a shared diffusion fin of the first diffusion type, and wherein each of the first and second finfet transistors of the second transistor type is formed in part by a shared diffusion fin of the second diffusion type, the shared diffusion fins of the first and second diffusion types electrically connected to the common node.
23. An integrated circuit as recited in claim 22, wherein a centerline-to-centerline distance as measured in a second direction between the gate electrodes of the first and second finfet transistors of the first transistor type is substantially equal to a centerline-to-centerline distance as measured in the second direction between the gate electrodes of the first and second finfet transistors of the second transistor type, the second direction perpendicular to the parallel direction.
24. An integrated circuit as recited in claim 23, further comprising:
a third finfet transistor of the first transistor type;
a third finfet transistor of the second transistor type;
a fourth finfet transistor of the first transistor type; and
a fourth finfet transistor of the second transistor type,
each of the third and fourth finfet transistors of the first transistor type and each of the third and fourth finfet transistors of the second transistor type having a respective gate electrode extending lengthwise in the parallel direction,
each gate electrode of the third and fourth finfet transistors of the first transistor type and each gate electrode of the third and fourth finfet transistors of the second transistor type formed as part of a corresponding linear-shaped conductive structure, and
each of the first, second, and third conductive structures having a linear shape.
25. A method for creating a layout of an integrated circuit, comprising:
operating a computer to define a layout of a first finfet transistor of a first transistor type;
operating the computer to define a layout of a first finfet transistor of a second transistor type;
operating the computer to define a layout of a second finfet transistor of the first transistor type;
operating the computer to define a layout of a second finfet transistor of the second transistor type,
each layout of the first and second finfet transistors of the first transistor type and each layout of the first and second finfet transistors of the second transistor type having a respective gate electrode layout feature extending lengthwise in a parallel direction, the gate electrode layout features of the first finfet transistor of the first transistor type and the first finfet transistor of the second transistor type having their lengthwise centerlines substantially aligned to a common gate electrode track extending in the parallel direction, the gate electrode layout features of the second finfet transistor of the first transistor type and the second finfet transistor of the second transistor type positioned on opposite sides of the common gate electrode track,
each layout of the first and second finfet transistors of the first transistor type including a respective diffusion fin layout of a first diffusion type to be electrically connected to a common node,
each layout of the first and second finfet transistors of the second transistor type including a respective diffusion fin layout of a second diffusion type to be electrically connected to the common node, the diffusion fin layouts of the first diffusion type collectively separated from the diffusion fin layouts of the second diffusion type in the parallel direction by an inner non-diffusion layout region,
the gate electrode layout features of both the first finfet transistor of the first transistor type and the first finfet transistor of the second transistor type formed as parts of a first conductive structure layout feature so as to be electrically connected to each other through a conductive structure corresponding to the first conductive structure layout feature, the gate electrode layout feature of the second finfet transistor of the first transistor type formed as part of a second conductive structure layout feature, the gate electrode layout feature of the second finfet transistor of the second transistor type formed as part of a third conductive structure layout feature, each of the first, second, and third conductive structure layout features including portions extending over the inner non-diffusion layout region;
operating the computer to define a layout of a first conductive contacting structure defined to connect to a portion of a conductive structure corresponding to the portion of the second conductive structure layout feature that extends over the inner non-diffusion region; and
operating the computer to define a layout of a second conductive contacting structure defined to connect to a portion of a conductive structure corresponding to the portion of the third conductive structure layout feature that extends over the inner non-diffusion region, each of the first and second conductive contacting structures respectively defined as either a gate contact or a local interconnect structure.
26. A data storage device having program instructions stored thereon for generating a layout of an integrated circuit, comprising:
program instructions for defining a layout of a first finfet transistor of a first transistor type;
program instructions for defining a layout of a first finfet transistor of a second transistor type;
program instructions for defining a layout of a second finfet transistor of the first transistor type;
program instructions for defining a layout of a second finfet transistor of the second transistor type,
each layout of the first and second finfet transistors of the first transistor type and each layout of the first and second finfet transistors of the second transistor type having a respective gate electrode layout feature extending lengthwise in a parallel direction, the gate electrode layout features of the first finfet transistor of the first transistor type and the first finfet transistor of the second transistor type having their lengthwise centerlines substantially aligned to a common gate electrode track extending in the parallel direction, the gate electrode layout features of the second finfet transistor of the first transistor type and the second finfet transistor of the second transistor type positioned on opposite sides of the common gate electrode track,
each layout of the first and second finfet transistors of the first transistor type including a respective diffusion fin layout of a first diffusion type to be electrically connected to a common node,
each layout of the first and second finfet transistors of the second transistor type including a respective diffusion fin layout of a second diffusion type to be electrically connected to the common node, the diffusion fin layouts of the first diffusion type collectively separated from the diffusion fin layouts of the second diffusion type in the parallel direction by an inner non-diffusion layout region,
the gate electrode layout features of both the first finfet transistor of the first transistor type and the first finfet transistor of the second transistor type formed as parts of a first conductive structure layout feature so as to be electrically connected to each other through a conductive structure corresponding to the first conductive structure layout feature, the gate electrode layout feature of the second finfet transistor of the first transistor type formed as part of a second conductive structure layout feature, the gate electrode layout feature of the second finfet transistor of the second transistor type formed as part of a third conductive structure layout feature, each of the first, second, and third conductive structure layout features including portions extending over the inner non-diffusion layout region;
program instructions for defining a layout of a first conductive contacting structure defined to connect to a portion of a conductive structure corresponding to the portion of the second conductive structure layout feature that extends over the inner non-diffusion region; and
program instructions for defining a layout of a second conductive contacting structure defined to connect to a portion of a conductive structure corresponding to the portion of the third conductive structure layout feature that extends over the inner non-diffusion region, each of the first and second conductive contacting structures respectively defined as either a gate contact or a local interconnect structure.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method for eliminating noises with multi-microphone array, the method comprising
according to the number of different spacings between each of pairs of microphones of the multi-microphone array, dividing a full frequency band into the same number of sub-bands;
decomposing signals of each of the pairs of microphones with the different spacings into a corresponding one of the sub-bands, wherein the larger the spacing between each pair of microphones is, the lower the frequencies of the sub-band into which the signals of the pair of microphones are decomposed will be;
adaptively reducing the noises in the decomposed signals of each of the pairs of microphones with the different spacings in the corresponding sub-band to obtain noise-reduced signals for each of the sub-bands; and
synthesizing the noise-reduced signals of each of the sub-bands to obtain a signal in which the noises have been reduced with the multi-microphone array in the full frequency band.
2. The method of claim 1, further comprising
acquiring a control parameter of an adaptive filter according to the amount of target signal components within a protection angle, and inputting the control parameter into the adaptive filter that adaptively reduces the noises in the corresponding sub-band.
3. The method of claim 2, wherein the step of acquiring a control parameter of an adaptive filter according to the amount of target signal components within a protection angle comprises
transforming the signals of each of the microphones of the multi-microphone array into a frequency domain through Discrete Fourier Transform (DFT);
calculating relative delay of the signals of each of the pairs of microphones with the different spacings in the frequency domain;
calculating signal incidence angle of each of the pairs of microphones according to the relative delay and the corresponding one of the different spacings; and
making statistics on the amount of signal components, whose incidence angle is within the protection angle, for each of the pairs of microphones and obtaining the control parameter of the adaptive filter through conversion according to the statistic result.
4. The method of claim 3, wherein the step of making statistics on the amount of signal components whose incidence angle is within the protection angle, for each of the pairs of microphones and obtaining the control parameter of the adaptive filter through conversion according to the statistic result comprises
making statistics on the amount of signal components whose incidence angle is within the protection angle, for each of the pairs of microphones in the full frequency band and obtaining a unified control parameter \u03b1 of the adaptive filter in the full frequency band through conversion according to the statistic result,
wherein 0\u2266\u03b1\u22661, the more the components within the protection angle are, the smaller the value of \u03b1 will be, and the lower an updating speed of the adaptive filter will be, and if all are the components within the protection angle, then \u03b1=0, and the adaptive filter will not be updated; and conversely, the more the components outside the protection angle are, the larger the value of \u03b1 will be, and the higher the updating speed of the adaptive filter will be, and if all are the components outside the protection angle, then \u03b1=1, and the adaptive filter will be updated at the maximum speed.
5. The method of claim 3, wherein the step of making statistics on the amount of signal components whose incidence angle is within the protection angle, for each of the pairs of microphones and obtaining the control parameter of the adaptive filter through conversion according to the statistic result comprises
making statistics on the amount of signal components whose incidence angle is within the protection angle, for each of the pairs of microphones in each of the sub-bands, respectively, and obtaining a control parameter \u03b1i of the ith sub-band through conversion according to the statistic result,
wherein 0\u2266\u03b1i\u22661, the more the components within the protection angle are, the smaller the value of \u03b1i will be, and the lower an updating speed of the adaptive filter of the sub-band will be, and if all of the components within the protection angle, then \u03b1i=0, and the adaptive filter of the sub-band will not be updated; and conversely, the more the components outside the protection angle are, the larger the value of \u03b1i will be, and the higher the updating speed of the adaptive filter of the sub-band will be, and if all of the components outside the protection angle, then \u03b1i=1, and the adaptive filter of the sub-band will be updated at the maximum speed.
6. The method of any of claim 1 to claim 5, wherein the step of decomposing signals of each of the pairs of microphones with the different spacings into a corresponding one of the sub-bands comprises
selecting a low-pass filter, a band-pass filter and a high-pass filter to filter the signals of each of the pairs of microphones with the different spacings, respectively, to obtain decomposed signals in the corresponding sub-band; or
using an analysis filter set to decompose the signals of each of the pairs of microphones with the different spacings into the corresponding sub-band.
7. The method of claim 6, wherein the step of synthesizing the noise-reduced signals of each of the sub-bands to obtain a signal in which the noises have been reduced with the multi-microphone array in the full frequency band comprises
for the sub-band decomposition approach of selecting a low-pass filter, a band-pass filter and a high-pass filter to filter the signals, respectively, to obtain decomposed signals in the corresponding sub-band, obtaining the full frequency band noise-reduced signal by using a sub-band synthesis approach of directly adding the noise-reduced signals of each of the sub-bands together; or
for the sub-band decomposition approach of using an analysis filter set to obtain decomposed signals in the corresponding sub-band, obtaining the full frequency band noise-reduced signal by using a sub-band synthesis approach of using a corresponding synthesis filter set to synthesize the noise-reduced signals of each of the sub-bands.
8. The method of any of claim 2 to claim 5, wherein the step of adaptively reducing the noises in the decomposed signals of each of the pairs of microphones with the different spacings in the corresponding sub-band comprises
acquiring two signals of each of the pairs of microphones with the different spacings in the corresponding sub-band to obtain an desired signal and a reference signal of the sub-band, respectively;
inputting the reference signal into the adaptive filter to be filtered, subtracting the filtered signal from the desired signal to obtain an output signal, and feeding the output signal back to the adaptive filter to update a weight of the adaptive filter; and
controlling the updating speed of the adaptive filter by means of the control parameter.
9. A device for eliminating noises with multi-microphone array, the device comprising
a sub-band decomposition unit, being configured to, according to the number of different spacings between each of pairs of microphones of the multi-microphone array, divide a full frequency band into the same number of sub-bands, and to decompose signals of each of the pairs of microphones with the different spacings into a corresponding one of the sub-bands, wherein the larger the spacing between each pair of microphones is, the lower the frequencies of the sub-band into which the signals of the pair of microphones are decomposed will be;
an adaptive filter, being configured to adaptively reduce the noises in the decomposed signals of each of the pairs of microphones with the different spacings in the corresponding sub-band to obtain noise-reduced signals for each of the sub-bands; and
a sub-band synthesizing unit, being configured to synthesize the noise-reduced signals of each of the sub-bands to obtain a signal in which the noises have been reduced with the multi-microphone array in the full frequency band.
10. The device of claim 9, further comprising:
a noise-reduction control unit, being configured to acquire a control parameter of the adaptive filter according to the amount of target signal components within a protection angle, and input the control parameter into the adaptive filter that adaptively reduces the noises in the corresponding sub-band.
11. The device of claim 10, wherein the noise-reduction control unit comprises
a DFT module, being configured to transform the signal of each of the microphones of the multi-microphone array into a frequency domain through Discrete Fourier Transform (DFT);
a delay calculation module, being configured to calculate a relative delay of the signals of each of the pairs of microphones with the different spacings in the frequency domain;
a direction calculation module, being configured to calculate a signal incidence angle of each of the pairs of microphones according to the relative delay and the corresponding one of the different spacings; and
a control parameter acquiring module, being configured to make statistics on the amount of signal components whose incidence angle is within the protection angle, for each of the pairs of microphones and obtain the control parameter of the adaptive filter through conversion according to the statistic result.
12. The device of claim 11, wherein the control parameter acquiring module is
a full frequency band control parameter acquiring module, being configured to make statistics on the amount of signal components whose incidence angle is within the protection angle, for each of the pairs of microphones in the full frequency band and obtain a unified control parameter \u03b1 of the adaptive filter in the full frequency band through conversion according to the statistic result, wherein 0\u2266\u03b1\u22661, the more the components within the protection angle are, the smaller the value of \u03b1 will be, and the lower an updating speed of the adaptive filter will be, and if all are the components within the protection angle, then \u03b1=0, and the adaptive filter will not be updated; and conversely, the more the components outside the protection angle are, the larger the value of \u03b1 will be, and the higher the updating speed of the adaptive filter will be, and if all are the components outside the protection angle, then \u03b1=1, and the adaptive filter will be updated at the maximum speed.
13. The device of claim 11, wherein the control parameter acquiring module is
a sub-band control parameter acquiring module, being configured to make statistics on the amount of signal components whose incidence angle is within the protection angle, for each of the pairs of microphones in each of the sub-bands, respectively, and obtain a control parameter \u03b1i of the ith sub-band through conversion according to the statistic result, wherein 0\u2266\u03b1i\u22661, the more the components, within the protection angle, of the signal incidence angle are, the smaller the value of \u03b1i will be, and the lower an updating speed of the adaptive filter of the sub-band will be, and if all the signal incidence angle is of components within the protection angle, then \u03b1i=0, and the adaptive filter of the sub-band will not be updated; and conversely, the more the components, outside the protection angle, of the signal incidence angle are, the larger the value of \u03b1i will be, and the higher the updating speed of the adaptive filter of the sub-band will be, and if all the signal incidence angle is of the components outside the protection angle, then \u03b1i=1, and the adaptive filter of the sub-band will be updated at the maximum speed.
14. The device of claim 9, wherein the sub-band decomposition unit is configured to select a low-pass filter, a band-pass filter and a high-pass filter to filter the signals of each of the pairs of microphones with the different spacings, respectively, to obtain signals in the corresponding sub-band; or use an analysis filter set to decompose the signals of each of the pairs of microphones with the different spacings into the corresponding sub-band.
15. The device of claim 14, wherein the sub-band synthesizing unit is configured to, for the sub-band decomposition approach of the sub-band decomposition unit which selects a low-pass filter, a band-pass filter and a high-pass filter to filter the signals, respectively, to obtain decomposed signals in the corresponding sub-band, obtain the full frequency band noise-reduced signal by using a sub-band synthesis approach of directly adding the noise-reduced signals of each of the sub-bands together; and for the sub-band decomposition approach of the sub-band decomposition unit which uses an analysis filter set to obtain decomposed signals in the corresponding sub-band, obtain the full frequency band noise-reduced signal by using a sub-band synthesis approach of using a corresponding synthesis filter set to synthesize the noise-reduced signals of each of the sub-bands.
16. A system for eliminating noises with multi-microphone array, the system comprising
a multi-microphone array, the multi-microphone array consisting of three or more microphones which have equal or different spacings therebetween; and
the device for eliminating noises with multi-microphone array of any of claim 9 to claim 15, being configured to perform noise reduction processing on signals collected by the multi-microphone array.

1. An electronic device comprising: a blade comprising: a faceplate; and a handle out locked position ejector configured to secure the blade to a chassis, the handle out locked position ejector extending outwardly from the faceplate when the handle out locked position ejector is in a closed position, the handle out locked position ejector comprising: two ejectors; and a mechanical attachment bar binding the two ejectors together; wherein the handle out locked position elector extends perpendicularly from the faceplate when the handle out locked position elector is in the closed position; and wherein the blade is locked to the chassis when the handle out locked position elector is in the closed position.
2. The electronic device of claim 1 wherein each ejector comprises:
an ejector handle; and
an ejector cam and tooth.
3. The electronic device of claim 2 wherein the ejector cam and tooth comprises an ejector tooth configured to engage a locking feature of the chassis.
4. The electronic device of claim 2 wherein the ejector handle is coupled to the ejector cam and tooth such that motion of the ejector handle causes motion of the ejector cam and tooth.
5. The electronic device of claim 4 wherein pivoting of the ejector handle in a first direction causes pivoting of the ejector cam and tooth in a second direction opposite the first direction.
6. The electronic device of claim 2 wherein the ejector cam and tooth comprises a locking mechanism for locking the handle out locked position ejector in place, the electronic device further comprising a sensor to sense a position of the locking mechanism.
7. An electronic device comprising: a blade comprising two handle out locked position ejectors comprising mechanical attachment bars; and a cable management system removably attached to the mechanical attachment bars; wherein each of the handle out locked position electors comprises: two electors; and one of the mechanical attachment bars binding the two electors together; and wherein the cable management system has snapping features configured to snap on and off the mechanical attachment bars.
8. The electronic device of claim 7 wherein the cable management system comprises a captive end and a snapping end.
9. The electronic device of claim 8 wherein the captive end comprises a slot like feature.
10. The electronic device of claim 8 wherein the snapping end comprises a C shaped opening.
11. The electronic device of claim 7 further comprising:
cabling coupled to ports of the blade, the cabling being supported by the cable management system.
12. The electronic device of claim 7 wherein the cable management system comprises apertures configured to secure cables.
13. The electronic device of claim 7 wherein the mechanical attachment bars comprise at least one protruding feature.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. An electron beam exposure apparatus, comprising:
a first shaping aperture having a plurality of rectangular openings, each having sizes different from each other and shaping a beam shape of an electron beam;
a rectangular opening selection deflector which controls a path of the electron beam to irradiate the electron beam on one of the plurality of rectangular openings;
a second shaping aperture having a plurality of character openings, each having sizes different from each other and shaping a beam shape of the electron beam passing through the first shaping aperture; and
a character beam deflector which controls the path of the electron beam to irradiate the electron beam on character openings corresponding to the rectangular openings in the first shaping aperture.
2. The electron beam exposure apparatus according to claim 1,
wherein the second shaping aperture includes a character opening of a first size which is suitable for drawing of repetitive structure, a character opening of a second size smaller than the first size which is suitable for drawing of random structure, and a character opening for shaping a variable shaped beam (VSB).
3. The electron beam exposure apparatus according to claim 2,
wherein the character beam deflector uses the character opening of the second size when a combination logic circuit and a sequential circuit are drawn, and uses the character opening of the first size when a memory cell circuit is drawn.
4. The electron beam exposure apparatus according to claim 1, further comprising a deflection controller which controls the rectangular opening selection deflector and the character beam deflector in accordance with a circuit type to be drawn.
5. The electron beam exposure apparatus according to claim 1, further comprising:
an aperture information storage which stores drawing information showing a correspondence relationship between first information indicative of sizes and types of the rectangular openings in the first shaping aperture and second information relating to positions and types of the character openings in the second shaping aperture; and
a drawing controller which controls the rectangular opening selection deflector and the character beam deflector based on drawing information stored in the aperture information storage.
6. The electron beam exposure apparatus according to claim 5,
wherein the aperture information storage stores the drawing information including character ID information indicative of character shape to be drawn; and
the drawing controller reads out the drawing information corresponding to the character ID information and controls the rectangular opening selection deflector and the character beam deflector.
7. The electron beam exposure apparatus according to claim 5,
wherein the aperture information storage has a character table indicative of a correspondence relationship of the character ID information, the first information and the second information.
8. An electron beam exposure method, comprising:
irradiating an electron beam on a first shaping aperture having a plurality of rectangular openings, each having sizes different from each other and shaping a beam shape of the electron beam;
controlling a path of the electron beam to irradiate the electron beam on one of the plurality of rectangular openings;
irradiating the electron beam passing through the first shaping aperture on a second shaping aperture having a plurality of character openings, each having sizes different from each other and shaping a beam shape of the electron beam; and
controlling the path of the electron beam by a character deflector to irradiate the electron beam on character openings corresponding to the rectangular openings in the first shaping aperture.
9. The electron beam exposure method according to claim 8,
wherein the second shaping aperture includes a character opening of a first size which is suitable for drawing of repetitive structure, a character opening of a second size smaller than the first size which is suitable for drawing of random structure, and a character opening for shaping a variable shaped beam (VSB).
10. The electron beam exposure method according to claim 9,
wherein the character beam deflector uses the character opening of the second size when a combination logic circuit and a sequential circuit are drawn, and uses the character opening of the first size when a memory cell circuit is drawn.
11. The electron beam exposure method according to claim 8,
wherein the rectangular opening selection deflector and the character beam deflector are controlled in accordance with the types of the circuit to be drawn.
12. The electron beam exposure method according to claim 8, further comprising:
controlling the rectangular opening selection deflector and the character beam deflector based on drawing information stored in an aperture information storage which stores the drawing information indicative of a correspondence relationship between first information indicative of sizes or types of the rectangular openings in the first shaping aperture and second information relating to positions and types of the character openings in the second shaping aperture.
13. The electron beam exposure method according to claim 12,
wherein the aperture information storage stores the drawing information including character ID information indicative of character shapes to be drawn; and
when controlling the character beam deflector, the drawing information corresponding to the character ID information is read out from the aperture information storage and controls the rectangular opening selection deflector and the character beam deflector.
14. The electron beam exposure method according to claim 12,
wherein the aperture information storage has a character table indicative of a correspondence relationship of the character ID information, the first information and the second information.
15. A method of manufacturing semiconductor device, comprising:
irradiating an electron beam on a first shaping aperture having a plurality of rectangular openings, each having sizes different from each other and shaping a beam shape of the electron beam;
controlling a path of the electron beam to irradiate the electron beam on one of the plurality of rectangular openings;
irradiating the electron beam passing through the first shaping aperture on a second shaping aperture having a plurality of character openings, each having sizes different from each other and shaping a beam shape of the electron beam;
controlling the path of the electron beam by a character deflector to irradiate the electron beam on character openings corresponding to the rectangular openings in the first shaping aperture; and
irradiating the electron beam passing through the character opening on a wafer to fabricate a semiconductor device.
16. The method of manufacturing semiconductor device according to claim 15,
wherein the second shaping aperture includes a character opening of a first size which is suitable for drawing of repetitive structure, a character opening of a second size smaller than the first size which is suitable for drawing of random structure, and a character opening for shaping a variable shaped beam (VSB).
17. The method of manufacturing semiconductor device according to claim 16,
wherein the character beam deflector uses the character opening of the second size when a combination logic circuit and a sequential circuit are drawn, and uses the character opening of the first size when a memory cell circuit is drawn.
18. The method of manufacturing semiconductor device according to claim 15,
wherein the rectangular opening selection deflector and the character beam deflector are controlled in accordance with the types of the circuit to be drawn.
19. The method of manufacturing semiconductor device according to claim 15, further comprising:
controlling the rectangular opening selection deflector and the character beam deflector based on drawing information stored in an aperture information storage which stores the drawing information indicative of a correspondence relationship between first information indicative of sizes or types of the rectangular openings in the first shaping aperture and second information relating to positions and types of the character openings in the second shaping aperture.
20. The method of manufacturing semiconductor device according to claim 19,
wherein the aperture information storage stores the drawing information including character ID information indicative of character shapes to be drawn; and
when controlling the character beam deflector, the drawing information corresponding to the character ID information is read out from the aperture information storage and controls the rectangular opening selection deflector and the character beam deflector.