All The Claims

1. A method for preventing snap-back current in a circuit including a first N-channel MOS (NMOS) transistor having an associated parasitic bipolar transistor, the method comprising:
connecting a second NMOS transistor in series with the first NMOS transistor;
coupling a gate node of the second NMOS transistor to a bias node, such that the second NMOS transistor is in a continuous conductive state; and
coupling a source node of the first NMOS transistor to an output node of an auxiliary circuit, the auxiliary circuit being configured to provide a bias potential at the source of the first NMOS transistor when the first NMOS transistor is in a non-conducting state (OFF), and to provide a zero potential at the source of the first NMOS transistor when the first NMOS transistor is in a conducting state,
wherein a combination of the second NMOS transistor in the continuous conductive state and the bias potential at the source of the first NMOS transistor when the first NMOS transistor is in a non-conducting state prevents the associated parasitic bipolar transistor from turning on.
2. The method of claim 1, wherein connecting the second NMOS transistor in series with the first NMOS transistor includes coupling a drain node of the first NMOS transistor to a source node of the second NMOS transistor.
3. The method of claim 2, wherein the drain node of the second NMOS transistor forms an output node of the circuit.
4. The method of claim 1, wherein coupling the gate node of the second NMOS transistor to the bias node includes connecting the bias node to a highest-voltage node of the circuit.
5. The method of claim 1, wherein the auxiliary circuit is configured to provide a positive bias potential at the source node of the first NMOS transistor.
6. A snap-back tolerant circuit comprising:
a first NMOS transistor having an associated parasitic bipolar transistor, a source node of the first NMOS transistor being coupled to an output node of an auxiliary circuit, the auxiliary circuit being configured to provide a bias potential at the source node of the first NMOS transistor when the first NMOS transistor is in a non-conducting state (OFF), and to provide a zero potential at the source of the first NMOS transistor when the first NMOS transistor is in a conducting state;
a second NMOS transistor connected in series with the first NMOS transistor, a source node of the second NMOS transistor being coupled to a drain node of the first NMOS transistor, a gate node of the second NMOS transistor being coupled to a bias node, such that the second NMOS transistor is in a continuous conductive state,
wherein a combination of the second NMOS transistor in the continuous conductive state and the bias potential at the source of the first NMOS transistor when the first NMOS transistor is in a non-conducting state prevents the associated parasitic bipolar transistor from turning on.
7. The circuit of claim 6, wherein a drain node of the second NMOS transistor forms an output node of the snap-back tolerant circuit.
8. The circuit of claim 6, wherein the bias node is connected to a highest voltage node of the circuit.
9. The circuit of claim 6, wherein the auxiliary circuit is configured to provide a positive bias potential at the source node of the first NMOS transistor.
10. A snap-back tolerant driver comprising:
a level shifter circuit configured to provide a high voltage at an output node; and
an inverter circuit having an input node coupled to the output node, at least one of the level shifter circuit and the inverter circuit including:
a first NMOS transistor having an associated parasitic bipolar transistor, a source node of the first NMOS transistor being coupled to an output node of an auxiliary circuit, the auxiliary circuit being configured to provide a bias potential at the source node of the first NMOS transistor when the first NMOS transistor is in a non-conducting state (OFF), the bias potential preventing the associated parasitic bipolar transistor from turning on; and
a second NMOS transistor in series with the first NMOS transistor, a source node of the second NMOS transistor being coupled to a drain node of the first NMOS transistor, a gate node of the second NMOS transistor being coupled to a bias node, such the second NMOS transistor is conductive.
11. The snap-back tolerant driver of claim 10, wherein the bias node is connected to a highest-voltage node of the circuit.
12. The snap-back tolerant driver of claim 10, wherein a drain node of the second NMOS transistor forms an output of the at least one of the level shifter circuit and the inverter circuit.
13. The snap-back tolerant driver of claim 10, wherein the auxiliary circuit is configured to provide a positive bias potential at the source node of the first NMOS transistor.
14. A memory device comprising:
a high voltage multiplier module;
a level shifter circuit configured to provide a high voltage at an output node; and
an inverter circuit having an input node coupled to the output node, at least one of the level shifter circuit and the inverter circuits including:
a first NMOS transistor having an associated parasitic bipolar transistor, a source node of the first NMOS transistor being coupled to an output node of an auxiliary circuit, the auxiliary circuit being configured to provide a bias potential at the source node of the first NMOS transistor when the first NMOS transistor is in a non-conducting state (OFF), the bias potential preventing the associated parasitic bipolar transistor from turning on; and
a second NMOS transistor in series with the first NMOS transistor, a drain node of the second NMOS transistor being coupled to an output node and a source node of the second NMOS transistor being coupled to a drain node of the first NMOS transistor, a gate node of the second NMOS transistor being coupled to a bias node, such that that the second NMOS transistor is in conductive (ON) state.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

What is claimed is:

1. A method of manufacturing a hybrid integrated circuit device comprising the steps of:
preparing a hybrid integrated circuit substrate having circuit elements electrically connected through conductor patterns;
fixing conductor member extended as an input or output to an outside onto desired conductors pattern by a solder;
fixing the position of the hybrid integrated circuit substrate by clamping and fixing the conductor means by upper and lower mold dies; and
integrally molding the hybrid integrated circuit substrate by transfer molding using a thermosetting resin.
2. The method of manufacturing a hybrid integrated circuit device according to claim 1, wherein the conductor member is a plurality of leads.
3. The method of manufacturing a hybrid integrated circuit device according to claim 2, wherein each of the plurality of leads is connected each other at least two connection portions, the leads being held as one leadframe until completing the step of molding.
4. The method of manufacturing a hybrid integrated circuit device according to claim 3, wherein the leadframe has a first connection portion at an extension outer end of the lead, and a second connection portion in a portion to be abutted against the upper and lower mold dies during molding.
5. The method of manufacturing a hybrid integrated circuit device according to claim 3, wherein, in the step of molding, the leadframe is abutted at lengthwise and widthwise sides against guide pins provided on the mold die to thereby fix the position of the hybrid integrated circuit substrate.
6. The method of manufacturing a hybrid integrated circuit device according to claim 4, wherein the second connection portion is to be removed away after completing the step of molding.
7. The method of manufacturing a hybrid integrated circuit device according to claim 5, wherein a spacing between the leads of the leadframe to be abutted against the guide pins is constant regardless of the number of leads extended from the hybrid integrated circuit substrate.
8. The method of manufacturing a hybrid integrated circuit device according to claim 4, wherein, in the step of molding, the second connection portion is abutted against the upper and lower dies to thereby prevent thermosetting resin from leaking to an outside.
9. The method of manufacturing a hybrid integrated circuit device according to claim 3, wherein the leadframe extends from opposite two sides of the hybrid integrated circuit substrate.

1. A semiconductor package, comprising:
a substrate having a first surface and a second surface opposite the first surface, the substrate having a set of bond wire studs on first bond pads formed on the second surface thereof;
a first semiconductor chip having a first surface and a second surface opposite the first surface, wherein the first surface of the first semiconductor chip is mounted to the second surface of the substrate by means of solder bumps;
an underfill material disposed between the first semiconductor chip and the substrate, encapsulating the solder bumps;
a second semiconductor chip having a first surface and a second surface opposite the first surface, wherein the first surface of the second semiconductor chip is mounted to the second surface of the first semiconductor chip; and
a set of bond wires electrically coupled from the second semiconductor chip to the set of bond wire studs on the substrate through second bond pads between the bond wire and the wire studs.
2. The semiconductor package of claim 1, wherein the underfill material fills into the gap between the first semiconductor chip and the substrate through capillary action, and further wherein the underfill material does not flow over andor overlap the top surfaces of the set of bond wire studs.
3. The semiconductor package of claim 1, wherein the first surface of the second semiconductor chip is mounted to the second surface of the first semiconductor chip by means of an adhesive.
4. The semiconductor package of claim 1, wherein a space between an edge of the first semiconductor chip and one of the set of bond wire studs of the substrate is about 0.1 mm to about 0.2 mm.
5. The semiconductor package of claim 1, wherein a height of one of the set of bond wire studs is between about 10 \u03bcm to about 30 \u03bcm high.
6. The semiconductor package of claim 1, further comprising an encapsulant that encapsulates the first and second semiconductor chips, the set of bond wires, and the set of bond wire studs.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. Hydrokinetic coupling device (10), for a motor vehicle, which comprises an axis of rotation (B) and also:
a driven shaft mounted to rotate around the axis of rotation (B);
a torque converter (12) comprising a turbine wheel (22) mounted to rotate around the axis of rotation (B);
a circumferential damper device (40) comprising a damper plate (42) with a radial flange (44), rotationally linked without any play to the turbine wheel (22) by a connecting element (62) on the one hand, and which is rotationally linked with the rotary driven shaft with circumferential damping on the other;
a locking clutch (14), comprising at least one annular, axially sliding friction disc (56A, 56B), which rotates together with the flange (44) of the damper plate (42), wherein the friction disc (56A, 56B) is carried by the connecting element (62), which directly links the turbine wheel (22) to the flange (44) of the damper plate (42).
2. Device (10) according to claim 1, wherein the connecting element is formed by an annular skirt (62) of the damper plate (42), which extends axially from the outer radial edge of the flange (44) as far as a free end section (84), which is fixed to a mounting face (31) of the turbine wheel (22) and wherein the friction disc (56A, 56B) is carried by an outer axial face (60) of the annular skirt (62) of the damper plate (42).
3. Device (10) according claim 2, wherein the friction disc (56A, 56B) comprises radial guide teeth (58), which extend radially inwards from their inner peripheral edge and which are received in an axial flow in associated axial channels (60) formed in the outer axial face of the skirt (22).
4. Device (10) according to claim 2, wherein the flange (44) and the skirt (62) are formed from a single piece.
5. Device (10) according to claim 2, wherein the skirt (62) is a separate piece, which is attached to the flange (44) of the damper plate (42).
6. Device (10) according to claim 5, wherein the skirt (62) is linked rotationally to the flange (44) by the mutual meshing of a toothed axial end side (88) of the skirt (62) and a toothed outer peripheral edge (90) of the flange (44).
7. Device (10) according to claim 2, wherein the free end section (84) of the skirt (62) is fixed to the mounting face (31) of the turbine wheel (22) in a leak-proof manner in respect of a fluid contained in the device (10).
8. Device (10) according to claim 7, wherein the free end section (84) of the skirt (62) is fixed to the mounting face (81) of the turbine wheel (22) by welding.
9. Device (10) according to claim 1, wherein the damper plate (42) is rotationally linked to the rotary driven shaft by means of at least one elastic member (54) with circumferential action, and wherein the elastic member (54) is carried by guide washers (48) fitted axially on both sides of the flange (44) of the damper plate (42) and rotationally linked without play to the rotary driven shaft by means of a first central damper hub (50).
10. Device (10) according to claim 9, wherein the turbine wheel (22) comprises a second turbine hub (32) which is rotationally mounted on a bearing surface (55) of the first damper hub (50).