All The Claims

1. An adjusting device for a pneumatic disc brake having a rotary-lever-actuated brake application device, the adjusting device being insertable into an adjusting spindle of the brake application device, comprising:
a drive ring;
an axial bearing arranged axially on a drive input side of the drive ring, the axial bearing being formed in part from a drive input side portion of the drive ring;
a ball ramp clutch with a freewheel function arranged axially on a drive output side of the drive ring, wherein the ball ramp clutch comprises balls of the ball ramp clutch arranged axially between a drive bush formed in part by a drive output side portion of the drive ring on a drive input side of the ball ramp clutch and a clutch ring on a drive output side of the ball ramp clutch;
a spring sleeve for a cylindrical spring; and
a cone clutch arranged between the ball ramp clutch and the spring sleeve, wherein the cone clutch comprises clamping balls arranged between a tapered bush connected to the spring sleeve having axially-extending ball grooves configured to receive the clamping balls on a drive input side of the tapered bush and an opposing surface of a drive output side portion of the clutch ring.
2. The adjusting device according to claim 1, wherein the tapered bush has an external profile corresponding to an internal profile of the spring sleeve to provide a rotationally conjoint connection.
3. The adjusting device according to claim 1, wherein the tapered bush and the spring sleeve are integrally formed.
4. The adjusting device according to claim 1, wherein the axial bearing includes rolling bodies and a collar of a collar bush extending axially through the ball ramp clutch.
5. The adjusting device according to claim 4, wherein one end of the collar bush extending through the ball ramp clutch forms an axial stop for the tapered bush.
6. The adjusting device according to claim 5, wherein the axial stop is formed one of directly or via a thrust washer.
7. A pneumatic disc brake, comprising:
a caliper;
a wear adjustor for adjusting wear of brake pads and a brake disc of the disc brake;
a rotary lever actuated brake application device arranged in the caliper, the wear adjustor being arranged in an adjusting spindle of the brake application device; and
wherein the wear adjustor comprises:
a drive ring;
an axial bearing arranged axially on a drive input side of the drive ring, the axial bearing being formed in part from a drive input side portion of the drive ring
a ball ramp clutch with a freewheel function arranged axially on a drive output side of the drive ring, wherein the ball ramp clutch comprises balls of the ball ramp clutch arranged axially between a drive bush formed in part by a drive output side portion of the drive ring on a drive input side of the ball ramp clutch and a clutch ring on a drive output side of the ball ramp clutch;
a spring sleeve for a cylindrical spring; and
a cone clutch arranged between the ball ramp clutch and the spring sleeve, wherein the cone clutch comprises clamping balls arranged between a tapered bush connected to the spring sleeve having axially-extending balls on a drive input side of the tapered bush and an opposing surface of a drive output side portion of the clutch ring.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A receiver comprising:
an edge detector to detect a first falling edge and a first rising edge of an input signal received from a transmitter;
a counter to count in a first direction in response to detecting the first falling edge, and to count in a second direction in response to detecting the first rising edge of the input signal, the counter to generate a final count value based on the counts in the first and second directions; and
a decision unit to determine whether data in the input signal is of logical high or logical low value, the determination made according to the final count value.
2. The receiver of claim 1 further comprises:
an over-sampler, coupled to the counter, to generate an over-sampled clock signal for the counter.
3. The receiver of claim 2, wherein the over-sampler is operable to generate the over-sampled clock signal by generating pulse signals at the rising and falling edges of an input clock signal.
4. The receiver of claim 3 further comprises a flip-flop or a latch to latch an output of the decision unit by one of the rising or falling edges of the input clock signal.
5. The receiver of claim 1, wherein the input signal is a pulse width modulated (PWM) signal.
6. The receiver of claim 1, wherein the transmitter is a MIPI\xae M-PHYSM transmitter.
7. The receiver of claim 1, wherein the first direction is different from the second direction.
8. The receiver of claim 1, wherein the first direction is same as the second direction.
9. A system comprising:
a receiver, coupled to a transmitter, the receiver comprises:
an edge detector to detect a first falling edge and a first rising edge of an input signal received from the transmitter;
a counter to count in a first direction in response to detecting the first falling edge, and to count in a second direction in response to detecting the first rising edge of the input signal, the counter to generate a final count value based on the counts in the first and second directions; and
a decision unit to determine whether data in the input signal is of logical high or logical low value, the determination made according to the final count value; and

a display unit to display a version of the data.
10. The system of claim 9, wherein the display unit is a touch pad.
11. The system of claim 9, wherein the receiver further comprises:
an over-sampler, coupled to the counter, to generate an over-sampled clock signal for the counter.
12. The system of claim 11, wherein over-sampler is operable to generate the over-sampled clock signal by generating pulse signals at the rising and falling edges of an input clock signal.
13. The system of claim 9, wherein the receiver further comprises a flip-flop or a latch to latch an output of the decision unit by one of the rising or falling edges of the input clock signal.
14. The system of claim 9, wherein the input signal is a pulse width modulated (PWM) signal.
15. The system of claim 9, wherein the receiver and the transmitter are a MIPI\xae M-PHYSM receiver and transmitter.
16. The system of claim 9, wherein the first direction is different from the second direction.
17. The system of claim 9, wherein the first direction is same as the second direction.
18. A method comprising:
receiving an input signal from a transmitter;
identifying a first falling edge and a first rising edge of the input signal;
counting, by a counter, in a first direction in response to identifying the first falling edge, and counting in a second direction in response to identifying the first rising edge of the input signal;
storing count value in response to identifying a second falling edge of the input signal, the second falling edge occurring in time after the first falling edge; and
determining whether data in the input signal is of logical high or logical low value, the determining is made according to the stored count value.
19. The method of claim 18 further comprises:
resetting the counter in response to identifying the first falling edge;
sending previous data for processing in response to resetting the counter; and
generating an over-sampled clock signal for the counter, the counter to count on every rising or falling edge of the over-sampled clock signal.
20. (canceled)
21. The method of claim 18, wherein the first direction is different from the second direction, or wherein the first direction is same as the second direction.
22. (canceled)
23. (canceled)
24. (canceled)

1. A method of generating an output symbol, wherein the output symbol is selected from an output alphabet and the output symbol is such that an input file, comprising an ordered plurality of input symbols each selected from an input alphabet, is recoverable from a set of such output symbols, the method comprising:
calculating, according to a predetermined function, a list AL for each output symbol to be output, wherein AL is an indication of weights W associated input symbols associated with the output symbol to be output, and wherein the weights W are positive integers that vary between at least two values and are greater than one for at least one list; and
generating an output symbol value B from a predetermined function of the associated input symbols indicated by AL for each output symbol to be output;
wherein the number of possible output symbols to be output is effectively unbounded such that the number of output symbols available given any expected signal to noise ratio can be larger than the number of input symbols in the plurality of input symbols.
2. The method of claim 1, further comprising:
obtaining a key I for each output symbol to be output, wherein I is unique for each output symbol to be output and the number of possible keys is much larger than the number of input symbols in the input file; and
wherein AL, W and B are calculated using I as an input.
3. The method of claim 2, wherein obtaining key I comprises calculating key I according to a random function or pseudorandom function.
4. The method of claim 2, wherein calculating comprises calculating W(I) according to a random function or pseudorandom function of I.
5. The method of claim 2, wherein calculating comprises calculating AL(I) according to a random function or pseudorandom function of I.
6. The method of claim 2, wherein each subsequent key I is one greater than the preceding key.
7. The method of claim 2, wherein calculating comprises:
calculating, according to a predetermined function of I and a probability distribution, a weight W(I), wherein the probability distribution is over at least two positive integers, at least one of which is greater than one;
calculating a list entry for list AL(I); and
repeating the step of calculating a list entry for list AL(I) until W(I) list entries are calculated.
8. The method of claim 7, wherein calculating W(I) comprises determining W(I) such that W approximates a predetermined distribution over the key alphabet.
9. The method of claim 8, wherein the predetermined distribution is a uniform distribution.
10. The method of claim 8, wherein the predetermined distribution is a bell curve distribution.
11. The method of claim 8, wherein the predetermined distribution is such that W=1 has a probability of 1K, where K is the number of input symbols in the input file, and W=i has a probability of 1i(i\u22121) for i=2, . . . K.
12. The method of claim 8, wherein the predetermined distribution is such that, given tunable parameters R1 and R2 and K being the number of input symbols in the input file, weight W=1 has a probability proportional to R1K, weights in a low-weight class ranging from weight W=2 to weight W=KR2\u22121 have a probability proportional to 1(W(W\u22121)(1\u2212W R2K)) and weights in a high-weight class ranging from weight W=KR2 to weight W=K have a selected probability distribution.
13. The method of claim 1, wherein the predetermined function of the associated input symbols indicated by AL is an exclusive OR (XOR) of the input symbols indicated by AL.
14. The method of claim 1, wherein the input alphabet and the output alphabet are the same alphabet.
15. The method of claim 1, wherein the input alphabet comprises 2Mi symbols and each input symbol encodes Mi bits and wherein the output alphabet comprises 2Mo symbols and each output symbol encodes Mo bits.
16. The method of claim 1, wherein calculating AL comprises:
identifying the number K of input symbols in the input file, at least approximately and a weight W;
determining the smallest prime number P greater than or equal to K;
if P is greater than K, at least logically padding the input file with P\u2212K padding input symbols;
generating a first integer X such that 1\u2266X<P and a second integer Y such that 0\u2266Y<P;
setting the J-th entry in AL to ((Y+(J\u22121)\xb7X) mod P) for each J from 1 to W.
17. The method of claim 16, wherein setting the J-th entry in AL for each J comprises:
setting the first entry VJ=0 in an array V to Y;
setting the J-th entry VJ in the array V to (VJ\u22121+X) mod P) for each J from 1 to W minus one; and
using the array V as the list AL.
18. The method of claim 1, further comprising:
repeating steps for generating a plurality output symbols;
generating a key I for each of the output symbols to be generated; and
outputting each of the generated output symbols as an output sequence to be transmitted through a data erasure channel.
19. The method of claim 18, wherein each key I is selected independently of other selected keys.
20. A method of generating an output symbol, wherein the output symbol is selected from an output alphabet and the output symbol is such that an input file, comprising an ordered plurality of input symbols each selected from an input alphabet, is recoverable from a set of such output symbols, the method comprising:
calculating, according to a predetermined function, a list AL for each output symbol to be output, wherein AL is an indication of weights W associated input symbols associated with the output symbol to be output, and wherein the weights W are positive integers that vary between at least two values and are greater than one for at least one list; and
generating an output symbol value B from a predetermined function of the associated input symbols indicated by AL for each output symbol to be output; wherein the number of possible output symbols is effectively unbounded such that the number of output symbols available given any expected loss rate of a communication medium can be greater than the number of input symbols in the plurality of input symbols.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. In a system for addressing and sustaining a surface discharge AC plasma display panel wherein an addressing voltage is applied to at least one section of S1 of the display panel while at least one other section S2 of the panel is being simultaneously sustained,
the improvement wherein a reset voltage is simultaneously applied to at least one section S2 of the display panel while an addressing voltage is simultaneously applied to at least one other section S1 of the panel, each of the sections S1 and S2 being sustained with a different number of sustains per subfield, the number of subfields being 12 to 17.
2. The invention of claim 1 wherein the period of said reset in said section is long enough to allow addressing of said at least one other section followed by sustaining in said at least one other section.
3. The invention of claim 1 wherein section S2 is subsequently addressed while section S1 is simultaneously sustained.
4. The invention of claim 1 wherein the resolution of the plasma display is about 480 to about 1200 row scan electrodes.
5. The invention of claim 1 wherein the reset comprises a ramp voltage with a positive or negative slope so as to provide a uniform wall charge at all pixels in the PDP.
6. The invention of claim 1 wherein the reset comprises a ramp voltage that has a slow rise time such that the background glow from off-pixels is less visible.
7. The invention of claim 6 wherein the reset ramp voltage has a rise time of about 2 to about 8 volts per microsecond.
8. The invention of claim 6 wherein the reset ramp voltage has a rise time below 2 volts per microsecond.
9. The invention of claim 6 wherein the reset ramp voltage has a rise time of about 1 to about 1.5 volts per microsecond.
10. The invention of claim 1 wherein there are 12 to 17 subfields for a resolution up to about 768 row scan electrodes.
11. A surface discharge AC plasma display panel and electronic circuitry for applying a reset voltage to at least one section of S1 of the panel while simultaneously applying an address voltage to at least one other section S2 of the panel, each of the sections S1 and S2 being sustained with a different number of sustains per subfield, the number of subfields being 12 to 17.
12. The invention of claim 11 wherein the period of the reset voltage is long enough to allow addressing of said other section S2 followed by sustaining in said other section S2.
13. The invention of claim 11 wherein section S1 is subsequently addressed while section S2 is simultaneously sustained.
14. The invention of claim 11 wherein section S2 is subsequently addressed while section S1 is simultaneously sustained.
15. The invention of claim 11 wherein the resolution of the plasma display is about 480 to about 1200 row scan electrodes.
16. The invention of claim 11 wherein the reset comprises a ramp voltage with a positive or negative slope so as to provide a uniform wall charge at all pixels in the PDP.
17. The invention of claim 11 wherein the reset comprises a ramp voltage that has a slow rise time such that the background glow from off-pixels is less visible.
18. The invention of claim 17 wherein the reset ramp voltage has a rise time of about 2 to about 8 volts per microsecond.
19. The invention of claim 17 wherein the reset ramp voltage has a rise time below 2 volts per microsecond.
20. The invention of claim 17 wherein the reset ramp voltage has a rise time of about 1 to about 1.5 volts per microsecond.
21. The invention of claim 11 wherein there are 12 to 17 subfields for a resolution up to about 768 row scan electrodes.
22. In a system for addressing and sustaining a surface discharge AC plasma display panel wherein an addressing voltage is applied to at least one section of S1 of the display panel while at least one other section S2 of the panel is being simultaneously sustained,
the improvement wherein a reset voltage is simultaneously applied to at least one section S2 of the display panel while an addressing voltage is simultaneously applied to at least one other section S1 of the panel, each of the sections S1 and S2 being sustained with a same number of sustains per subfield, the number of subfields being 12 to 17.
23. The invention of claim 22 wherein the period of said reset in said section is long enough to allow addressing of said at least one other section followed by sustaining in said at least one other section.
24. The invention of claim 22 wherein section S2 is subsequently addressed while section S1 is simultaneously sustained.
25. The invention of claim 22 wherein the resolution of the plasma display is about 480 to about 1200 row scan electrodes.
26. The invention of claim 22 wherein there are 12 to 17 subfields for a resolution up to about 768 row scan electrodes.
27. The invention of claim 22 wherein the reset comprises a ramp voltage with a positive or negative slope so as to provide a uniform wall charge at all pixels in the PDP.
28. The invention of claim 22 wherein the reset comprises a ramp voltage that has a slow rise time such that the background glow from off-pixels is less visible.
29. The invention of claim 28 wherein the reset ramp voltage has a rise time of about 2 to about 8 volts per microsecond.
30. The invention of claim 28 wherein the reset ramp voltage has a rise time below 2 volts per microsecond.
31. The invention of claim 28 wherein the reset ramp voltage has a rise time of about 1 to about 1.5 volts per microsecond.
32. A surface discharge AC plasma display panel and electronic circuitry for applying a reset voltage to at least one section of S1 of the panel while simultaneously applying an address voltage to at least one other section S2 of the panel, each of the sections S1 and S2 being sustained with a same number of sustains per subfield, the number of subfields being 12 to 17.
33. The invention of claim 32 wherein the period of the reset voltage is long enough to allow addressing of said other section S2 followed by sustaining in said other section S2.
34. The invention of claim 32 wherein section S1 is subsequently addressed while section S2 is simultaneously sustained.
35. The invention of claim 32 wherein section S2 is subsequently addressed while section S1 is simultaneously sustained.
36. The invention of claim 32 wherein the resolution of the plasma display is about 480 to about 1200 row scan electrodes.
37. The invention of claim 32 wherein there are 12 to 17 subfields for a resolution up to about 768 row scan electrodes.
38. The invention of claim 32 wherein the reset comprises a ramp voltage with a positive or negative slope so as to provide a uniform wall charge at all pixels in the PDP.
39. The invention of claim 32 wherein the reset comprises a ramp voltage that has a slow rise time such that the background glow from off-pixels is less visible.
40. The invention of claim 39 wherein the reset ramp voltage has a rise time of about 2 to about 8 volts per microsecond.
41. The invention of claim 39 wherein the reset ramp voltage has a rise time below 2 volts per microsecond.
42. The invention of claim 39 wherein the reset ramp voltage has a rise time of about 1 to about 1.5 volts per microsecond.