All The Claims

1. A truck cargo box enclosure including a pair of support tracks adapted to mount to side rails of the cargo box, a plurality of flexible support rods for connecting to the support tracks, and a fabric siding including a U-shaped channel edge for engaging the support track on each side of the cargo box and adapted to connect to the support tracks and span the support rods in tension.
2. The truck cargo box enclosure of claim 1, wherein the flexible support rods are formed of multiple sections linked together.
3. The truck cargo box enclosure of claim 2, wherein the flexible support rods are longer than a width of the cargo box so as to describe an arch when connected to the support tracks.
4. The truck cargo box enclosure of claim 1, further including a door assembly for an end of the cargo box.
5. The truck cargo box enclosure of claim 4, wherein the door assembly is formed of fabric and integral with the fabric siding.
6. A cover adapted to enclose an open vehicle portion defined by a plurality of opposing wall sections, comprising:
a plurality of cover support tracks each adapted to attach to one of the plurality of opposing wall sections, each cover support track extending beyond an outer face of the wall section, and comprising a plurality of apertures and a depending flange;
a plurality of flexible support rods having an alignment tip and collar on each end; and
a fabric covering having a lateral edge comprising a channel section adapted to engage the depending flange of one of the pair of cover support tracks,
wherein the tips of the support rods are adapted to engage the apertures of support tracks on opposing wall sections, supported on the collars, to define a support framework, and the fabric covering is adapted to span at least a portion of the support framework in tension with the channel section engaging the depending flange.
7. The cover of claim 6, wherein the fabric covering comprises a second lateral edge comprising a second channel section, and wherein the channel sections are adapted to engage the depending flange of cover support tracks attached to opposing wall sections to draw the tent fabric in tension over the support rods.
8. The cover of claim 7, wherein the support rods are each formed of at least two sections removably connected.
9. A vehicle cargo box having a pair of parallel side rails and a cargo box cover comprising:
a cover support track affixed to each of the parallel side rails, each cover support track extending beyond an outer face of the side rail and having a depending lip;
a plurality of support rods engaging the cover support tracks to form a frame over the cargo box; and
a fabric cover spanning the frame and having lateral edges each comprising an inwardly directed U-shaped channel engaging the depending lip.
10. The vehicle cargo box of claim 9, wherein the cover support track further comprises a plurality of apertures and wherein the support rods are adapted to engage the apertures.
11. The vehicle cargo box of claim 10, wherein at least one of the plurality of support rods comprises a tip and a collar adapted to engage the support rod with an aperture.
12. The vehicle cargo box of claim 9, wherein the support rods are flexible and the frame describes an arch over the cargo box.
13. The vehicle cargo box of claim 12, wherein the fabric spans the frame in tension.
14. The vehicle cargo box of claim 9, wherein the fabric spans the frame in tension.
15. The vehicle cargo box of claim 9, wherein the support rods are formed of a plurality of connected sections.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A system for real time transmission of variable bit rate MPEG video traffic with consistent quality, comprising:
a video encoder for encoding video data;
an encoder buffer for storing encoded video data;
an encoder rate controller for estimating a number of bits quantized from a target quantization parameter during a frame of said video data corresponding to discrete cosine transform (DCT) coefficients of said frame, and for providing quantization parameters based on slice level to said encoder;
a channel rate controller for dynamically generating parameters for smoothing and bandwidth renegotiation corresponding to said number of bits generated from said encoder rate controller, wherein smoothing includes reducing a peak transmission rate to a sustainable transmission rate and smoothing a transmission rate to said sustainable transmission rate;
a network for generating negotiated parameters corresponding to said parameters generated from said channel rate controller; and
a counter for transmitting said video data stored in said encoder buffer through said network at a smoothed transmission rate, in response to said negotiated parameters.
2. The system of claim 1, wherein said channel rate controller generates the maximum number of bits capable of being generated and stored during said frame period corresponding to the negotiated parameters generated from said network.
3. The system of claim 2, wherein said channel rate controller determines an actual bit rate of said encoded video data transmitted to said network through the encoder buffer corresponding to the generated maximum number of bits.
4. The system of claim 3, wherein said channel rate controller is filled with bits to protect an underflow of said encoder buffer.
5. The system of claim 1, wherein said parameters for smoothing and bandwidth renegotiation generated from said channel rate controller comprise peak rate, sustainable rate, and maximum burst length.
6. The system of claim 2, wherein said encoder rate controller generates an actual number of bits quantized by the target quantization parameter during the frame corresponding to the maximum number of bits generated from the channel rate controller.
7. The system of claim 1, wherein the counter comprises a Leaky Bucket counter, wherein during the frame encoding period, the Leaky Bucket counter increases the number of bits and decreases the sustainable bits during the frame period.
8. The system of claim 1, wherein when said counter is full, the counter discards the data transferred from said encoder buffer.
9. The system of claim 1, wherein said network comprises an asynchronous transfer mode (ATM).
10. The system of claim 1, wherein said encoded video data comprises variable bit rate MPEG video data.
11. A method for transmission of variable bit rate MPEG video traffic with consistent quality, comprising the steps of:
encoding frames of video data and generating encoding information associated therewith;
estimating a number of bits quantized from a target quantization parameter during a given frame of said video data based on encoding information of the given frame;
estimating a maximum number of bits capable of being generated based on network traffic parameters and buffer sizes;
computing a target bit rate using the estimated number of bits quantized with the target quantization parameters and the estimated maximum number of bits;
generating quantization parameters to control the actual encoding rate, if necessary, so that a number of actual bits generated does not exceed the target bit rate; and
dynamically negotiating with a network to generate traffic parameters that are used for dynamically adjusting bandwidth and for dynamically smoothing a transmission rate, wherein a negotiated peak transmission rate is reduced to a sustainable transmission rate, and said transmission rate is smoothed to said sustainable transmission rate.
12. The method of claim 11, wherein the encoding information comprises DCT (discrete cosine transformation) coefficients.
13. The method of claim 11, wherein the step of generating quantization parameters to control the actual encoding rate comprises generating quantization parameters based on slice level.
14. The method of claim 11, wherein the traffic parameters comprise peak rate, sustainable rate and maximum burst length.
15. The method of claim 11, further comprising the step of protecting against an underflow in an encoder buffer by stuffing bits.
16. The method of claim 11, further comprising the step of generating the actual number of bits quantized by the target quantization parameter during the given frame corresponding to the estimated maximum number of bits.
17. A program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine to perform method steps for transmission of variable bit rate MPEG video traffic with consistent quality, the method steps comprising:
encoding frames of video data and generating encoding information associated therewith;
estimating a number of bits quantized from a target quantization parameter during a given frame of said video data based on encoding information of the given frame;
estimating a maximum number of bits capable of being generated based on network traffic parameters and buffer sizes;
computing a target bit rate using the estimated number of bits quantized with the target quantization parameters and the estimated maximum number of bits;
generating quantization parameters to control the actual encoding rate, if necessary, so that a number of actual bits generated does not exceed the target bit rate; and
dynamically negotiating with a network to generate traffic parameters that are used for dynamically adjusting bandwidth and for dynamically smoothing a transmission rate, wherein a negotiated peak transmission rate is reduced to a sustainable transmission rate, and said transmission rate is smoothed to said sustainable transmission rate.
18. The program storage device of claim 17, wherein the encoding information comprises DCT (discrete cosine transformation) coefficients.
19. The program storage device of claim 17, wherein the instructions for generating quantization parameters to control the actual encoding rate comprise instructions for generating quantization parameters based on slice level.
20. The program storage device of claim 17, wherein the traffic parameters comprise peak rate, sustainable rate and maximum burst length.
21. The program storage device of claim 17, further comprising instructions for performing the step of protecting against an underflow in an encoder buffer by stuffing bits.
22. The program storage device of claim 17, further comprising instructions for performing the step of generating the actual number of bits quantized by the target quantization parameter during the given frame corresponding to the estimated maximum number of bits.

1. A switching mode power supply operative in a normal mode and a measure mode, comprising:
an output stage; and
a controller for driving the output stage to produce an output voltage;
wherein the controller compensates the switching mode power supply with a first compensation factor in the measure mode so as to measure a frequency response of the switching mode power supply for determining a second compensation factor which is used to compensate the switching mode power supply in the normal mode.
2. The switching mode power supply of claim 1, wherein the controller has a feedback pin for receiving either a small signal voltage in the measure mode or a feedback signal derived from the output voltage in the normal mode to regulate the output voltage.
3. The switching mode power supply of claim 2, wherein the controller comprises:
an error amplifier for comparing a signal from the feedback pin with a reference voltage to produce an error signal;
a compensator for compensating the error signal with either the first compensation factor in the measure mode or the second compensation factor in the normal mode, so as to produce a compensated error signal; and
a pulse width modulator for driving the output stage according to the compensated error signal.
4. The switching mode power supply of claim 3, further comprising an analog-to-digital converter for digitizing the error signal.
5. The switching mode power supply of claim 3, wherein the compensator comprises:
a digital filter for filtering the error signal to produce a first signal;
an adder having a first input to receive the first signal and a second input to receive a second signal, so as to combine the first and second signals to produce a third signal; and
a multiplexer for selecting a forth signal to be the second signal in the normal mode and a fifth signal to be the second signal in the measure mode.
6. The switching mode power supply of claim 5, wherein the digital filter comprises a gain circuit for amplifying the error signal, the gain circuit having a first gain in the normal mode and a second gain in the measure mode.
7. The switching mode power supply of claim 2, wherein the controller comprises:
an error amplifier for comparing a signal from the feedback pin with a reference voltage to produce an error signal;
a first compensator for compensating the error signal with the first compensation factor in the measure mode to produce a first signal;
a second compensator for compensating the error signal with the second compensation factor in the normal mode to produce a second signal; and
a pulse width modulator for driving the output stage according to the first signal in the measure mode and the second signal in the normal mode.
8. The switching mode power supply of claim 7, further comprising an analog-to-digital converter for digitizing the error signal.
9. The switching mode power supply of claim 7, wherein the first compensator comprises:
a gain circuit for amplifying the error signal; and
an adder having a first input to receive the amplified error signal and a second input to receive a third signal, so as to combine the amplified error signal and the third signal to produce the first signal.
10. The switching mode power supply of claim 7, further comprising a multiplexer for connecting the first signal to the pulse width modulator in the measure mode and the second signal to the pulse width modulator in the normal mode.
11. The switching mode power supply of claim 1, wherein the controller comprises:
an error amplifier for comparing the output voltage with a reference voltage to produce an error signal;
an AC signal generator for providing a small signal voltage;
a first compensator for compensating the small signal voltage with the first compensation factor in the measure mode to produce a first signal;
a second compensator for compensating the error signal with the second compensation factor in the normal mode to produce a second signal;
a pulse width modulator for driving the output stage according to the first signal or the second signal; and
an analyzer for analyzing the small signal voltage and a third signal related to the error signal in the measure mode, to derive the frequency response for determining the second compensation factor.
12. The switching mode power supply of claim 11, further comprising a fast Fourier transformer for transforming the error signal to the third signal.
13. The switching mode power supply of claim 11, further comprising an analog-to-digital converter for digitizing the error signal.
14. The switching mode power supply of claim 11, further comprising a multiplexer for connecting the first signal to the pulse width modulator in the measure mode and the second signal to the pulse width modulator in the normal mode.
15. The switching mode power supply of claim 11, wherein the first compensator comprises:
a gain circuit for amplifying the small signal voltage; and
an adder having a first input to receive the amplified small signal voltage and a second input to receive a fourth signal, so as to combine the amplified small signal voltage and the fourth signal to produce the first signal.
16. A method for determining a compensation factor for a switching mode power supply operative in a normal mode and a measure mode, comprising the steps of:
switching the switching mode power supply to the measure mode;
providing a small signal voltage;
driving an output stage of the switching mode power supply according to the small signal voltage and a first compensation factor, for producing an output voltage; and
deriving a frequency response of the switching mode power supply from the output voltage for determining a second compensation factor which is used to compensate the switching mode power supply in the normal mode.
17. The method of claim 16, wherein the step of driving an output stage of the switching mode power supply according to the small signal voltage and a first compensation factor comprises the steps of:
comparing the small signal voltage with a reference voltage for producing an error signal;
compensating the error signal with the first compensation factor; and
driving the output stage according to the compensated error signal.
18. The method of claim 17, further comprising the step of digitizing the error signal before the step of compensating the error signal with the first compensation factor.
19. The method of claim 16, wherein the step of driving an output stage of the switching mode power supply according to the small signal voltage and a first compensation factor comprises the step of:
compensating the small signal voltage with the first compensation factor; and
driving the output stage according to the compensated small signal voltage.
20. The method of claim 16, wherein the step of deriving a frequency response of the switching mode power supply from the output voltage for determining a second compensation factor comprises the steps of:
comparing the small signal voltage with a reference voltage for producing an error signal;
fast Fourier transforming the error signal; and
analyzing the transformed error signal and the small signal voltage to derive the frequency response.
21. The method of claim 20, further comprising the step of digitizing the error signal before the step of fast Fourier transforming the error signal.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method comprising:
booting a computer system;
copying contents stored in a portion of a system programmable read-only memory (PROM) responsive to said booting;
storing a duplicate of the contents in a storage unit;
periodically comparing the contents stored in the portion of the system PROM with the duplicate of the contents in the storage unit;
performing a system alert if the contents stored in the portion of the system PROM are different from the contents in the storage unit, wherein performing a system alert includes deactivating of system shutdown commands.
2. The method as recited in claim 1, wherein the contents stored in the portion of the system PROM are static.
3. The method as recited in claim 2, wherein the system PROM includes a static portion and a dynamic portion.
4. The method as recited in claim 1, wherein the system PROM is a serial electrically erasable-programmable ROM (SEEPROM).
5. The method as recited in claim 1, wherein performing a system alert includes invoking an indication on a visual display.
6. The method as recited in claim 1, wherein performing a system alert includes providing an audio indication.
7. The method as recited in claim 1 further comprising writing the duplicate of the contents in the storage unit to the portion of the system PROM responsive to determining the contents stored in the portion of the system PROM are different from the contents in the storage unit.
8. The method as recited in claim 1, wherein the system PROM is mounted upon a system board.
9. The method as recited in claim 8, wherein the system board is a field replaceable unit (FRU).
10. The method as recited in claim 9, wherein the FRU is configured for plug-and-play.
11. A computer system comprising:
a system programmable read-only memory (PROM); and
a storage unit;
wherein the computer system is configured to, responsive to booting:
copy contents stored in a portion of the system PROM;
store a duplicate of the contents in the storage unit;
periodically compare the contents stored in the portion of the system PROM to the duplicate of the contents in the storage unit; and
perform a system alert if the contents stored in the portion of the system PROM are different from the duplicate of the contents in the storage unit, wherein performing a system alert includes deactivating of system shutdown commands.
12. The computer system as recited in claim 11, wherein the system PROM is a serial electrically erasable-programmable ROM (SEEPROM).
13. The computer system as recited in claim 11, wherein performing a system alert includes invoking an indication on a visual display.
14. The computer system as recited in claim 11, wherein performing a system alert includes providing an audio indication.
15. The computer system as recited in claim 11, wherein the system is configured to write the duplicate of the contents in the storage unit to the portion of the system PROM responsive to determining the contents stored in the portion of the system PROM are different from the contents in the storage unit.
16. The computer system as recited in claim 11, wherein the system PROM is mounted upon a system board.
17. The computer system as recited in claim 16, wherein the system board is a field replaceable unit (FRU).
18. The computer system as recited in claim 17, wherein the FRU is configured for plug-and-play.
19. The computer system as recited in claim 18, wherein the FRU is configured for hot-plugging.