All The Claims

1. A calibration system for a portable locator, comprising:
a frame for supporting a locator;
a pair of coil windings mounted on the frame for generating a substantially symmetrical electromagnetic field surrounding the locator when supported on the frame when the coil windings are energized with a predetermined signal generated by a transmitter;
a drive assembly for rotating the locator; and
an interface that enables a computer to sample field strength signals from the locator at different rotational positions of the locator.
2. A calibration system for a portable locator, comprising:
a frame for supporting a locator;
a pair of coil windings mounted on the frame for generating a symmetrical electromagnetic field surrounding the locator when supported on the frame when the coil windings are energized with a predetermined signal generated by a transmitter;
a drive assembly for rotating the locator; and
an interface that enables a computer to sample field strength signals from the locator at different rotational positions of the locator;
wherein the system is configured so that the computer can control the rotation of the drive assembly and store position signals generated by the drive assembly corresponding to the sampled field strength signals.
3. The calibration system of claim 1 wherein the coil windings are substantially matched Helmholtz coils.
4. The calibration system of claim 3 wherein the coil windings are each made of a single turn of Copper tape.
5. The calibration system of claim 1 wherein the support for the locator includes a mount that receives an antenna node of the locator.
6. The calibration system of claim 5 wherein the mount that supports the antenna node is rotated by the drive assembly.
7. The calibration system of claim 1 wherein the frame is made of non-metallic parts.
8. The calibration system of claim 1 wherein the mount is connected to the frame by a coupling that permits a vertical position of the locator with respect to the frame to be adjusted.
9. The calibration system of claim 1 wherein the drive assembly includes a drive motor and a rotary encoder assembly.
10. The calibration system of claim 1 wherein the interface includes a USB hub.
11. A calibration system for a portable locator, comprising:
means for supporting a portable locator;
means for generating an electromagnetic field around the locator; and
means for enabling a plurality of field strength samples to be extracted from the locator representing different angular andor vertical positional relationships of the locator and the electromagnetic field.
12. The calibration system of claim 11 wherein the field generating means includes a pair of matched Helmholtz coils.
13. The calibration system of claim 11 wherein the supporting means includes a mount that receives an antenna node of the locator.
14. The calibration system of claim 11 wherein the extracting means includes a computer interface.
15. The calibration system of claim 11 wherein the supporting means includes means mounted on the frame for rotating the locator.
16. The calibration system of claim 15 wherein the extracting means includes means connected to locator rotating means and the locator for sampling field strength signals from the locator at a plurality of different rotational positions of the locator relative to the electromagnetic field.
17. The calibration system of claim 11 wherein the supporting means includes means for raising and lowering the locator relative to the electromagnetic field.
18. The calibration system of claim 17 wherein the extracting means includes means for enabling field strength samples to be extracted from the locator at a plurality of different vertical positions of the locator relative to the electromagnetic field.
19. The calibration system of claim 11 and further comprising means connected to the extracting means for calculating corrective values and uploading the corrective values to the locator to thereby calibrate the locator.
20. A locator calibration system, comprising:
a frame that supports a portable locator;
at least one coil that generates an electromagnetic field around the locator when a suitable signal is applied to the coil;
a motor assembly capable of rotating the locator;
a sensor that outputs a signal representative of a rotational position of the locator relative to the magnetic field; and
a computer interface that enables a computer to sample a plurality of field strength samples from the locator at each of a plurality of different rotational positions of the locator, calculate at least one corrective value, and upload the corrective value to the locator to calibrate the locator.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

What is claimed is:

1. A semiconductor memory device having a semiconductor substrate, comprising:
a field oxide film which is formed to a forward taper shape on the semiconductor substrate, and
a floating gate which is formed to a reverse taper shape between the field oxide film over the semiconductor substrate,
wherein sidewall angle is less than 90 degrees in the forward taper shape while sidewall angle is more than 90 degrees in the reverse taper shape.
2. A device as claimed in claim 1, wherein:
a tunnel oxide film is formed between the floating gate and the semiconductor substrate.
3. A device as claimed in claim 1, wherein:
the semiconductor substrate comprises a p-type silicon substrate.
4. A device as claimed in claim 1, wherein:
the field oxide film has a thickness within a range between 300 nm and 500 nm.
5. A device as claimed in claim 1, wherein:
the tunnel oxide film has a thickness within a range between 8 nm and 10 nm.
6. A device as claimed in claim 1, wherein:
a word line is formed via an insulating film on the floating gate.
7. A device as claimed in claim 1, wherein:
the semiconductor memory device comprises a flash memory.
8. A method of manufacturing a semiconductor memory device on a semiconductor substrate, comprising the steps of:
depositing a first oxide film on the semiconductor substrate;
forming a field oxide film in the first oxide film such that a plurality of grooves extend in a predetermined direction and exposes the semiconductor substrate, the field oxide film having a forward taper shape;
depositing a second oxide film having on the exposed semiconductor substrate; and
forming a floating gate to a reverse taper shape between the field oxide film on the second oxide film,
wherein sidewall angle is less than 90 degrees in the forward taper shape while sidewall angle is more than 90 degrees in the reverse taper shape.
9. A method as claimed in claim 8, wherein:
the semiconductor substrate comprises a p-type silicon substrate.
10. A method as claimed in claim 8, wherein:
the first oxide film has a thickness within a range between 300 nm and 500 nm.
11. A method as claimed in claim 8, wherein:
the field oxide film is deposited by the use of anisotropic etching.
12. A method as claimed in claim 8, wherein:
the second oxide film comprises a tunnel oxide film formed by the use of a thermal oxidation method, and
the tunnel oxide film has a thickness within a range between 8 nm and 10 nm.
13. A method as claimed in claim 8, wherein:
the floating gate is formed by burying polysilicon in the groove with a film thickness of the field oxide film or thicker, and by removing the buried polysilicon with a predetermined film thickness.
14. A method as claimed in claim 13, wherein:
the polysilicon is buried by the use of a CVD method.
15. A method as claimed in claim 13, wherein:
the polysilicon is removed by the use of a CMP method.
16. A method as claimed in claim 13, wherein:
the polysilicon is removed by the use of a dry-etching method.
17. A method as claimed in claim 8, wherein:
the floating gate is formed in a self-alignment manner with the field oxide film.

1. A method of operating a processor, the method comprising:
fetching, by a fetcher instructions from an instruction source to provide an instruction stream that includes one or more fetched branch instructions;
storing, by a branch instruction queue having a plurality of entries, the one or more branch instructions from the instruction stream, wherein each of the one or more branch instructions occupies one of the entries, and wherein the recently stored one or more branch instructions is designated as valid, meaning that the branch instruction is in process;
in response to a branch instruction being stored in the branch instruction queue, dynamically pointing, by the branch instruction queue, a head pointer to a newest, valid, branch instruction stored in one of the entries, and dynamically pointing a tail pointer to an oldest, valid, branch instruction stored in one of the entries, such that any branch instructions positioned between the head pointer and the tail pointer are valid;
speculatively executing, by a branch execution unit, one or more fetched branch instructions by using branch prediction information and resolving whether or not a branch in the speculatively executed branch instruction is taken, thus providing one or more executed branch instructions;
designating as invalid the one or more executed branch instructions in the branch instruction queue and moving the tail pointer such that the tail pointer points to the oldest, valid, branch instruction stored in the branch instruction queue;
storing, by a confidence storage memory, a confidence value describing an amount of confidence in the branch prediction information for each fetched branch instruction stored in the branch instruction queue;
summing the confidence values of the branch instructions positioned from the head pointer to the tail pointer stored in the branch instruction queue, thus generating a confidence value total for valid branch instructions only;
throttling, by a throttle circuit, the fetching of instructions from the instruction source if the confidence value total indicates confidence less than a predetermined confidence threshold, wherein the throttling reduces power consumption by the processor; and
repeating the above steps.
2. The method of claim 1, wherein the throttling step further comprises instructing, by the throttle circuit, the fetcher to fetch instructions from the instruction source without throttling if the confidence value total does not indicate confidence less than the predetermined confidence threshold.
3. The method of claim 1, further comprising generating, by a valid vector generation circuit, a valid vector that identifies valid and invalid fetched branch instructions stored in the branch instruction queue.
4. The method of claim 3, further comprising logically ANDing, by an AND circuit, the valid vector with the confidence values of each branch instruction currently in the branch instruction queue to obtain a valid confidence value for each valid branch instruction.
5. The method of claim 1, wherein the throttling step comprises:
comparing, by a comparator, the confidence value total with the predetermined threshold; and
reducing, by a fetch throttle state machine, a rate of fetching instructions from the instruction source by the fetcher if the comparator determines that the confidence value total exceeds the predetermined threshold, the fetch throttle state machine otherwise allowing fetching of instructions by the fetcher from the instruction source at full speed.
6. The method of claim 1, wherein the predetermined threshold is a programmable threshold.
7. A processor comprising:
an instruction source that stores instructions;
a fetcher coupled to the instruction source, that fetches instructions from the instruction source to provide an instruction stream that includes one or more fetched branch instructions;
a branch execution unit, coupled to the fetcher that speculatively executes one or more of the fetched branch instructions by using branch prediction information and that resolves whether or not a branch in the speculatively executed branch instruction is taken, thus providing one or more executed branch instructions; and
a throttle controller, coupled to the fetcher capable of throttling the fetching of instructions by the fetcher the throttle controller including:
a branch instruction queue, having a plurality of entries, that stores the one or more fetched branch instructions from the instruction stream, wherein each of the one or more branch instructions occupies one of the entries, and wherein the recently stored one or more branch instructions is designated as valid, meaning that the branch instruction is still in process;
the branch instruction queue having a head pointer for dynamically pointing to a newest, valid, branch instruction in response to a branch instruction being stored in the branch instruction queue, and a tail pointer dynamically pointing to an oldest, valid, branch instruction stored in the branch instruction queue, such that any branch instructions positioned between the head pointer and the tail pointer are valid;
a valid vector for designating as invalid the one or more executed branch instructions in the branch instruction queue;
the branch instruction queue for moving the tail pointer such that the tail pointer points to the oldest, valid, branch instruction stored in the branch instruction queue;
a confidence storage memory that stores a confidence value describing an amount of confidence in the branch prediction information for each fetched branch instruction stored in the branch instruction queue;
an adder for summing the confidence values of the branch instruction positioned from the head pointer to the tail pointer stored in the branch instruction queue, thus generating a confidence value total for valid branch instructions only; and
the throttle controller throttling the fetching of instructions from the instruction source if the confidence value total indicates confidence less than a predetermined confidence threshold, wherein the throttling reduces power consumption by the processor.
8. The processor of claim 7, wherein the throttle controller instructs the fetcher to fetch instructions from the instruction source without throttling if the confidence value total does not indicate confidence less than the predetermined confidence threshold.
9. The processor of claim 7, further comprising a valid vector generation circuit that generates the valid vector that identifies valid and invalid fetched branch instructions stored in the branch instruction queue.
10. The processor of claim 9, further comprising an AND circuit, coupled to the confidence storage memory and the valid vector generation circuit that logically ANDs the valid vector with the confidence values of each branch instruction currently in the branch instruction queue to obtain a valid confidence value for each valid branch instruction.
11. An information handling system (IHS), the IHS comprising:
a memory;
a processor coupled to the memory, the processor including:
an instruction source that stores instructions, the instruction source being coupled to the memory;
a fetcher coupled to the instruction source, that fetches instructions from the instruction source to provide an instruction stream that includes one or more fetched branch instructions;
a branch execution unit, coupled to the fetcher that speculatively executes one or more of the fetched branch instructions by using branch prediction information and that resolves whether or not a branch in the speculatively executed branch instruction is taken, thus providing one or more executed branch instructions; and
a throttle controller, coupled to the fetcher capable of throttling the fetching of instructions by the fetcher the throttle controller including:
a branch instruction queue, having a plurality of entries, that stores the one or more fetched branch instructions from the instruction stream, wherein each of the one or more branch instructions occupies one of the entries, and wherein the recently stored one or more branch instructions is designated as valid, meaning that the branch instruction is still in process;
the branch instruction queue having a head pointer for dynamically pointing to a newest, valid, branch instruction in response to a branch instruction being stored in one of the entries, and a tail pointer for dynamically pointing to an oldest, valid, branch instruction stored in one of the entries, such that any branch instructions positioned between the head pointer and the tail pointer are valid;
a valid vector for designating as invalid the one or more executed branch instructions in the entries of the branch instruction queue;
the branch instruction queue for moving the tail pointer such that the tail pointer points to the oldest, valid, branch instruction stored in the entries of the branch instruction queue;
a confidence storage memory that stores a respective confidence value for each of the fetched branch instruction in the branch instruction queue, the confidence values describing a lack of confidence in the branch prediction information for respective fetched branch instructions in the branch instruction queue;
an adder for summing the confidence value of the branch instructions positioned from the head pointer to the tail pointer stored in the branch instruction queue, thus generation a confidence value total for valid branch instructions only; and
the throttle controller throttling the fetching of instructions from the instruction source if the confidence value total in the confidence storage memory exceeds a predetermined threshold, wherein the throttling reduces power consumption by the processor.
12. The IHS of claim 11, wherein the processor includes a valid vector generation circuit that generates a valid vector that identifies valid and invalid fetched branch instructions stored in the branch instruction queue.
13. The IHS of claim 12, wherein the processor includes an AND circuit, coupled to the confidence storage memory and the valid vector generation circuit that logically ANDs the valid vector with the confidence values of each branch instruction currently in the branch instruction queue to obtain a valid confidence value for each valid branch instruction.
14. The IHS of claim 13, wherein the adder is an adder circuit, coupled to the AND circuit, that adds the valid confidence values to obtain the confidence value total stored in the confidence storage memory.
15. The IHS of claim 14 wherein the processor includes a comparator, coupled to the adder circuit and a threshold circuit, that compares the confidence value total with the predetermined threshold that the threshold circuit provides.
16. The IHS of claim 15, wherein the processor includes a fetch throttle state machine, coupled to the comparator and the fetcher the fetch throttle state machine reducing a rate of fetching instructions by the fetcher from the instruction source if the comparator determines that the confidence value total exceeds the predetermined threshold, the fetch throttle state machine otherwise allowing fetching of instructions by the fetcher from the instruction source at full speed.
17. The IHS of claim 16, wherein the processor includes a programmable threshold circuit that provides the predetermined threshold.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A function performing apparatus comprising:
a function performing unit configured to perform a specific function;
an operation unit configured to be operated by a user;
a processor; and
memory storing computer-readable instructions therein, the computer-readable instructions, when executed by the processor, causing the function performing apparatus to perform:
receiving a first instruction for registering first authentication information from a portable device,
in a case where the first instruction is received, determining, based on a registration condition designated by an administrator, whether the first authentication information for the portable device is to be registered in an authentication memory,
registering the first authentication information in the authentication memory when determined that the first authentication information is to be registered in the authentication memory,
transmitting the first authentication information when determined that the first authentication information is to be registered in the authentication memory,
receiving a second instruction including the first authentication information from the portable device,
in a case where the second instruction is received while the first authentication information is registered in the authentication memory, changing a state of the function performing apparatus from a non-permission state where use of the specific function is not permitted to a permission state where the use of the specific function is permitted, and
in a case where the operation unit is operated by a user and second authentication information different from the first authentication information is input to the function performing apparatus while the second authentication information is registered in the authentication memory, changing the state of the function performing apparatus from the non-permission state to the permission state.
2. The function performing apparatus according to claim 1,
wherein the determining comprises:
transmitting a request for registration of the first authentication information in the authentication memory to a registration management apparatus which is used by the administrator,
receiving a request result from the registration management apparatus in response to the request, and
in a case where the request result included in the registration condition indicates that the registration of the first authentication information is permitted, determining that the first authentication information is to be registered in the authentication memory.
3. The function performing apparatus according to claim 1,
wherein the computer-readable instructions, when executed by the processor, causing the function performing apparatus to further perform:
receiving use condition information, which indicates a use condition for using the specific function, from the portable device, and

wherein the determining is performed, based on the use condition information, whether the first authentication information is to be registered in the authentication memory.
4. The function performing apparatus according to claim 1,
wherein the computer-readable instructions, when executed by the processor, causing the function performing apparatus to further perform:
storing permission condition information, which indicates a permission condition for permitting use of the specific function, in the memory, and
receiving use condition information, which indicates a use condition for using the specific function, from the portable device, and

wherein in a case where the use condition indicated by the use condition information meets the permission condition included in the registration condition, the determining is performed to determine that the first authentication information is to be registered in the authentication memory.
5. The function performing apparatus according to claim 4,
wherein the determining comprises:
in a case where the use condition does not meet the permission condition,
transmitting a request for registration of the first authentication information in the authentication memory to a registration management apparatus which is used by the administrator, the request including the use condition information,
receiving a request result from the registration management apparatus in response to the request, and
in a case where the request result included in the registration condition indicates that registration of the first authentication information is permitted, determining that the first authentication information is to be registered in the authentication memory.
6. The function performing apparatus according to claim 5, further comprising:
a first interface configured to perform communication according to a first communication method; and
a second interface configured to perform communication according to a second communication method different from the first communication method,
wherein the computer-readable instructions, when executed by the processor, causing the function performing apparatus to further perform:
receiving an email address from the portable device by performing communication using the first interface,

wherein the receiving of the first instruction is performed by performing communication with the portable device using the first interface,
wherein in a case where determined that the first authentication information is to be registered in the authentication memory based on that the use condition indicated by the use condition information meets the permission condition indicated by the permission condition information, the transmitting of the first authentication information is performed to the portable device by performing communication using the first interface, and
wherein in a case where determined that the first authentication information is to be registered in the authentication memory based on that the request result indicates that registration of the first authentication information is permitted, the transmitting of the first authentication information is performed to transmit an email including the first authentication information to the email address received from the portable device by performing communication using the second interface.
7. The function performing apparatus according to claim 1,
wherein the computer-readable instructions, when executed by the processor, causing the function performing apparatus to further perform:
generating the first authentication information, and

wherein the registering of the generated first authentication information is performed.
8. The function performing apparatus according to claim 1, further comprising:
a first interface configured to operate in any one of a plurality of modes including a first mode and a second mode and to establish a connection with the portable device, thereby performing communication according to a first communication method,
wherein the first instruction is received in a case where the first interface operates in the first mode when the connection with the portable device is established, and
wherein the second instruction is received in a case where the first interface operates in the second mode when the connection with the portable device is established.
9. The function performing apparatus according to claim 1,
wherein the memory include the authentication memory.
10. The function performing apparatus according to claim 1,
wherein the determining is performed to determine whether the first authentication information is to be registered in the authentication memory of a specific device, and
wherein the registering of the first authentication information is performed in the authentication memory of the specific device.
11. A non-transitory computer-readable storage medium storing computer-readable instructions, when executed by the computer, causing a function performing apparatus to perform:
receiving a first instruction for registering first authentication information from a portable device,
in a case where the first instruction is received, determining, based on a registration condition designated by an administrator, whether the first authentication information for the portable device is to be registered in an authentication memory,
registering the first authentication information in the authentication memory when determined that the first authentication information is to be registered in the authentication memory,
transmitting the first authentication information when determined that the first authentication information is to be registered in the authentication memory,
receiving a second instruction including the first authentication information from the portable device, and
in a case where the second instruction is received while the first authentication information is registered in the authentication memory, changing a state of the function performing apparatus from a non-permission state where use of a specific function, which is performed by a function performing unit of the function performing apparatus, is not permitted to a permission state where the use of the specific function is permitted, and
in a case where an operation unit of the function performing apparatus is operated by a user and second authentication information different from the first authentication information is input to the function performing apparatus while the second authentication information is registered in the authentication memory, changing the state of the function performing apparatus from the non-permission state to the permission state.