All The Claims

1. A process for producing an electrophoretic display of the type wherein a dispersion liquid for migration and a plurality of charged particles are sandwiched between a first substrate and a second substrate, said process comprising:
a latent image forming step of forming an electrostatic latent image on an adsorption member,
a developing step of causing the adsorption member to contact the dispersion liquid in which the charged particles are dispersed, thereby to attach the charged particles together with the dispersion liquid onto a surface of the adsorption member on which the latent image is formed,
a transfer step of transferring the charged particles from the surface of the adsorption member to the second substrate together with the dispersion liquid, and
a sealing step of bonding the first substrate to the second substrate to seal the charged particles and the dispersion liquid, therebetween.
2. A process according to claim 1, wherein the dispersion liquid contains an ultraviolet curable resin, and said process further comprises an irradiation step of irradiating the ultraviolet curable resin with ultraviolet rays after said transfer step.
3. A process according to claim 2, wherein said latent image forming step, said developing step, said transfer step, and said irradiation step were repeated for each color of charged particles different in color.
4. A process according to claim 1, wherein said developing step is a step of adsorbing only charged particles having an electric charge amount larger than a predetermined electric charge amount, from the charged particles in the dispersion liquid.
5. A process according to claim 1, wherein before said transfer step, the surface of the second substrate is electrically charged to a polarity identical to that of the surface of the adsorption member.
6. A process according to claim 1, wherein the surface of the second substrate and the surface of the adsorption member have an identical wettability to the dispersion liquid.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A common electrode substrate comprising:
a transparent insulating substrate to be arranged opposite to an array substrate having pixel electrodes formed in respective pixel regions that are defined by a plurality of gate bus lines and drain bus lines, and to hold a liquid crystal having negative dielectric anisotropy;
a common electrode formed on the transparent insulating substrate;
alignment regulating structures having linear protrusions formed on the common electrode; and
a light shield film formed on the transparent insulating substrate and having overlap regions that overlap the pixel electrodes when viewed in a direction perpendicular to a surface of the transparent insulating substrate so as to shield, from light, alignment defective regions of the liquid crystal formed in regions of end portions of the pixel electrodes.
2. The common electrode substrate according to claim 1, wherein the light shield film has the overlap regions extending along the drain bus lines, when viewed in the direction perpendicular to the surface of the transparent insulating substrate.
3. The common electrode substrate according to claim 2, wherein a width of the overlap regions is greater than or equal to 2 \u03bcm and smaller than or equal to 12 \u03bcm when viewed in the direction perpendicular to the surface of the transparent insulating substrate.
4. The common electrode substrate according to claim 1, wherein:
the alignment regulating structures further have auxiliary protrusions that branch off the linear protrusions and extend along portions of the drain bus lines that are opposed to end portions of the pixel electrodes; and
the light shield film has the overlap regions in regions where the auxiliary protrusions are not formed, when viewed in the direction perpendicular to the surface of the transparent insulating substrate.
5. The common electrode substrate according to claim 1, wherein the light shield film is formed outside each of the pixel electrodes in normal alignment regions other than the alignment defective regions of the liquid crystal, when viewed in the direction perpendicular to the surface of the transparent insulating substrate.
6. The common electrode substrate according to claim 5, wherein the light shield film is formed outside each of the pixel electrodes so as to extend along the drain bus lines, when viewed in the direction perpendicular to the surface of the transparent insulating substrate.
7. The common electrode substrate according to claim 6, wherein a distance between end portions of the light shield film and end portions of each of the pixel electrodes in the normal alignment regions of the liquid crystal is smaller than or equal to 7 \u03bcm, when viewed parallel with the surface of the transparent insulating substrate.
8. The common electrode substrate according to claim 5, wherein:
the alignment regulating structures further have auxiliary protrusions that branch off the protrusions and extend along portions of the drain bus lines that are opposed to end portions of the pixel electrodes; and
the light shield film is formed outside each of the pixel electrodes in regions where the auxiliary protrusions are formed when viewed in the direction perpendicular to the surface of the transparent insulating substrate.
9. A common electrode substrate comprising:
a transparent insulating substrate to be arranged opposite to an array substrate having pixel electrodes formed in respective pixel regions that are defined by a plurality of gate bus lines and drain bus lines, and to hold a liquid crystal having negative dielectric anisotropy;
a common electrode formed on the transparent insulating substrate;
alignment regulating structures having linear protrusions formed on the common electrode; and
a light shield film formed on the transparent insulating substrate outside each of the pixel electrodes in normal alignment regions other than alignment defective regions of the liquid crystal when viewed in a direction perpendicular to a surface of the transparent insulating substrate.
10. The common electrode substrate according to claim 9, wherein the light shield film is formed outside each of the pixel electrodes so as to extend along the drain bus lines when viewed in the direction perpendicular to the surface of the transparent insulating substrate.
11. The common electrode substrate according to claim 9, wherein:
the alignment regulating structures further have auxiliary protrusions that branch off the linear protrusions and extend along portions of the drain bus lines that are opposed to end portions of the pixel electrodes; and
the light shield film is formed outside each of the pixel electrodes in regions where the auxiliary protrusions are formed when viewed in the direction perpendicular to the surface of the transparent insulating substrate.
12. The common electrode substrate according to claim 1, wherein the light shield film is formed by laminating, one on another, forming materials of color filters that are formed in the respective pixel regions.
13. A common electrode substrate comprising:
a transparent insulating substrate to be arranged opposite to an array substrate having pixel electrodes formed in respective pixel regions that are defined by a plurality of gate bus lines and drain bus lines, and to hold a liquid crystal having negative dielectric anisotropy;
a common electrode formed on the transparent insulating substrate and having steps for alignment-restricting the liquid crystal in regions opposed to regions between each of the pixel electrodes and the drain bus lines; and
alignment regulating structures having linear protrusions formed on the common electrode.
14. The common electrode substrate according to claim 13, wherein the steps are formed thicker than the regions that are opposed to the respective pixel electrodes.
15. The common electrode substrate according to claim 13, wherein:
the alignment regulating structures further have auxiliary protrusions that branch off the linear protrusions and extend along portions of the drain bus lines that are opposed to end portions of the pixel electrodes; and
the steps are formed in regions where the auxiliary protrusions are not formed.
16. The common electrode substrate according to claim 13, wherein each of the steps is formed in such a manner that a resin is formed under the common electrode.
17. The common electrode substrate according to claim 16, wherein each of the steps is formed in such a manner that forming materials of color filters formed in the respective pixel regions are laminated one on another.
18. The common electrode substrate according to claim 16, wherein each of the steps is made of a black resin.
19. The common electrode substrate according to claim 1, wherein the linear protrusions are formed obliquely with respect to edges of the pixel electrodes.
20. A liquid crystal display device comprising an array substrate having pixel electrodes formed in respective pixel regions that are defined by a plurality of gate bus lines and drain bus lines, an opposite substrate arranged opposite to the array substrate, and a liquid crystal having negative dielectric anisotropy sealed between the array substrate and the opposite substrate;
wherein the opposite substrate is the common electrode substrate as set forth in claim 1.

1. A method for receiving a clock synchronization signal, the method comprising:
determining, by a first communication entity, whether the clock synchronization signal is received from a satellite;
entering, by the first communication entity, a master mode when the clock synchronization signal is received; and
entering a slave mode if the clock synchronization signal is not received,
wherein, if the first communication entity enters the slave mode, the first communication entity searches a second communication entity which operates as the master mode, and
wherein, if the first communication entity enters the master mode, the communication entity provides the clock synchronization signal with a third communication entity which operates as the slave mode.
2. The method of claim 1, wherein entering the slave mode comprises searching the second communication entity providing a clock synchronization signal.
3. The method of claim 2, further comprising selecting, if a plurality of communication entities providing a clock synchronization signal are searched, one of the plurality of the communication entities as the second communication entity.
4. The method of claim 3, wherein the second communication entity is selected based on at least one of M-MAP, number of satellites (#sats), number of slave base stations receiving service currently (#slaves), and signal strength (maxSnr) received from a satellite.
5. The method of claim 4, wherein the at least one of the M-MAP, the number of satellites (#sats), the number of slave base stations receiving service currently (#slaves), and the signal strength (maxSnr) is transmitted from each of the plurality of the communication entities.
6. The method of claim 3, wherein the selecting one of the plurality of the communication entities comprises selecting a communication entity having the smallest number of slave base stations among the plurality of the communication entities as the second communication entity.
7. The method of claim 3, wherein the second communication entity is selected based on scores that are weighted according to number of satellites (#sats), number of slave base stations receiving service currently (#slaves), and signal strength (maxSnr) received from a satellite.
8. The method of claim 1, wherein the determining comprises, if the clock synchronization signal is received, determining whether the received clock synchronization signal fulfills at least one predetermined condition.
9. A first communication entity comprising:
a transceiver configured to transmit and receive a signal; and
a controller configured:
to determine whether a clock synchronization signal is received from a satellite,
to enter a master mode if the clock synchronization signal is received, and
to enter a slave mode if the clock synchronization signal is not received,

wherein, if the first communication entity enters the slave mode, the first communication entity searches a second communication entity which operates as the master mode, and
wherein, if the first communication entity enters the master mode, the first communication entity provides the clock synchronization signal with a third communication entity which operates as the slave mode.
10. The first communication entity of claim 9, wherein the controller is further configured to search the second communication entity providing a clock synchronization signal.
11. The first communication entity of claim 10, wherein if a plurality of communication entities providing a clock synchronization signal are searched, the controller is further configured to select one of the plurality of the communication entities as the second communication entity.
12. The first communication entity of claim 11, wherein the second communication entity is selected based on at least one of M-MAP, number of satellites (#sats), number of slave base stations receiving service currently (#slaves), and signal strength (maxSnr) received from a satellite.
13. The first communication entity of claim 12, wherein the at least one of the M-MAP, the number of satellites (#sats), the number of slave base stations receiving service currently (#slaves), and the signal strength (maxSnr) is transmitted from each of the plurality of the communication entities.
14. The first communication entity of claim 11, wherein the controller is further configured to select a communication entity having the smallest number of slave base stations among the plurality of the communication entities as the second communication entity.
15. The communication entity of claim 11, wherein the second communication entity is selected based on scores that are weighted according to number of satellites (#sats), number of slave base stations receiving service currently (#slaves), and signal strength (maxSnr) received from a satellite.
16. The communication entity of claim 9, wherein the controller is further configured to determine whether the received clock synchronization signal fulfills at least one predetermined condition.
17. The method of claim 8, further comprising entering, if the received clock synchronization signal fulfills the at least one predetermined condition, the master mode.
18. The method of claim 8, further comprising entering, if the received clock synchronization signal unfulfills the at least one predetermined condition, the slave mode.
19. The first communication entity of claim 16, wherein the controller is further configured to enter the master mode if the received clock synchronization signal fulfills the at least one predetermined condition.
20. The first communication entity of claim 16, wherein the controller configured to enter the slave mode if the received clock synchronization signal unfulfills the at least one predetermined condition.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

What is claimed is:

1. An ear covering comprising:
a. an enclosure formed generally in the shape of a human ear and having an opening by which said enclosure may be inserted over the ear;
b. a portion of said enclosure lying adjacent the tragus of the ear having an adhesive thereon for adhering said portion to the tragus of the ear such that an enhanced fluid seal is provided between said enclosure and the tragus; and
c. said opening entirely elasticized to retain said enclosure over the ear and to generally keep foreign materials and fluid out of the ear canal even if said portion having an adhesive thereon loses the ability to adhere to the tragus.
2. The ear covering of claim 1 wherein said portion of said enclosure lying adjacent the tragus of the ear further comprises a flap covering the ear canal and the tragus.
3. The ear covering of claim 1 further comprising said enclosure formed larger than the ear which is to be covered by said enclosure in order to provide insulating space between said enclosure and the ear when said enclosure is inserted over the ear.
4. The ear covering of claim 1 further comprising said enclosure is formed of a material generally permeable to sound such that the enclosure does not substantially impair hearing of a person wearing said enclosure.
5. A method of protecting an ear comprising:
a. enclosing an ear within a membrane having an opening therein by which the membrane is inserted over the ear;
b. providing an adhesive on a portion of said membrane adjacent the tragus of the ear such that said portion of said membrane adheres to the tragus to provide an enhanced seal against fluids and foreign particles entering into the ear canal; and
c. entirely elasticizing said opening to generally retain said membrane over the ear and to keep foreign materials and fluids out of the ear canal even if said portion of said membrane loses the ability to adhere to the tragus.
6. The method of claim 4 further comprising forming said membrane larger than the ear which is to be enclosed within said membrane to provide insulating space between said membrane and the ear when the ear is enclosed within said membrane.
7. The method of claim 4 further comprising forming said membrane from a material generally permeable to sound.