All The Claims

1. A method for testing an electronic device under test that contains wireless communications circuitry and peripheral input-output devices, the method comprising:
while each of the peripheral input-output devices is turned off, using the wireless communications circuitry to obtain a first radio-frequency power level measurement at a selected frequency channel and a first radio frequency power level measurement at an additional frequency channel;
after the wireless communications circuitry has obtained the first radio frequency power level measurement at the selected frequency channel and the first radio frequency power level measurement at the additional frequency channel, while at least one of the peripheral input-output devices is turned on, using the wireless communications circuitry to obtain a second radio frequency power level measurement at the selected frequency channel; and
characterizing radio-frequency performance of the electronic device under test based on the first and second radio frequency power level measurements at the selected channel.
2. The method defined in claim 1 wherein the electronic device under test further contains an applications processor, the method further comprising:
with the applications processor, computing a difference between the first radio frequency power level measurement at the selected frequency channel and the second radio frequency power level measurement at the selected frequency channel.
3. The method defined in claim 2 further comprising:
in response to determining that the difference is less a predetermined threshold, marking the peripheral input-output device as producing an acceptable amount of noise; and
in response to determining that the difference exceeds the predetermined threshold, marking the peripheral input-output device as producing an excessive amount of noise.
4. The method defined in claim 2 wherein the wireless communications circuitry includes a baseband processor and wherein using the wireless communications circuitry to obtain the first radio frequency power level measurement at the selected frequency channel and the second radio frequency power level measurement at the selected frequency channel comprises making the first radio frequency power level measurement at the selected frequency channel and the second radio frequency power level measurement at the selected frequency channel with the baseband processor.
5. The method defined in claim 1 wherein the wireless communications circuitry includes a baseband processor and wherein using the wireless communications circuitry to obtain the first radio frequency power level measurement at the selected frequency channel and the second radio frequency power level measurement at the selected frequency channel comprises making the first radio frequency power level measurement at the selected frequency channel and the second radio frequency power level measurement at the selected frequency channel with the baseband processor.
6. The method defined in claim 1 wherein the wireless communications circuitry includes at least one antenna, the method further comprising:
with the antenna, receiving only noise signals generated from the wireless communications circuitry when obtaining the first radio frequency power level measurement at the selected frequency channel; and
with the antenna, receiving only noise signals generated from the wireless communications circuitry and the at least one of the peripheral input-output devices when obtaining the second radio frequency power level measurement at the selected frequency channel.
7. The method defined in claim 1 wherein the peripheral input-output devices comprise devices selected from the group consisting of: cameras, light-based sensors, displays, touch-based sensors, audio devices, and accelerometers.
8. The method define claim 1 further comprising:
after using the wireless communications circuitry to obtain a second radio frequency power level measurement at the selected frequency channel, using the wireless communications circuitry to obtain a second radio frequency power level measurement at the additional frequency channel.
9. A method for testing an electronic device under test using a test station, wherein the test station includes a test enclosure in which the electronic device under test is tested and wherein the electronic device under test contains processing circuitry and wireless communications circuitry, the method comprising:
using an antenna in the wireless communications circuitry to receive noise signals generated by the wireless communications circuitry and the processing circuitry, wherein the antenna does not receive radio-frequency signals generated by the test station;
with the wireless communications circuitry, making radio frequency power level measurements on the received noise signals, wherein the electronic device under test further contains peripheral input-output devices, and wherein making the radio-frequency power level measurements on the received noise signals comprises:
making a first radio frequency power level measurement in a selected frequency channel while the peripheral input-output devices are turned off;
after making the first radio frequency power level measurement in the selected frequency channel, making a first radio frequency power level measurement in an additional frequency channel while the peripheral input-output devices are turned off;
after making the first radio frequency power level measurement in the additional frequency channel, making a second radio frequency power level measurement in the selected frequency channel while a subset of the peripheral input-output devices is turned on; and
after making the second radio frequency power level measurement in the selected frequency channel, making a second radio frequency power level measurement in a additional frequency channel while the subset of the peripheral input-output devices is turned on; and

characterizing radio-frequency performance of the electronic device under test based on the first radio frequency power level measurements in the selected and additional frequency channels and the second radio frequency power level measurements in the selected and additional frequency channels.
10. The method defined in claim 9 further comprising:
configuring the antenna to prevent transmission of radio-frequency signals.
11. The method defined in claim 9 wherein the wireless communications circuitry contains a baseband processor, the method further comprising:
with the baseband processor, making the radio-frequency power level measurements on the received noise signals.
12. The method defined in claim 9 further comprising:
with the processing circuitry, computing a difference between the first and second radio frequency power level measurements in the selected frequency channel.
13. The method defined in claim 12 further comprising:
in response to determining that the difference is less a predetermined threshold, marking the subset of peripheral input-output devices as producing an acceptable amount of noise; and
in response to determining that the difference exceeds the predetermined threshold, marking the subset of peripheral input-output devices as producing an excessive amount of noise.
14. The method defined in claim 9 wherein the peripheral input-output devices comprise devices selected from the group consisting of: cameras, light-based sensors, displays, touch-based sensors, audio devices, and accelerometers.
15. A method for testing an electronic device under test that contains wireless communications circuitry, the method comprising:
configuring the electronic device under test to operate in a self test mode so that the electronic device under test will automatically be placed in different states; and
while the electronic device is operating in each of the different states, obtaining first radio-frequency power level measurements with the wireless communications circuitry, wherein the electronic device under test further contains peripheral input-output devices, wherein configuring the electronic device under test in the self test mode comprises configuring the electronic device under test to selectively activate respective subsets of the peripheral input-output devices in each of the different states, and wherein the peripheral input-output devices comprise devices selected from the group consisting of: cameras and light-based sensors; and
characterizing radio-frequency performance of the electronic device under test based on the first radio-frequency power level measurements.
16. The method defined in claim 15 wherein the peripheral input-output devices further comprise devices selected from the group consisting of: displays, touch-based sensors, audio devices, and accelerometers.
17. The method defined in claim 15 further comprising:
with the wireless communications circuitry, obtaining second radio-frequency power level measurements while each of the peripheral input-output devices is turned off.
18. The method defined in claim 17 wherein the electronic device under test further comprises an applications processor, the method further comprising:
with the applications processor, comparing the first and second radio-frequency power level measurements to determine whether the wireless communications circuitry is performing satisfactorily in each of the different states.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A system comprising:
a plurality of memory devices including non-volatile solid state memory; and
a memory controller configured to:
scan the non-volatile solid state memory of all of the plurality of memory devices to identify one or more bit line errors for the plurality of memory devices;
construct a set of data corresponding to the identified one or more bit line errors for the plurality of memory devices;
store multiple copies of the set of data in the non-volatile solid state memory of the plurality of memory devices prior to a power down of the plurality of memory devices; and
upon power up of the plurality of memory devices that occurs subsequent to the power down prior to which the set of data is stored,
retrieve the stored multiple copies of the set of data,
perform a comparison of content of the retrieved copies of the set of data, and
use results of the comparison to reconstruct the set of data corresponding to the identified one or more bit line errors for the plurality of memory devices.
2. The system of claim 1, wherein ten copies of the set of data are stored in the non-volatile solid state memory of the plurality of memory devices.
3. The system of claim 1, wherein the comparison is an exclusive or operation (XOR) resulting in a value of true when the retrieved copies, or a portion thereof, match.
4. The system of claim 1, wherein the copies of the set of data are stored in a plurality of memory pages.
5. The system of claim 4, wherein
the plurality of memory pages are within non-volatile solid state memory of a single memory device of the plurality of memory devices, and
the copies of the stored set of data are retrieved by accessing the plurality of memory pages in series.
6. The system of claim 4, wherein
at least two of the plurality of memory pages are within non-volatile solid state memory of two different devices of the plurality of memory devices, and
the copies of the stored set of data are retrieved by accessing the at least two of the plurality of memory pages in parallel.
7. The system of claim 1, wherein the memory controller is further configured to encode the constructed set of data using an error correction code (ECC) prior to storing copies of the set of data in the non-volatile solid state memory of the plurality of memory devices; and
decode, using the ECC, the content of the retrieved copies of the set of data prior to performing the comparison thereof.
8. The system of claim 1, wherein the plurality of memory devices are NAND devices.
9. The system of claim 1, wherein the non-volatile solid state memory of all of the plurality of memory devices is scanned, upon a power up of the plurality of memory devices, as part of a validation process carried out during fabrication of the system.
10. A memory controller comprising:
an interface to connect with non-volatile solid state memory of a plurality of memory devices; and
circuitry to:
perform a first scan of the non-volatile solid state memory of all of the plurality of memory devices to identify one or more bit line errors for the plurality of memory devices;
construct a set of data corresponding to the identified one or more bit line errors for the plurality of memory devices;
store the set of data in the non-volatile solid state memory of one or more but fewer than all of the plurality of memory devices prior to a power down of the plurality of memory devices; and
upon power up of the plurality of memory devices that occurs subsequent to the power down prior to which the set of data is stored,
perform a second scan of only the non-volatile solid state memory of the one or more but fewer than all of the plurality of memory devices which store the set of data;
taking into consideration whether any bit line errors are identified during the second scan, retrieve the set of data stored in the non-volatile solid state memory of the one or more but fewer than all of the plurality of memory devices; and
ascertain, from the retrieved set of data, any one or more bit line errors for all remaining ones of the plurality of memory devices which were not scanned as part of performing the second scan.
11. The memory controller of claim 10, wherein the plurality of memory devices are NAND devices.
12. The memory controller of claim 10, wherein the set of data is stored in a plurality of memory pages.
13. The memory controller of claim 12, wherein
the plurality of memory pages are within non-volatile solid state memory of a single memory device of the plurality of memory devices,
the second scan is performed by scanning only the non-volatile solid state memory of the single memory device, and
the stored set of data is retrieved by accessing the plurality of memory pages in series.
14. The memory controller of claim 12, wherein
the plurality of memory devices comprises three or more memory devices,
at least two of the plurality of memory pages are within non-volatile solid state memory of two different memory devices of the plurality of memory devices,
the second scan is performed by scanning only the non-volatile solid state memory of the two different memory devices, and
the stored set of data is retrieved by accessing the at least two of the plurality of memory pages in parallel.
15. The memory controller of claim 10, wherein the circuitry is further configured to
encode the constructed set of data using an error correction code (ECC) prior to storing the set of data in the non-volatile solid state memory of the plurality of memory devices; and
decode, using the ECC, the content of the retrieved set of data prior to ascertaining any one or more bit line errors for all remaining ones of the plurality of memory devices which were not scanned as part of performing the second scan.
16. The memory controller of claim 10, wherein the first scan of the non-volatile solid state memory of all of the plurality of memory devices is performed, upon a power up of the plurality of memory devices, as part of a validation process carried out during fabrication of a system including the plurality of memory devices and the memory controller.
17. A method performed by a memory controller that is communicatively coupled with a plurality of memory devices including non-volatile solid state memory, the method comprising:
performing a first scan of the non-volatile solid state memory of all of the plurality of memory devices to identify one or more bit line errors for the plurality of memory devices;
constructing a set of data corresponding to the identified one or more bit line errors for the plurality of memory devices;
storing the set of data in the non-volatile solid state memory of one or more but fewer than all of the plurality of memory devices prior to a power down of the plurality of memory devices; and
upon power up of the plurality of memory devices that occurs subsequent to the power down prior to which the set of data is stored,
performing a second scan of only the non-volatile solid state memory of the one or more but fewer than all of the plurality of memory devices which store the set of data;
taking into consideration whether any bit line errors are identified during the second scan, retrieving the set of data stored in the non-volatile solid state memory of the one or more but fewer than all of the plurality of memory devices; and
ascertaining, from the retrieved set of data, any one or more bit line errors for all remaining ones of the plurality of memory devices which were not scanned as part of performing the second scan.
18. The method of claim 17, wherein the first scan of the non-volatile solid state memory of all of the plurality of memory devices is performed, upon a power up, as part of a validation process carried out during fabrication of a system including the plurality of memory devices and the memory controller.
19. The method of claim 17, wherein storing the set of data comprises storing the set of data in a plurality of memory pages.
20. The method of claim 19, wherein
the plurality of memory pages are within non-volatile solid state memory of a single memory device of the plurality of memory devices,
the second scan is performed by scanning only the non-volatile solid state memory of the single memory device, and
the method further comprises retrieving the set of data by accessing the plurality of memory pages in series.
21. The method of claim 19, wherein
the plurality of memory devices comprises three or more memory devices,
at least two of the plurality of memory pages are within non-volatile solid state memory of two different memory devices of the plurality of memory devices, and
the method further comprises retrieving the set of data by accessing the at least two of the plurality of memory pages in parallel.
22. The method of claim 17, further comprising:
encoding the constructed set of data using an error correction code (ECC) prior to storing the set of data in the non-volatile solid state memory of the plurality of memory devices; and
decoding, by using the ECC, the content of the retrieved set of data prior to performing the ascertaining.
23. A method performed by a memory controller that is communicatively coupled with a plurality of memory devices including non-volatile solid state memory, the method comprising:
scanning the non-volatile solid state memory of all of the plurality of memory devices to identify one or more bit line errors for the plurality of memory devices;
constructing a set of data corresponding to the identified one or more bit line errors for the plurality of memory devices;
storing multiple copies of the set of data in the non-volatile solid state memory of the plurality of memory devices prior to a power down of the plurality of memory devices; and
upon power up of the plurality of memory devices that occurs subsequent to the power down prior to which the set of data is stored,
retrieving the stored multiple copies of the set of data,
performing a comparison of content of the retrieved copies of the set of data, and
reconstructing, based on results of the comparison, the set of data corresponding to the identified one or more bit line errors for the plurality of memory devices.
24. The method of claim 23, wherein the scanning of the non-volatile solid state memory of all of the plurality of memory devices is performed, upon a power up of the plurality of memory devices, as part of a validation process carried out during fabrication of a system including the plurality of memory devices and the memory controller.
25. The method of claim 23, wherein ten copies of the set of data are stored in the non-volatile solid state memory of the plurality of memory devices.
26. The method of claim 23, wherein the comparison is an exclusive or operation (XOR) resulting in a value of true when the retrieved copies, or a portion thereof, match.
27. The method of claim 23, wherein the copies of the set of data are stored in a plurality of memory pages.
28. The method of claim 27, wherein
the plurality of memory pages are within non-volatile solid state memory of a single memory device of the plurality of memory devices, and
the copies of the stored set of data are retrieved by accessing the plurality of memory pages in series.
29. The method of claim 27, wherein
at least two of the plurality of memory pages are within non-volatile solid state memory of two different devices of the plurality of memory devices, and
the copies of the stored set of data are retrieved by accessing the at least two of the plurality of memory pages in parallel.
30. The method of claim 23 further comprising:
encoding the constructed set of data using an error correction code (ECC) prior to storing copies of the set of data in the non-volatile solid state memory of the plurality of memory devices; and
decoding, using the ECC, the content of the retrieved copies of the set of data prior to performing the comparison thereof.

1. A computing architecture for a mobile multimedia system used in a land-based vehicle comprised of a plurality of interconnected electrical components including at least one processor with a memory and a field programmable gate array connected with each other by a standardized data bus for the exchange of data between the components, wherein the field programmable gate array is adapted, upon system start-up or during system operation, to load data from the memory to realize application-specific functionality by logic functions implemented inside the field programmable gate array.
2. The computing architecture according to claim 1, where the field programmable gate array serves as a scaleable hardware interface between the central processor and peripheral components comprising at least two of an external memory, a display, a network, a mass storage, an inputoutput system controller and a peripheral inputoutput component.
3. The computing architecture according to claim 1, where time critical or computing intensive functions are realized by means of dedicated scalable hardware accelerators included in the field programmable gate array.
4. The computing architecture according to claim 1, where system functions that include graphicvideo processing, DVD decoding or DSP functions are shared between the application software running on the central processor and the field programmable gate array in a way that the gate array performs pre- or post processing of IO data.
5. The computing architecture according to claim 1, where time-critical or computing intensive functions are realized by means of dedicated hardware accelerators included in the field programmable gate array.
6. The computing architecture according to claim 1, where the at least one central processor comprises two central processors, and where high priority or real-time applications are assigned to one processor and lower priority applications are assigned to the other processor.
7. The computing architecture according to claim 6, where upon completion of the system start-up, an application may be transferred from one processor to another.
8. The computing architecture according to claim 1, where the memory comprises at least one of a random access memory or a flash memory, or combinations thereof.
9. The computing architecture according to claim 1, where the at least one central processor and the memory are integrated as a module.
10. The computing architecture according to claim 1, where the application-specific functionality includes at least one of DVD decoding, digital signal processing and graphic functions.
11. The computing architecture according to claim 1, where the field programmable gate array contains an embedded processor core to be used to implement a hardware accelerator.
12. A computing architecture for a mobile multimedia system used in a land-based vehicle, the computing architecture comprising:
a processor;
a field programmable gate array; and
a recognized industry standard communication bus configured to communicate data between the processor and the field programmable gate array;
where the field programmable gate array is configured to be loaded with a first part of a multimedia vehicle-related application-specific functionality that is cooperatively operable with a second part of the multimedia vehicle-related application-specific functionality that is executable with the processor.
13. The computing architecture of claim 12, further comprising a memory configured to store the multimedia vehicle-related application-specific functionality, the memory accessible by the processor to download the first part of the multimedia vehicle-related application-specific functionality over the recognized industry standard communication bus to the field programmable gate array.
14. The computing architecture of claim 12, where the first part of the multimedia vehicle-related application-specific functionality is executable by the field programmable gate array to decode at least one of video or audio information, or combinations thereof, and the processor is configured to further process the decoded at least one of video or audio information.
15. The computing architecture of claim 12, where the processor, the field programmable gate array, and the recognized industry standard communication bus are configured to operate as a head unit for a vehicle.
16. A computing architecture for a mobile multimedia system used in a land-based vehicle, the computing architecture comprising:
a processor having a bus communication module configured to communicate with a predefined industry standard protocol;
a field programmable gate array having a bus communication module configured to communicate with the predefined industry standard protocol; and
a communication bus coupled between the bus communication modules, the communication bus configured to communicate data between the processor and the field programmable gate array with the predefined industry standard protocol;
where the field programmable gate array is loadable on startup with a vehicle navigation component, a digital video decoder component and a digital data disc driver component;
and where the navigation component and the digital video decoder component are configured to use the same data disc driver component to enable access to data stored on a digital data disc.
17. The computing architecture of claim 16, where the field programmable gate array is configured to be loaded with a first part of a multimedia-related application-specific functionality that is cooperatively operable with a second part of the multimedia-related application-specific functionality that is executable with the processor.
18. The computing architecture of claim 16, further comprising a memory in communication with the processor over a recognized industry standard memory bus, wherein the memory is configured to store the vehicle navigation component, the digital video decoder component and the digital data disc driver component, which are downloadable to the field programmable gate array by the processor over the memory bus and then over the communication bus.
19. The computing architecture of claim 16, where the field programmable gate array is further loadable on startup with a graphics controller, and the navigation component and the digital video decoder component are configured to use the same the graphics controller to drive a display.
20. A computing architecture for a mobile multimedia system used in a land-based vehicle, the computing architecture comprising:
a vehicle head unit;
a predefined industry standard communication bus included in the vehicle head unit, where the predefined industry standard communication bus is configured to provide communication compatibility with products from different manufacturers;
at least one processor and at least one field programmable gate array installable in the vehicle head unit and configurable to communicate over the predefined industry standard communication bus; and
a memory configured to store instructions related to the operational functionality of the vehicle head unit that are selectively executable by the processor and downloadable to the field programmable gate array over the predefined industry standard communication bus for execution by the field programmable gate array.
21. The computing architecture of claim 20, where the processor is operable to access and download the instructions stored in memory to the field programmable gate array over the predefined industry standard communication bus.
22. The computing architecture of claim 20, where the instructions comprise a plurality of multimedia related applications in support of the operation of the vehicle head unit, where some of the applications are downloadable into the field programmable gate array for execution, some of the applications are executable with the processor and some of the applications are a combination of both.
23. The computing architecture of claim 20, where the instructions comprise instructions to provide the functionality of a navigation system and instructions to provide the functionality of a digital video device decoder.
24. The computing architecture of claim 20, where the memory is configured to communicate over a dedicated recognized industry standard memory bus to the processor, and the instructions that are downloadable to the field programmable gate array are communicatable over the dedicated recognized industry standard memory bus to the processor, and then over the predefined industry standard communication bus to the field programmable gate array.
25. A method of operating a computing architecture for a mobile multimedia navigation system used in a land-based vehicle, the method comprising:
energizing a processor and a field programmable gate array included in a head unit of a vehicle;
loading a first portion of a multimedia application supported by the head unit into the field programmable gate array;
executing the first portion of the multimedia application to pre-process data with the field programmable gate array;
communicating the pre-processed data from the field programmable gate array to the processor over a recognized industry standard communication bus;
executing a second portion of the specific application with the processor to further process the pre-processed data from the field programmable gate array;
communicating the data processed by the processor back to the field programmable gate array over the recognized industry standard communication bus; and
further executing with the field programmable gate array the first portion of the specific application to post process the data processed by the processor.
26. The method of claim 25, loading the first portion comprises the processor retrieving the first portion of the multimedia application from a memory over a dedicated recognized industry standard memory bus.
27. The method of claim 26, where loading the first portion comprises the processor transmitting the first portion of the multimedia application retrieved from the memory to the field programmable gate array over the recognized industry standard communication bus.
28. A method of operating a computing architecture for a mobile multimedia navigation system used in a land-based vehicle, the method comprising:
providing a recognized industry standard communication bus protocol;
implementing operation of a first processor from a first processor manufacturer and a field programmable gate array in a head unit of a vehicle;
enabling communication between the first processor and the first field programmable gate array via the recognized industry standard communication bus;
implementing operation of a second processor from a second processor manufacturer to support the vehicle-related functionality provided by the head unit; and
enabling communication between the second processor, the first processor and the first field programmable gate array via the recognized industry standard communication bus.
29. The method of claim 28, where the field programmable gate array is a first field programmable gate array from a first field programmable gate array manufacturer and the method further comprises implementing operation in the head unit a second field programmable gate array from a second field programmable gate array manufacturer and enabling communication between the first processor, the second processor, the first programmable gate array and the second programmable gate array via the recognized industry standard communication bus.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A test device comprising:
a circuit modelling portion suitable for generating one or more model circuits by modelling a test-object circuit in a one-to-one ratio relationship between the test-object circuit and the model circuits or in a one-to-multi ratio relationship between the test-object circuit and the model circuits; and
a test operation portion suitable for synthesizing the model circuits and performing a test operation on the model circuits,
wherein the circuit modelling portion models the test-object circuit with the one-to-multi relationship to generate the model circuits of different types based on a delay amount of the test-object circuit.
2. A method of operating a test device comprising:
at a circuit modelling portion, modelling a first test-object circuit of test-object circuits in a one-to-one ratio relationship between the first test-object circuit and a first model circuit to generate the first model circuit;
at the circuit modeling portion, modelling a second test-object circuit of the test-object circuits in a one-to-multi ratio relationship between the second test-object circuit and a second model circuit to generate the second model circuit; and
at a test operation circuit, performing a test operation by synthesizing the first and second model circuits,
wherein the modelling of the second test-object circuit comprises:
determining a circuit type of the second model circuit based on a delay amount of the second test-object circuit.
3. The method of claim 2, wherein the modelling of the second test-object circuit comprises:
generating the second model circuit of a first type when the delay amount less than a predetermined delay amount; and
generating the second model circuit of a second type when the delay amount is greater than or equal to the predetermined delay amount.
4. The method of claim 3, wherein a circuit area of the first-typed second model circuit is proportional to the delay amount.
5. The method of claim 3, wherein the first-typed second model circuit performs a shifting operation during a period corresponding to the delay amount.
6. The method of claim 3, wherein a circuit area of the second-typed second model circuit is substantially constant regardless of the delay amount.
7. The method of claim 3, wherein the second-typed second model circuit performs a counting operation a number of times corresponding to the delay amount.
8. The method of claim 3, wherein the first-typed and second-typed second model circuits are synchronous circuits.
9. A test device comprising:
a circuit modelling portion suitable for generating various types of model circuits based on a delay amount of a test-object circuit; and
a test operation portion suitable for synthesizing the model circuits and performing a test operation on the model circuits,
wherein the model circuits include a first-typed model circuit generated when the delay amount is under a predetermined delay amount, and a second-typed model circuit when the delay amount is greater than or equal to the predetermined delay amount.
10. The test device of claim 9, wherein a circuit area of the first-typed model circuit is proportional to the delay amount.
11. The test device of claim 9, wherein the first-typed model circuit includes a shifting circuit suitable for shifting an input signal during a period corresponding to the delay amount.
12. The test device of claim 9, wherein a circuit area of the second-typed model circuit is substantially constant regardless of the delay amount.
13. The test device of claim 9, wherein the second-typed model circuit includes:
a counting unit suitable for counting in response to an input signal; and
a comparison unit suitable for comparing the delay amount with an output signal of the counting unit and outputting a result of the comparison.
14. The test device of claim 9, wherein the second-typed model circuit includes:
a first latching unit suitable for latching a time corresponding to the delay amount in response to a rising edge of an input signal;
a second latching unit suitable for latching the time corresponding to the delay amount in response to a falling edge of the input signal;
a counting unit suitable for performing a counting operation in response to a clock signal;
a first comparison unit suitable for comparing output signals of the first latching unit and the counting unit;
a second comparison unit suitable for comparing output signals of the second latching unit and the counting unit; and
an output unit suitable for generating an output signal in response to output signals of the first and second comparison units.
15. The test device of claim 14, wherein the second-typed model circuit further includes an addition unit suitable for providing the first and second latching units with a sum of the output signal of the counting unit and the delay amount.
16. The test device of claim 9, wherein the first-typed and second-typed model circuits are synchronous circuits.
17. A method of operating a test device comprising:
at a circuit modelling portion, generating a first netlist in response to a first delay amount;
at the circuit modelling portion, generating a second netlist in response to a second delay amount, which is greater than the first delay amount;
at a test operation circuit, testing the first and second netlists;
loading a delay circuit of test-object circuits; and
determining whether a delay amount of a loaded delay circuit is the first delay amount or the second delay amount,
wherein the first and second netlists are different model circuits than each other.
18. The method of claim 17, wherein the model circuits corresponding to the first and second netlists are synchronous circuits.
19. The method of claim 17, wherein the testing of the first and second netlists includes:
synthesizing the first and second netlists in the test device to generate a synthesized circuit; and
testing the synthesized circuit.