All The Claims

We claim:

1. For an electronic design automation application, a method of placing circuit modules in an integrated circuit (IC) layout, the method comprising using a diagonal line to measure a placement metric.
2. The method of claim 1, wherein using the diagonal line to measure a placement metric comprises using a diagonal cut line to measure congestion in the IC layout.
3. The method of claim 1, wherein a set of nets represents the interconnection between a set of circuit elements, each net having a number of circuit elements, wherein using the diagonal line to measure a placement metric comprises:
a) using a diagonal cut line to partition a region of the IC layout into two sub-regions;
b) measuring the number of nets that have circuit elements in both the sub-regions created by the diagonal cut line.
4. The method of claim 1, wherein the IC layout has a number of circuit elements, a net having a set of circuit elements, wherein using the diagonal line to measure a placement metric comprises calculating an estimate of the length of interconnect lines necessary to connect the circuit elements of said net, wherein the calculation measures the length of at least one line that is at least partially diagonal.
5. The method of claim 4, wherein calculating the estimate comprises constructing a bounding box encompassing all the circuit elements of the net.
6. The method of claim 5, wherein calculating the estimate further comprises using the diagonal line to measure an attribute of the bounding box.
7. The method of claim 6, wherein said attribute is the distance between two opposing corners of the bounding box, and said diagonal line traversing at least a portion of said distance.
8. The method of claim 6, wherein the diagonal line is 45 line.
9. The method of claim 4, wherein calculating the estimate comprises constructing a connection graph that models the topology of interconnect lines for connecting the circuit elements of the net, said connection graph having edges, wherein at least one of the edges is at least partially diagonal.
10. The method of claim 9, wherein calculating the estimate further comprises calculating the length of the edges of the graphs.
11. The method of claim 10, wherein to calculate the length of each edge that connects two circuit elements, the method further comprises:
a) constructing a bounding box that encompasses the two circuit elements, said bounding box having a long side with a length L and a short side with a length S, wherein the two circuit elements are two corners of the bounding box;
b) calculating the distance (D) between the two corners of the bounding box by the using the equation DLS(cos Asin A)Ssin A,
wherein in said equation, A represents the angle of a diagonal edge of the connection graph.
12. The method of claim 9, wherein the connection graph is a minimum spanning tree that includes a diagonal line and at least one of a horizontal line and a vertical line.
13. The method of claim 9, wherein the connection graph is a Steiner tree that includes a diagonal line and at least one of a horizontal line and a vertical line.
14. For an electronic design automation application, a method of placing circuit elements in an integrated circuit layout, said layout using a wiring model that includes Manhattan and diagonal lines, the method comprising using a diagonal line to measure a cost of a placement configuration.
15. The method of claim 14, wherein using the diagonal line to measure a placement cost comprises using a diagonal cut line to measure congestion of interconnect lines that connect the circuit elements.
16. The method of claim 15, wherein said congestion measurement quantifies the placement cost of an initial placement configuration.
17. The method of claim 15 further comprising:
a) modifying the position of at least one circuit element in the IC layout; and
b) using the diagonal cut line to measure the placement cost of the placement configuration after said modification.
18. The method of claim 14, wherein using the diagonal line to measure a placement cost comprises measuring the length of interconnect lines that connect the circuit elements by using Manhattan lines and diagonal lines.
19. The method of claim 18, wherein said length measurement quantifies the placement cost of an initial placement configuration.
20. The method of claim 18 further comprising:
a) modifying the position of at least one circuit element in the IC layout; and
b) after said modification, measuring the length of interconnect lines that connect the circuit elements by using Manhattan lines and diagonal lines.
21. The method of claim 14, wherein the circuit elements include pins of circuit modules.
22. The method of claim 14, wherein the circuit elements include circuit modules.
23. For an electronic design automation application, a method of placing circuit modules in an integrated circuit (IC) layout, wherein said IC layout includes a net and a plurality of circuit elements, said net representing interconnections between a set of circuit elements in the IC layout, the method comprising:
a) constructing a bounding box that encompasses the circuit elements of the net; and
b) using a diagonal line to measure an attribute of the bounding box.
24. The method of claim 23, wherein said attribute is the distance between two opposing corners of the bounding box, said diagonal line traversing at least a portion of said distance.
25. The method of claim 24, wherein the bounding box has a long side with a length L and a short side with a length S, said diagonal line forming an angle A with a side of the IC layout, wherein measuring the distance (D) between the two corners of the bounding box comprises using the equation DLS(cos Asin A)Ssin A.
26. The method of claim 25, wherein the angle A corresponds to the angle of at least one type of interconnect-line in a wiring model used by the IC layout.
27. The method of claim 24, wherein said distance provides an estimate of interconnect-line length needed to connect the circuit elements of the net.
28. The method of claim 27, wherein said estimate is a lower-bound estimate.
29. The method of claim 27, wherein said estimate is measured to obtain a placement cost of an initial placement configuration.
30. The method of claim 27 further comprising:
a) modifying the position of at least one circuit elements of the net; and
b) after said modification,
constructing a second bounding box that encompasses the circuit elements of the net; and
using a diagonal line to measure the distance between two corners of the second bounding box to obtain a second estimate of the interconnect-line length needed to connect the circuit elements of the net.
31. The method of claim 23, wherein the diagonal line forms a 45 angle with respect to a side of the IC layout.
32. The method of clam 23, wherein the diagonal line forms a 120 angle with respect to a side of the IC layout.
33. The method of claim 23, wherein the circuit elements include pins of circuit modules.
34. The method of claim 23, wherein the circuit elements include circuit modules.
35. For an electronic design automation application, a method of placing circuit modules in an integrated circuit (IC) layout, wherein said IC layout includes a plurality of nets and uses a wiring model that includes diagonal lines, each net including a plurality of circuit elements in the IC layout, the method comprising:
a) for each particular net, constructing a bounding box that encompasses the circuit elements of the particular net;
b) for each particular bounding box, measuring an attribute of the particular bounding box, wherein the method uses diagonal lines to measure the attributes of some of the constructed bounding boxes; and
c) combining said attribute measurements to obtain an estimate of interconnect-line length necessary to connect the circuit elements of the nets in the IC layout.
36. The method of claim 35, wherein the combining of said attribute measurements comprises adding said measurements.
37. The method of claim 35, wherein measuring the attribute of each particular bounding box comprises measuring the distance between two opposing corners of the particular bounding box, wherein at least a portion of said distance for some of the constructed bounding boxes is traversed by a diagonal line.
38. The method of claim 37, wherein measuring the distance between the two corners of a bounding box comprises using the equation DLS(cos Asin A)Ssin A, wherein D is the measured distance, L is the length of a long side of the bounding box, S is zero or the length of a short side of the bounding box, and A is an angle formed by a diagonal line with a side of the IC layout when S is not zero.
39. The method of claim 38, wherein the angle A corresponds to the angle of at least one type of diagonal interconnect-line in the wiring model used by the IC layout.
40. The method of claim 39, wherein the wiring model further includes Manhattan lines.
41. The method of claim 35, wherein the circuit elements include pins of circuit modules.
42. The method of claim 35, wherein the circuit elements include circuit modules.
43. For an electronic design automation application, a method of placing circuit modules in an integrated circuit (IC) layout, wherein said IC layout includes a net and a plurality of circuit elements, wherein the net represents interconnections between a set of circuit elements, the method comprising:
constructing a connection graph that models the topology of interconnect lines for connecting the circuit elements of the net,
said connection graph having edges, each edge connecting two circuit elements of the net, wherein at least one of the edges is at least partially diagonal.
44. The method of claim 43 further comprising:
calculating the length of the edges of the graph; and
combining the length calculations of the edges of the graph.
45. The method of claim 44, wherein the combining of said length calculations comprises adding said measurements.
46. The method of claim 44, wherein to calculate the length of each edge that connects two circuit elements, the method further comprises:
a) constructing a bounding box that encompasses the two circuit elements, said bounding box having a long side with a length L and a short side with a length S, said diagonal edge forming an angle A with a side of the IC layout, wherein the two circuit elements are at two corners of the bounding box;
b) calculating the distance (D) between the two corners of the bounding box by using the equation DLS(cos Asin A)Ssin A,
47. The method of claim 46, wherein the angle A corresponds to the angle of at least one type of interconnect-line in a wiring model used by the IC layout.
48. The method of claim 44, wherein the combined length calculation provides an estimate of interconnect-line length needed to connect the circuit elements of the net.
49. The method of claim 48, wherein said estimate is measured to obtain a placement cost of an initial placement configuration.
50. The method of claim 48 further comprising:
a) modifying the position of at least one circuit elements of the net;
b) after said modification,
constructing a second connection graph that models the topology of interconnect lines for connecting the circuit elements of the net, said second graph having a number of edges, each edge connecting two circuit elements, and
calculating the length of the edges of the second connection graph,

c) to calculate the length of each edge that connects two circuit elements,
constructing a bounding box that encompasses the two circuit elements, said bounding box having a long side with a length L and a short side with a length S, wherein at least one type of interconnect-line in a wiring model used by the IC layout forms an angle A with a side of the IC layout;
calculating the length (D) of the edge by using the equation DLS(cos Asin A)Ssin A.

d) combining the length calculations of the edges of the graph.
51. The method of claim 44, wherein the IC layout includes a plurality of nets, each net having a plurality of circuit elements, the method comprising:
a) for each particular net, constructing a connection graph that models the topology of interconnect lines for connecting the circuit elements of the particular net, said connection graphs having edges, wherein some of the edges are at least partially diagonal;
b) calculating the length of the edges of the graphs; and
c) combining the length calculations to obtain an estimate of the interconnect-line length needed for connecting the circuit elements of the nets.
52. The method of claim 43, wherein the diagonal edge forms a 45 angle with respect to a side of the IC layout.
53. The method of clam 43, wherein the diagonal edge forms a 120 angle with respect to a side of the IC layout.
54. The method of claim 43, wherein the circuit elements include pins of circuit modules.
55. The method of claim 43, wherein the circuit elements include circuit modules.
56. The method of claim 43, wherein the connection graph is a minimum spanning tree.
57. The method of claim 43, wherein the connection graph is a Steiner tree.
58. For an electronic design automation application, a method of placing circuit modules in an integrated circuit (IC) layout, wherein said IC layout includes a plurality of nets each of which includes a plurality of circuit elements in the IC layout, wherein the EDA application includes a wiring model that defines different types of interconnect lines for connecting the circuit elements of the nets, said wiring model having diagonal lines, the method comprising:
a) for each particular net, defining a minimum spanning tree that models the topology of interconnect lines for connecting the circuit elements of the particular net, said minimum spanning trees having edges, wherein at least one of the edges of at least one of the minimum spanning trees is at least partially diagonal,
b) calculating the length of the edges of the minimum spanning trees; and
c) combining the length calculations to obtain an estimate of the total interconnect-line length needed for connecting the circuit elements of the nets.
59. The method of claim 58, wherein some of the diagonal edges are in the same direction as some of the diagonal lines in the wiring model.
60. The method of claim 58 further comprising:
a) moving a circuit element from a first location in the IC layout to a second location in this layout;
b) for each net containing the moved circuit element, defining a new minimum spanning tree that models the topology of interconnect lines for connecting the circuit elements of the particular net after the move, said minimum spanning trees having edges, wherein at least one of the edges of at least one of the minimum spanning trees is at least partially diagonal,
c) calculating the length of the new minimum spanning trees to estimate the change in the total interconnect-line length.
61. For an electronic design automation application, a method of placing circuit modules in an integrated circuit (IC) layout, wherein said IC layout includes a plurality of nets each of which includes a plurality of circuit elements in the IC layout, wherein the EDA application includes a wiring model that defines different types of interconnect lines for connecting the circuit elements of the nets, said wiring model having diagonal lines, the method comprising:
a) for each particular net, defining a Steiner tree that models the topology of interconnect lines for connecting the circuit elements of the particular net, said Steiner trees having edges, wherein at least one of the edges of at least one of the Steiner trees is at least partially diagonal;
b) calculating the length of the Steiner trees; and
c) combining the length calculations to obtain an estimate of the total interconnect-line length needed for connecting the circuit elements of the nets.
62. The method of claim 61, wherein some of the diagonal edges are in the same direction as some of the diagonal lines in the wiring model.
63. The method of claim 61 further comprising defining a set of Steiner points for at least some of the nets.
64. The method of claim 61 further comprising:
a) moving a circuit element from a first location in the IC layout to a second location in this layout;
b) for each net containing the moved circuit element, defining a new Steiner tree that models the topology of interconnect lines for connecting the circuit elements of the particular net after the move, said new Steiner trees having edges, wherein at least one of the edges of at least one of the new Steiner trees is at least partially diagonal,
c) calculating the length of the new Steiner trees to estimate the change in the total interconnect-line length.
65. For an electronic design automation application, a method of placing circuit modules in an integrated circuit (IC) layout, wherein the application uses a set of nets, and each net specifies a set of circuit elements in the layout, the method comprising
a) partitioning a region of the IC layout into two sub-regions by using a diagonal cut line;
b) measuring the number of nets that have circuit elements in both the sub-regions created by the diagonal cut line.
66. The method of claim 65 further comprising changing the positions of the circuit elements in said region to reduce the number of nets that have circuit elements in both sub-regions.
67. The method of claim 66 wherein changing the positions of the circuit elements comprises using a KLFM optimization process.
68. The method of claim 66 wherein changing the positions of the circuit elements comprises using annealing optimization process.
69. The method of claim 66 wherein changing the positions of the circuit elements comprises using a local optimization process.
70. The method of claim 66 further comprising:
a) partitioning one of the sub-regions into two smaller sub-regions by using a second cut line;
b) measuring the number of nets that have circuit elements in both of the smaller sub-regions created by the second cut line.
71. The method of claim 70 wherein the second cut line is a diagonal line.
72. The method of claim 70 wherein the second cut line is a vertical line.
73. The method of claim 70 wherein the second cut line is a horizontal line.
74. The method of claim 70 further comprising changing the positions of the circuit elements in the sub-region to reduce the number of nets that have circuit elements in both of the smaller sub-regions.
75. The method of claim 65, wherein said region was defined by partitioning a bigger region by using a third cut line.
76. The method of claim 75, wherein the third cut line is a diagonal line.
77. The method of claim 75, wherein the third cut line is a vertical line.
78. The method of claim 75, wherein the third cut line is a horizontal line.
79. For an electronic design automation application, a method of placing circuit modules in an integrated circuit layout, wherein the application uses a set of nets, and each net specifies a set of circuit elements in the layout, the method comprising:
a) defining a diagonal cut line that partitions a region of the IC layout into two sub-regions;
b) determining the number of nets intersected by the diagonal cut line;
c) changing the positions of the circuit modules between the sub-regions to minimize the number of nets intersected by the diagonal cut line.
80. The method of claim 79 wherein changing the positions of the circuit elements comprises using a KLFM optimization process.
81. The method of claim 79 wherein changing the positions of the circuit elements comprises using annealing optimization process.
82. The method of claim 79 wherein changing the positions of the circuit elements comprises using a local optimization process.
83. The method of claim 79 further comprising:
a) defining a second cut line that partitions one of the sub-regions into two smaller sub-regions;
b) determining the number of nets intersected by the second cut line; and
c) changing the positions of the circuit modules between the smaller sub-regions to minimize the number of nets intersected by the diagonal cut line.
84. The method of claim 83 wherein the second cut line is one of a diagonal line, a horizontal line, and a vertical line.
85. The method of claim 83 further comprising changing the positions of the circuit elements in the sub-region partitioned by the second cut line to reduce the number of nets that have circuit elements in both of the smaller sub-regions.
86. The method of claim 79, wherein said region was defined by partitioning a bigger region by using a third cut line.
87. The method of claim 86, wherein the third cut line is one of a diagonal line, a vertical line, and a horizontal line.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A wet grinding process comprising wet grinding a mineral material product comprising at least calcium carbonate in the presence of an optional dispersing agent, in order to obtain a wet ground product with a d50 (average diameter) of 0.4 to 1.0 microns, wherein the mineral material product is prepared by the process comprising the stages of:
a) crushing the mineral material in at least one crushing unit until a crushed material is obtained with a d95 of less than 10 cm;
b) optionally subjecting the material crushed according to stage a) to a flotation stage andor a magnetic separation stage andor a sieving stage andor a chemical treatment stage;
c) dry grinding the material according to stage a) andor b) in at least one grinding unit:
(i) in the presence of at least one comb-type hydrophilic polymer containing at least one polyalkylene oxide function grafted on to at least one unsaturated ethylene monomer,
(ii) in such a manner that the quantity of liquid in the grinding unit is less than 15% by dry weight of the material crushed in the crushing unit;

d) optionally classifying the material dry ground according to stage c) with at least one classification unit; and
e) optionally repeating stages c) andor d) on all or part of the dry ground material resulting from stages c) andor d);
wherein the material recovered following stage c) andor d) andor e) has a d50 of 0.5 to 500 microns.
2. The process according to claim 2, wherein the wet ground product so obtained as has a d50 (average diameter) of 0.6 to 0.9 microns.

1. A rotary drill bit comprising:
a bit body having a connecting portion for connection to a conveyance and a drilling portion;
the drilling portion including a drilling surface having a plurality of cutting elements, each cutting element having
at least a first cutting surface and a second cutting surface, the drilling portion being operable in at least two different drilling orientations; and
the drilling surface being rotatable in two opposing directions comprising a first direction and a second direction opposite from the first direction.
2. A rotary drill bit as claimed in claim 1, wherein the first cutting surface is used for drilling when the drilling portion is rotated in a first direction.
3. A rotary drill bit as claimed in claim 1, wherein the second cutting surface is used when the drilling portion is rotated in a second direction.
4. A rotary drill bit as claimed in claim 1, wherein an adjustment means is located on each cutting element for adjusting the configuration of the cutting element while in use.
5. A rotary drill bit as claimed in claim 4, wherein the positional orientation of the cutting elements in relation to the surface of the drilling portion is adjustable.
6. A rotary drill bit as claimed in claim 4, wherein the height of the cutting surface above the surface of the drilling portion is adjustable.
7. A rotary drill bit as claimed in claim 4, wherein the angular displacement between a cutting surface and the surface of the drilling portion is adjustable.
8. A rotary drill bit as claimed in claim 4, wherein the adjustment means is remotely controlled.
9. A rotary drill bit as claimed in claim 1, wherein the rotary drill bit is used with electronically controlled drilling equipment, and the cutting elements are electronically adjustable.
10. A rotary drill bit as claimed in claim 1, wherein at least a portion of the cutting surfaces on the cutting elements are of the PDC type.
11. A rotary drill bit as claimed in claim 1, wherein the drill bit is used with conventional drill pipes.
12. A rotary drill bit as claimed in claim 1, wherein the drill bit is configurable downhole in response to changing conditions in the downhole environment.
13. A method, comprising:
rotating a rotary drill bit in a first rotational direction within a well to extend the well, wherein the rotary drill bit comprises a plurality of cutting elements,
wherein:
at least one of the plurality of cutting elements comprises first and second cutting surfaces; and
rotating the rotary drill bit in the first rotational direction extends the well by removing material with the first cutting surface of the at least one of the plurality of cutting elements; and
rotating the rotary drill bit in a second rotational direction within the well to further extend the well, wherein the first and second rotational directions are substantially opposite, and wherein
rotating the rotary drill bit in the second rotational direction extends the well by removing material with the second cutting surface of the at least one of the plurality of cutting elements.
14. The method of claim 13 further comprising conveying the rotary drill bit within the well via one of:
a wireline; and
a drill string.
15. The method of claim 13 further comprising modifying at least one of the plurality of cutting elements after rotating the rotary drill bit in the first rotational direction but before rotating the rotary drill bit in the second rotational direction.
16. The method of claim 15 wherein modifying at least one of the plurality of cutting elements comprises changing an angle of at least one of the plurality of cutting elements.
17. The method of claim 15 wherein modifying at least one of the plurality of cutting elements comprises changing a height of at least one of the plurality of cutting elements.
18. The method of claim 15 wherein modifying at least one of the plurality of cutting elements comprises retracting at least one of the plurality of cutting elements into the rotary drill bit.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method of making a transient electronic device comprising the steps of:
fabricating one or more inorganic semiconductor components, one or more metallic conductor components or one or more inorganic semiconductor components and one or more metallic conductor components supported by a mother substrate; wherein the one or more inorganic semiconductor components or one or more metallic conductor components independently comprise a selectively transformable material and have a preselected transience profile;
providing a handle substrate having a receiving surface; wherein the receiving surface supports a release layer;
transfer printing the one or more inorganic semiconductor components, one or more metallic conductor components or one or more inorganic semiconductor components and one or more metallic conductor components from the mother substrate to the release layer supported by the handle substrate;
removing the release layer on said handle substrate;
providing a substrate layer on top of the one or more inorganic semiconductor components, one or more metallic conductor components or one or more inorganic semiconductor components and one or more metallic conductor components;
releasing the substrate layer and the one or more inorganic semiconductor components, one or more metallic conductor components or one or more inorganic semiconductor components and one or more metallic conductor components from the handle substrate;
flipping the substrate layer and the one or more inorganic semiconductor components, one or more metallic conductor components or one or more inorganic semiconductor components and one or more metallic conductor components to access an exposed surface of said one or more inorganic semiconductor components, one or more metallic conductor components or one or more inorganic semiconductor components and one or more metallic conductor components supported by the substrate layer; and
processing the exposed surface, thereby making said transient electronic device.
2. A method of making a transient electronic device comprising the steps of:
fabricating one or more inorganic semiconductor components, one or more metallic conductor components or one or more inorganic semiconductor components and one or more metallic conductor components supported by a mother substrate; wherein the one or more inorganic semiconductor components or one or more metallic conductor components independently comprise a selectively transformable material and have a preselected transience profile;
providing a patterned substrate comprising one or more components of an electronic device on a receiving surface of the patterned substrate;
transfer printing the one or more inorganic semiconductor components, one or more metallic conductor components or one or more inorganic semiconductor components and one or more metallic conductor components from the mother substrate to the receiving surface of the patterned substrate; and
integrating the one or more inorganic semiconductor components, one or more metallic components or one or more inorganic semiconductor components and one or more metallic conductor components with the one or more electronic device components on the receiving surface of the patterned substrate, thereby making said transient electronic device.
3. The method of claim 1 or 2, wherein said step of fabricating one or more inorganic semiconductor components, one or more metallic conductor components or one or more inorganic semiconductor components and one or more metallic conductor components supported by a mother substrate is carried out at a semiconductor foundry.
4. The method of any of the preceding claims, wherein said steps other than said step of fabricating one or more inorganic semiconductor components, one or more metallic conductor components or one or more inorganic semiconductor components and one or more metallic conductor components supported by a mother substrate are not carried out in a semiconductor foundry.
5. The method of claim 1, wherein the processing step comprises adding a transient device component.
6. The method of claim 5, wherein the transient device component comprises an electrode, an electrical interconnect, a semiconductor, an encapsulating layer, or any combination thereof.
7. The method of claim 1, wherein the processing step comprises replacing:
an inorganic semiconductor component with a transient inorganic semiconductor component; or
a metallic conductor component with a transient metallic conductor.
8. The method of claim 7, wherein the replacing comprises modifying a physical parameter of the inorganic semiconductor or metallic conductor to make a corresponding transient inorganic semiconductor or transient metal conductor.
9. The method of claim 8, wherein the physical parameter is one or more of:
porosity, thickness, effective density, defect density, dopant concentration, composition, or morphology.
10. The method of claim 1, wherein the processing step comprises providing a transient substrate.
11. The method of claim 1 or 10, wherein the processing step comprises encapsulating at least a portion of the exposed surface with an encapsulating layer.
12. The method of claim 11, wherein the encapsulating layer comprises a selectively removable material that is at least partially removed in response to an external or internal stimulus.
13. The method of claim 12, wherein the selectively removable material of the encapsulating layer comprises a material selected from the group consisting of a polymer, a metal, a metal oxide, a glass and a ceramic.
14. The method of claim 11, 12 or 13, wherein the encapsulating layer, the substrate and at least a portion of the one or more inorganic semiconductor components or the one or more metallic conductor components, each independently comprise a selectively transformable material.
15. The method of claim 1 or 3-14, wherein processing the exposed surface comprises providing one or more interconnect structures for electrically interconnecting the one or more semiconductor components, wherein the interconnect structures independently comprise a selectively transformable material and have a preselected transience profile.
16. The method of claim 15, wherein the electrically interconnecting comprises patterning a transient metal that is W or Mo.
17. The method of claim 15, wherein the one or more interconnect structures are provided via physical vapor deposition, chemical vapor deposition, sputtering, atomic layer deposition, electrochemical deposition, spin casting, ink jet printing, electrohydrodynamic jet printing, screen printing or any combination thereof.
18. The method of claim 1 or 3-17, further comprising the step of integrating a transient passive component, a transient active component, or both, with the one or more inorganic semiconductor components.
19. The method of claim 18, wherein the integrating step is carried out after the step of flipping the substrate layer.
20. The method of claim 18, wherein the integrating step is part of the fabricating step.
21. The method of claim 1 further comprising providing a protective layer between said release layer and said one or more inorganic semiconductor components, one or more metallic conductor components or one or more inorganic semiconductor components and one or more metallic conductor components.
22. The method of claim 21, wherein said protective layer allows for said removal of said release layer without substantial degradation of said one or more inorganic semiconductor components, one or more metallic conductor components or one or more inorganic semiconductor components and one or more metallic conductor components.
23. The method of claim 21 or 22 wherein said protective layer is a polymer layer in contact with said one or more inorganic semiconductor components, one or more metallic conductor components or one or more inorganic semiconductor components and one or more metallic conductor components.
24. The method of any of the preceding claims, wherein the fabricating step comprises forming a plurality of semiconductor components on the mother substrate.
25. The method of claim 24, wherein the fabricating step further comprises undercutting the semiconductor components.
26. The method of claim 25, wherein the plurality of semiconductor components are freestanding on the mother substrate and connected to the mother substrate by one or more anchors.
27. The method of any of the preceding claims, wherein the mother substrate comprises a silicon-on-insulator (SOI) wafer.
28. The method of claim 27, wherein the SOI wafer has a <111> orientation.
29. The method of claim 27, wherein the SOI wafer comprises:
a silicon handle wafer having a <111> orientation;
a buried insulator layer; and
a top layer of active Si having a <100> orientation from which the one or more semiconductor components are formed.
30. The method of claim 29, further comprising the step of: etching the Si <111> handle wafer to facilitate release of the one or more semiconductor device components that comprise Si <100> from the mother substrate.
31. The method of claim 29, wherein the SOI wafer comprises a commercial quality SOI wafer that is coated with the buried insulator layer that is an oxide layer, and the oxide layer is bonded to a bulk <111>-oriented silicon wafer.
32. The method of claim 31, wherein the oxide layer comprises silicon dioxide.
33. The method of any of the preceding claims, wherein the transfer printing comprises dry transfer contact printing.
34. The method of claim 33, wherein the dry transfer printing further comprises
contacting the one or more inorganic semiconductor components, one or more metallic conductor components or one or more inorganic semiconductor components and one or more metallic conductor components with a transfer device;
removing the transfer device and the one or more inorganic semiconductor components, one or more metallic conductor components or one or more inorganic semiconductor components and one or more metallic conductor components from the mother substrate;
contacting the transfer device and the one or more inorganic semiconductor components, one or more metallic conductor components or one or more inorganic semiconductor components and one or more metallic conductor components to the handle substrate; and
removing the transfer device without the one or more inorganic semiconductor components, one or more metallic conductor components or one or more inorganic semiconductor components and one or more metallic conductor components, thereby transferring the one or more inorganic semiconductor components, one or more metallic conductor components or one or more inorganic semiconductor components and one or more metallic conductor components to the handle substrate.
35. The method of claim 33, wherein the transfer device comprises an elastomeric stamp.
36. The method of any of the preceding claims, wherein the transfer printing is high throughput and high fidelity.
37. The method of claim 1, wherein the handle substrate comprises a Si wafer.
38. The method of any of the preceding claims, wherein the step of providing said substrate layer comprises:
spin casting; or
laminating a polymer, metal, metal oxide, ceramic or glass to a surface of the one or more metallic conductor components or one or more inorganic semiconductor components and one or more metallic conductor components.
39. The method of claim 38, wherein the polymer is an organic polymer, poly(lactic-co-glycolic acid) (PLGA), or polydimethylsiloxane (PDMS).
40. The method of claim 30, wherein providing the substrate layer is before the etching step.
41. The method of claim 30, wherein providing the substrate layer is after the etching step.
42. The method of any of the preceding claims, wherein the substrate layer comprises a selectively transformable material.
43. The method of claim 42, wherein the substrate layer has a user-selected degradation characteristic in a defined environmental setting.
44. The method of claim 43, wherein the degradation characteristic is a degradation rate that is at least partially dependent on a physical parameter of the surrounding environment.
45. The method of any of the preceding claims, further comprising the step of transferring the one or more inorganic semiconductor components, one or more metallic conductor components or one or more inorganic semiconductor components and one or more metallic conductor components from the substrate layer to a receiving substrate by contact printing.
46. The method of any of the preceding claims, the substrate layer having mechanical properties to facilitate handling and flipping without damage to the one or more inorganic semiconductor components, one or more metallic conductor components or one or more inorganic semiconductor components and one or more metallic conductor components.
47. The method of any of the preceding claims, wherein the step of releasing the substrate layer and the one or more inorganic semiconductor components, one or more metallic conductor components or one or more inorganic semiconductor components and one or more metallic conductor components from the handle substrate comprises applying a removal force to the substrate layer in a direction away from the handle substrate.
48. The method of any of the preceding claims, wherein the step of releasing the substrate layer and the one or more inorganic semiconductor components, one or more metallic conductor components or one or more inorganic semiconductor components and one or more metallic conductor components from the handle substrate comprises peeling the substrate layer in a direction away from the handle substrate.
49. The method of claim 1, wherein the substrate layer functions as a handle for separating the one or more inorganic semiconductor components, one or more metallic conductor components or one or more inorganic semiconductor components and one or more metallic conductor components from handle substrate.
50. The method of claim 49, wherein the substrate layer functions as a handle for transferring the one or more inorganic semiconductor components, one or more metallic conductor components or one or more inorganic semiconductor components and one or more metallic conductor components to a receiving substrate having a receiving surface.
51. The method of claim 1, wherein the release layer comprises a layer of poly(methyl methacrylate) (PMMA).
52. The method of claim 51, wherein the removing step comprises a two-step dry and wet process to facilitate removal of the substrate layer and the one or more inorganic semiconductor components, one or more metallic conductor components or one or more inorganic semiconductor components and one or more metallic conductor components from the handle wafer.
53. The method of any of the preceding claims, wherein the transience profile is selected by adjusting any one or more of:
a thickness of the semiconductor or the metallic conductor components;
a density of the semiconductor or the metallic conductor components;
a defect density of the semiconductor or the metallic conductor components;
a composition of the semiconductor or the metallic conductor components;
a porosity of the semiconductor or the metallic conductor components;
a crystallinity of the semiconductor or the metallic conductor components;
a dopant of the semiconductor or the metallic conductor components; or
a morphology of the semiconductor or the metallic conductor components.
54. The method of any of the preceding claims, wherein the one or more metallic conductor components are independently selected from the group consisting of Mg, Mo, W, Fe, Zn and alloys thereof.
55. The method of any of the preceding claims comprising fabricating a plurality of inorganic semiconductor components.
56. The method of claim 55, wherein the processing step comprises providing one or more metallic components.
57. The method of any of the preceding claims, wherein the one or more metallic components comprise interconnects that electrically interconnect one or more semiconductor components.
58. The method of any of the preceding claims, wherein the metallic components comprise electrodes in electrical communication with the one or more semiconductor components.
59. The method of any of the preceding claims, wherein the metallic components are provided by a deposition technique.
60. The method of claim 59, wherein the deposition technique is selected from the group consisting of physical vapor deposition, chemical vapor deposition, sputtering, epitaxial growth, atomic layer deposition, electrochemical deposition, electrohydrodynamic jet printing, and molecular beam epitaxy.
61. The method of any of the preceding claims, wherein the one or more inorganic semiconductor components or one or more metallic conductor components is microsized, having a lateral dimension that is greater than or equal to 5 \u03bcm and less than or equal to 500 \u03bcm.
62. The method of any of the preceding claims, wherein the transient electronic device comprises a metal-oxide semiconductor field-effect transistor (MOSFET);
a complementary metal-oxide-semiconductor (CMOS), a transistor, a capacitive sensor, a diode, a photodector, or a capacitor.
63. The method of any of the preceding claims, wherein the transient electronic device is a communication system, a photonic device, a sensor, an optoelectronic device, a biomedical device, a temperature sensor, a photodetector, a photovoltaic device, a strain gauge, an imaging system, a wireless transmitter, an antenna, a battery, a nanoelectromechanical system or a microelectromechanical system.
64. The method of claim 1, comprising a plurality of semiconductor components or a plurality of metallic conductor components that are simultaneously transferred to the handle wafer, wherein the plurality is selected from a range that is greater than or equal to 2 components and less than or equal to 100,000,000 components.
65. The method of any of the preceding claims, wherein the one or more inorganic semiconductor components or the one or more metallic conductor components independently comprise one or more thin film structures.
66. The method of claim 65, wherein the one or more thin film structures each independently have a thickness selected over a range that is greater than or equal to 10 nm and less than or equal to 100 \u03bcm.
67. The method of any of the preceding claims, wherein the transient electronic device degrades in response to an environmental signal.
68. The method of any of the preceding claims, wherein the transient electronic device degrades in response to a user-initiated signal.
69. The method of any of the preceding claims, wherein the selectively transformable material has an electrical dissolution rate selected from the range of 0.01 nmday to 100 \u03bcms.
70. The method of any of the preceding claims, wherein the preselected transience profile is characterized by one or more of:
a transformation of 0.01% to 100% of said one or more inorganic semiconductor components or said one or more metallic conductor components over a time interval selected from the range of 1 ms to 5 years;
a decrease in average thickness of said one or more inorganic semiconductor components or said one or more metallic conductor components at a rate selected over the range of 0.01 nmday to 100 microns s\u22121;
a decrease in electrical conductivity of said one or more inorganic semiconductor components or said one or more metallic conductor components at a rate selected over the range of 1010 S\xb7m\u22121 s\u22121 to 1 S\xb7m\u22121 s\u22121;
a change in morphology of said one or more inorganic semiconductor components or said one or more metallic conductor components, said change in morphology selected from the group consisting of pitting, flaking, cracking and uniform degradation;
a percentage decrease in density of said one or more inorganic semiconductor components or said one or more metallic conductor components selected over the range of 0.01% to 99.9%; or
a percentage increase in porosity of said one or more inorganic semiconductor components or said one or more metallic conductor components selected over the range of 0.01% to 99.9%.