All The Claims

1. A computer implemented method comprising steps of: converting lines of source code representing functions to byte-codes representing functions;
selecting a subsequence of byte-codes based on the byte-codes and dynamic run-time properties of variables referenced by the byte-codes;
generating processor instructions in a compiler for the subsequence; and
generating alternate byte-codes in an accelerated interpreter for at least a portion of the byte-codes not contained in the subsequence.
2. The method of claim 1 in which the properties comprise at least one of variable type or variable shape.
3. The method of claim 2 in which selecting comprises:
analyzing the type and shape of the variables referenced by the byte-codes; and
determining whether at least one of the type or shape is modified.
4. The method of claim 3 in which selecting further comprises:
adding the byte-codes to the subsequence if the type and shape is not modified.
5. The method of claim 4 in which the subsequence represents a compilation unit.
6. The method of claim 1 further comprising executing the processor instructions in a processor.
7. The method of claim 1 further comprising:
reverting a compilation unit to interpreted byte-codes; and
removing the byte-codes in the subsequence of lines in which the type or shape of variables has changed.
8. A computer implemented method comprising steps of:
converting lines of source code representing functions to byte-codes representing functions;
selecting a subsequence of byte-codes based on the byte-codes and dynamic run-time properties of variables referenced by the byte-codes;
generating processor instructions in a compiler for the subsequence;
interpreting the byte-codes not contained in the subsequence;
reverting a compilation unit to interpreted byte-codes; and
determining whether the byte-codes that are members of the subsequence can remain in the subsequence.
9. The method of claim 8 in which determining comprises:
analyzing an original type and shape of a variable; and
determining whether a new type and a new shape of variable can be represented by the original type and original shape of variable.
10. The method of claim 8 in which determining comprises:
analyzing an original type and shape of a variable; and
determining whether the byte-codes can be compiled to processor instructions that can process both the original type and shape of the variable and the modified type and shape of the variable.
11. A computer implemented method comprising steps of:
converting lines of source code representing functions to byte-codes representing functions;
selecting a subsequence of byte-codes based on the byte-codes and dynamic run-time properties of variables referenced by the byte-codes;
generating alternate byte-codes in an accelerated interpreter for the subsequence; and
interpreting the byte-codes not contained in the subsequence by a second interpreter.
12. The method of claim 11 in which selecting comprises:
determining type and shape of variables referenced by the byte-codes; and
resolving dynamic variable and constant value references to an absolute memory address.
13. The method of claim 12 in which resolving comprises determining:
whether an expression requires one or more temporary results; and
storing the temporary results in memory locations that are determined at compile time.
14. The method of claim 12 in which resolving comprises:
using a composition of an expression to group operations of an element-wise expression into a single compound operation.
15. A computer implemented method comprising steps of:
converting source code representing functions to byte-codes representing functions;
selecting a first subsequence of byte-codes based on the byte-codes and dynamic run-time state of program variables;
selecting a second subsequence of byte-codes based on the byte-codes and the dynamic run-time state of program variables;
generating processor instructions in a compiler for the first subsequence;
generating alternate byte-codes in an accelerated interpreter for the second subsequence; and
interpreting the byte-codes not contained in the first subsequence and the second subsequence.
16. The method of claim 15 in which selecting the first subsequence comprises:
analyzing type and shape of the variables referenced by the byte-codes;
determining whether the type and shape is modified; and
adding the byte-codes to the subsequence if the type and shape is not modified.
17. The method of claim 15 in which selecting the second subsequence comprises:
determining the type and shape of variables referenced by the byte-codes; and
resolving dynamic variable and constant value references to an absolute memory address.
18. The method of claim 15 in which selecting the second subsequence comprises:
using a structure of an expression to group operations of an element-wise expression into a single compound operation.
19. A computer implemented system comprising steps of:
a first interpreter in a memory for converting source code into bytes-codes representing functions;
an analysis unit in the memory for analyzing whether the byte-codes can be stored in a subsequence of byte-codes;
a compiler for compiling byte-codes in the subsequence to processor instructions; and
a second compiler for converting byte-codes not resident in the subsequence to alternate byte-codes.
20. The system of claim 19 further comprising a second interpreter for executing the alternate byte-codes.
21. The system of claim 19 further comprising a processor for executing the processor instructions.
22. The system of claim 21 further comprising an inputoutput device for receiving the source code and displaying results after execution of the processor instructions.
23. The system of claim 19, wherein the first interpreter, the compiler, or the second compiler executes on a first processor or a second processor.
24. An article comprising:
a storage medium having stored thereon instructions that when executed by a machine results in the following:
converting lines of source code representing functions to byte-codes representing functions;
selecting a subsequence of byte-codes based on the byte-codes and dynamic run-time properties of variables referenced by the byte-codes;
generating processor instructions in a compiler for the subsequence; and
generating alternate byte-codes in an accelerated interpreter for at least a portion of the byte-codes not contained in the subsequence.
25. An article comprising a storage medium having stored thereon instructions that when executed by a machine results in the following:
converting source code representing functions to byte-codes representing functions;
selecting a first subsequence of byte-codes based on the byte-codes and the dynamic run-time state of program variables;
selecting a second subsequence of byte-codes based on the byte-codes and dynamic run-time state of program variables;
generating processor instructions in a compiler for the first subsequence;
generating alternate byte-codes in an accelerated interpreter for the second subsequence; and
interpreting the byte-codes not contained in the first subsequence and the second subsequence.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A bus, having at least an address remapper defining two sections in the bus, each section comprising at least one station having a physical address, wherein stations on each section of the bus are each assigned a dummy address for being addressed by a station on the other section, the address remapper remapping a dummy address from one section into a physical address to the other section.
2. A bus according to claim 1, wherein the format of a physical address comprises a fixed part and a setable part, and wherein the dummy address is obtained by changing at least one bit of the fixed part of the physical address.
3. A bus according to claim 1, wherein the dummy addresses for stations out of a given section are different from the physical addresses for stations in said given section.
4. An address remapper for a bus, comprising:
terminals for connecting two sections of the bus;
address detecting means for detecting an address received from one section of the bus;
address remapping means for remapping the address and transmitting the remapped address to the other section of the bus.
5. An address remapper according to claim 4, wherein the bus is a two wire serial bus, and wherein the address detecting means detect a transition of the value on one wire while the other wire is a given level.
6. An address remapper according to claim 4, wherein the bus is a two wire serial bus, and wherein the address remapping means comprise means for bringing one wire to a given level.
7. An address remapper according to claim 4, wherein the bus is a two wire serial bus having one data wire and one clock wire, the terminals for the clock wire of each section being connected.
8. An address remapper according to claim 7, wherein the address remapping means includes switching means for selectively disconnecting the bus during the remapping operation.
9. A process for connecting two sections of a bus, by transmitting data from one section of the bus to the other section of the bus, comprising the steps of
detecting an address sent from one section of the bus to the other section of the bus;
remapping the address before transmitting it to the other section of the bus.
10. A process according to claim 9, wherein the step of detecting comprises detecting a START condition preceding an address.
11. A process according to claim 10, wherein the step of remapping comprises changing at least one bit of an address, preferably one bit of a fixed part of an address.
12. A computer system including a bus, having at least an address remapper defining two sections in the bus, each section comprising at least one station having a physical address, wherein a station on one section of the bus is assigned a dummy address for being addressed by a station on the other section, the address remapper remapping a dummy address from the other section into a physical address to the one section.
13. A computer system according to claim 12, wherein the format of a physical address comprises a fixed part and a setable part, and wherein the dummy address is obtained by changing at least one bit of the fixed part of the physical address.
14. A computer system according to claim 12, wherein the dummy addresses for stations out of a given section are different from the physical addresses for stations in said given section.
15. A bus having at least an address remapper defining at least two sections of the bus, each section of the bus having at least one station having a physical address and wherein each station in each section of the bus is assigned a dummy address for use when being addressed by a station on the other bus section, the address remapper remapping dummy addresses on either section of the bus into a corresponding physical address on the other section of the bus.
16. The bus of claim 15 wherein a station on one portion of the bus and another station on the other portion of the bus share a common physical address.
17. A bus as claimed in claim 15 wherein the address remapping is performed by changing at least one bit of the address of each station.
18. A bus, having at least an address remapper defining two sections in the bus, each section including at least one station having a physical address, wherein each station on each section of the bus is assigned a dummy address by the remapper for the purpose of being addressed by a station on the other section, the address remapper transparently remapping each dummy address from one section into a physical address on the other section.

1. A video signal transceiver having a triax port, a baseband port, a demodulator for converting a HF video signal received at said triax port into a first baseband video signal for outputting at said baseband port and at least one modulator for converting a baseband control signal received at said baseband port into a HF control signal for outputting at said triax port, a fibre-optical port, an optical receiver for converting an optical video signal received at said fibre-optical port into a second baseband video signal, a switch for connecting either said first baseband video signal or said second baseband video signal to a video signal line of said baseband port, and an optical transmitter for transmitting, via said fibre-optical port, an optical control signal derived from said baseband control signal.
2. The transceiver of claim 1, wherein an input of the optical transmitter receives said HF control signal from said at least one modulator.
3. The transceiver of claim 2, further comprising a switch for selectively applying said HF control signal either to said triax port or to said optical transmitter.
4. A video signal transceiver having a baseband port, a triax port, a modulator for converting a baseband video signal received at said baseband port, into a HF video signal for outputting at said triax port and a filter for converting a HF control signal received at said triax port into a first baseband control signal for outputting at said baseband port, a fibre-optical port, an optical transmitter for converting a baseband video signal received at said baseband port into an optical video signal for transmission at said fibre-optical port, an optical receiver for converting an optical control signal received via said fibre-optical port into a second baseband control signal, and a switch for selectively connecting either the first baseband control signal or said second baseband control signal derived from said optical control signal by said optical receiver to at least one demodulator, and said at least one demodulator for converting said output of said switch into a control signal supplied to a control signal line of said baseband port.
5. The transceiver of claim 4, wherein said second baseband control signal from said optical receiver is applied to said at least one demodulator.
6. The transceiver of claim 5, further comprising a switch for selectively applying said baseband video signal either to said modulator or to said optical transmitter.
7. The transceiver of claim 4, comprising signal source detecting means for detecting a signal source connected to said triax port or to said fibre-optical port and for operating the switch so as to establish a signal connection between the baseband port and the one of triax and fibre-optical ports at which the signal is detected.
8. The transceiver of claim 7, wherein the signal source detecting means is adapted to establish the signal connection between the baseband port and a predetermined one of triax and fibre-optical ports if the signal is detected at both the triax port and the fibre-optical port.
9. The transceiver of claim 7, wherein the signal source detecting means comprises a photo-detector connected to said fibre-optical port and judges a signal to be present at the fibre-optical port based on the average optical power received at said photodiode.
10. The transceiver of claim 7, wherein said signal source detecting means comprises carrier detecting means for retrieving a carrier of a modulated signal received at said fibre-optical port and judges a signal to be present at the fibre-optical port based on whether said carrier is retrieved or not.
11. The transceiver of claim 1, comprising signal source detecting means for detecting a signal source connected to said triax port or to said fibre-optical port and for operating the switch so as to establish a signal connection between the baseband port and the one of triax and fibre-optical ports at which the signal source is detected.
12. The transceiver of claim 11, wherein the signal source detecting means is adapted to establish the signal connection between the baseband port and a predetermined one of triax and fibre-optical ports if the signal source is detected at both the triax port and the fibre-optical port.
13. The transceiver of claim 11, wherein the signal source detecting means comprises a photo-detector connected to said fibre-optical port and judges a signal to be present at the fibre-optical port based on the average optical power received at said photodiode.
14. The transceiver of claim 11, wherein said signal source detecting means comprises carrier detecting means for retrieving a carrier of a modulated signal received at said fibre-optical port and judges a signal to be present at the fibre-optical port based on whether said carrier is retrieved or not.
15. The transceiver of claim 14, wherein the fibre-optical port comprises two optical fibre lines, the first one of which is connected to said optical receiver and the second one of which is connected to said carrier detecting means.
16. The transceiver of claim 1, wherein a power supply circuit is connected to said triax port and to an electric line of said fibre-optical port so as to provide electric power to a remote signal source, and a load detecting means is provided for detecting whether an electric load is connected to one of said triax and optical ports and for operating the switch so as to establish a signal connection between the baseband port and the one of triax and fibre-optical ports at which the load is detected.
17. The transceiver of claim 16, wherein the load detecting means is adapted to establish the signal connection between the baseband port and a predetermined one of triax and fibre-optical ports if the signal source is detected at both the triax port and the fibre-optical port.
18. The transceiver of claim 17, wherein said switch is operated by a voltage present at said triax port or at an electric line of said fibre-optical port to establish a signal connection between the baseband port and the one of triax and fibre-optical ports at which the voltage is detected.
19. The transceiver of claim 11 wherein the switch is adapted to establish the signal connection between the baseband port and a predetermined one of triax and fibre-optical ports if the voltage is detected at both the triax port and the fibre-optical port.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A frequency modulation method for imprinting a digital message formed by a sequence of symbols on a set of frequency bands, whereby each symbol is assigned one symbol value out of a defined set of symbol values, the method comprising:
defining at least two symbol transmission channels, each symbol transmission channel being formed by a sub-set of frequency bands selected from the set of frequency bands and each frequency band of a symbol transmission channel being allocated to a symbol value of the set of symbol values in a one-to-one relation, such that the symbol transmission channels differ from each other in at least one frequency band of the sub-set of frequency bands andor in an allocation of a frequency band to a symbol value; and
modulating each of the defined symbol transmission channels successively with a single symbol value of the digital message according to the allocation defined for the frequency bands of the respective symbol transmission channel, wherein
modulation of a defined symbol transmission channel with a single symbol value is effected by up-converting a baseband shaped pulse signal to the frequency band of a respective symbol transmission channel which is allocated to a respective single symbol value.
2. A method according to claim 1, further comprising:
defining a usage order for modulating the defined symbol transmission channels; and
modulating each symbol transmission channel successively according to the defined usage order.
3. A method according to claim 1, wherein the defined symbol transmission channels are reused for effecting a modulation with symbol values of the digital message upon the number of symbols in the digital message exceeding the number of defined symbol transmission channels.
4. A method according to claim 3, wherein the defined symbol transmission channels are reused in the order used for modulating the defined symbol transmission channels with the first symbol values of the digital message.
5. A method according to claim 3 wherein the defined symbol transmission channels are reused in an order different to the order used for modulating the defined symbol transmission channels with the first symbol values of the digital message.
6. A method according to claim 1, wherein the bandwidth of the baseband shaped pulse signal corresponds to the bandwidth defined for the frequency band to which it is up-converted.
7. A method according to claim 1, wherein at least two sub-channels are defined for a frequency band of the set of frequency bands such that the phase angles of any two sub-channels defined for a frequency band are different.
8. A conversion controller for a frequency shift keying transmitter and for a frequency shift keying receiver, the controller comprising:
symbol transmission channel definition means for defining at least two symbol transmission channels with each symbol transmission channel being formed by a sub-set of frequency bands selected from a set of frequency bands;
allocation means for allocating each frequency band of a symbol transmission channel to a symbol value of the set of symbol values in a one-to-one relation such, that the symbol transmission channels differ from each other in at least one frequency band of the sub-set of frequency bands andor in an allocation of a frequency band to a symbol value; and
output means for outputting a control signal to an oscillator, whereby the control signal is adapted to adjust the oscillator frequency to the centre frequency of the frequency band used for modulating a respective symbol transmission channel, wherein
the symbol transmission channel definition means further comprises a sub-channel definition means for defining at least two sub-channels with different phase angles for each frequency band, and
the output means is further adapted to control a phase of an oscillator according to the phase angle defined for a sub-channel.
9. A transmitter having a conversion controller according to claim 8.
10. A frequency modulation method for imprinting a digital message formed by a sequence of symbols on a set of frequency bands, whereby each symbol is assigned one symbol value out of a defined set of symbol values, the method comprising:
defining at least two symbol transmission channels formed by a sub-set of frequency bands selected from the set of frequency bands, each frequency band of each symbol transmission channel within one time frame being allocated to a symbol value of the set of symbol values in a one-to-one relation, such that the symbol transmission channels differ within one time frame from each other in at least one frequency band of the sub-set of frequency bands andor in an allocation of a frequency band to a symbol value;
modulating each of the defined symbol transmission channels successively with a single symbol value of the digital message according to the allocation defined for the frequency bands of the respective symbol transmission channel;
rotating the allocation of the frequency bands to the symbol values for each time frame; and
rotating the allocation of the frequency bands from frame to frame in such a way that a fixed frequency offset between the frequency band of a symbol transmission channel in a current time frame and the corresponding frequency band used in the corresponding symbol transmission channel of the previous time frame is achieved, wherein
at least two sub-channels are defined for a frequency band of the set of frequency bands such that the phase angles of any two sub-channels defined for a frequency band are different.
11. A conversion controller for a frequency shift keying transmitter and for a frequency shift keying receiver, the controller comprising:
symbol transmission channel definition means for defining at least two symbol transmission channels with each symbol transmission channel being formed by a sub-set of frequency bands selected from a set of frequency bands;
allocation means for allocating within one time frame each frequency band of a symbol transmission channel to a symbol value of the set of symbol values in a one-to-one relation such that the symbol transmission channels within one time frame differ from each other in at least one frequency band of the sub-set of frequency bands andor in an allocation of a frequency band to a symbol value; and
output means for outputting a control signal to an oscillator, whereby the control signal is adapted to adjust the oscillator frequency to the centre frequency of the frequency band used for modulating a respective symbol transmission channel, wherein
the allocation means rotates the allocation of the frequency bands to the symbol values for each time frame and rotates the order of the frequency bands from frame to frame in such a way that a fixed frequency offset between the frequency band of a symbol transmission channel in a current time frame and the corresponding frequency band used in the corresponding symbol transmission channel of the previous time frame is achieved, and
the symbol transmission channel definition means includes sub-channel definition means for defining at least two sub-channels with different phase angles for each frequency band.