All The Claims

1. An endovascular graft comprising an expandable stent portion and a stent cover portion, wherein the stent cover portion comprises a porous, fibrous material having both an outer perigraft surface and an inner luminal surface, and is coated on at least the outer surface with a hemostatic bioactive agent covalently attached by the activation of photoreactive groups provided by the stent cover portion, by the bioactive agent itself, andor by a linking agent, wherein the coating comprises the bioactive agent attached to the fibers of the material without occluding its pores.
2-5. (canceled)
6. A graft according to claim 1 wherein the agent is selected from the group consisting of proteins having a specific hemostatic effect, and positively charged compounds having a nonspecific effect.
7. (canceled)
8. A graft according to claim 6 wherein the agent is (a) a positively charged polymeric molecule selected from the group consisting of chitosan, polylysine, poly(ethyleneimine) and acrylic polymers incorporating positively-charged groups in the form of primary, secondary, or tertiary amines or quaternary salts, or (b) a positively charged non-polymeric molecule selected from the group consisting of alkyldimethylbenzylammonium chloride and tridodecylmethylammonium chloride.
9-10. (canceled)
11. A method of preparing an endovascular graft comprising an expandable stent portion and a stent cover portion, comprising the step of coating at least the outer surface of the stent cover portion with a hemostatic bioactive agent that is covalently attached by the activation of photoreactive groups provided by the stent cover portion, by the bioactive agent, andor by a linking agent.
12-15. (canceled)
16. A method according to claim 11 wherein the agent is selected from the group consisting of proteins having specific hemostatic effect, and positively charged compounds having a nonspecific hemostatic effect.
17. (canceled)
18. A method according to claim 16 wherein the agent is (a) a positively charged polymeric molecule selected from the group consisting of chitosan, polylysine, poly(ethyleneimine) and acrylic polymers incorporating positively-charged groups in the form of primary, secondary, or tertiary amines or quaternary salts, or (b) a positively charged non-polymeric molecule selected from the group consisting of alkyldimethylbenzylammonium chloride and tridodecylmethylammonium chloride
19-20. (canceled)
21. A method of preventing endoleaking in the course of deploying and using an endovascular graft that comprises an expandable stent portion and a stent cover, the method comprising the step of first coating the stent cover by a method that comprises the step of coating at least the outer surface of the stent cover portion with a hemostatic bioactive agent that is covalently attached by the activation of photoreactive groups provided by the stent cover portion, by the bioactive agent, andor by a linking agent.
22. A method according to claim 21 wherein the stent cover portion is prepared from a porous material selected from PET and ePTFE.
23. A method according to claim 21 wherein the agent is selected from the group consisting of proteins having a specific hemostatic effect, and positively charged compounds having a nonspecific hemostatic effect.
24-25. (canceled)
26. A method according to claim 21 wherein the coating is provided on the perigraft, as opposed to luminal, surface of the stent cover.
27. A method according to claim 21 wherein the coating adds about 5%, or less, to the original thickness of the material used as the stent cover portion.
28. A method according to claim 21 wherein the bioactive agent used to coat the surface is itself photoderivatized.
29-30. (canceled)
31. A method of preventing endoleaking in the course of deploying and using an endovascular graft, the method comprising the steps of:
a) providing an endovascular graft comprising an expandable stent portion and a stent cover portion, wherein the stent cover portion comprises a porous, fibrous material having both an outer perigraft surface and an inner luminal surface, the cover portion having a hemostatic bioactive agent on at least the outer surface in the form of a coating covalently attached to the fibers of the material without occluding its pores, by the activation of photoreactive groups provided by the stent cover portion, by the bioactive agent, andor by a linking agent, and
b) implanting the stent in the vessel in a manner that avoids endoleaking.
32. A method according to claim 31 wherein the stent cover portion is prepared from a porous material selected from PET and ePTFE.
33. A method according to claim 31 wherein the agent is selected from the group consisting of proteins having a specific hemostatic effect, and positively charged compounds having a nonspecific hemostatic effect.
34-35. (canceled)
36. A method according to claim 31 wherein the coating is provided on the perigraft, as opposed to luminal, surface of the stent cover.
37. A method according to claim 31 wherein the coating adds about 5%, or less, to the original thickness of the material used as the stent cover portion.
38. A method according to claim 31 wherein the bioactive agent used to coat the surface is itself photoderivatized.
39-40. (canceled)
41. A method according to claim 31 wherein the agent is immobilized in an amount between about 0.05 \u03bcgcm2 to about 10 \u03bcgcm2.
42. A method according to claim 31 wherein the endovascular graft is provided in the form of a collapsed small diameter tube of on the order of two mm or less overall diameter, and can be expanded to form a larger diameter tube in situ of between about six mm and about thirty mm.
43. A method according to claim 39 wherein the bioactive agent used to coat the surface is itself photoderivatized, and is immobilized in an amount between about 0.05 \u03bcgcm2 to about 10 \u03bcgcm2, and wherein the endovascular graft is provided in the form of a collapsed small diameter tube of on the order of two mm or less overall diameter, and can be expanded to form a larger diameter tube in situ of between about six mm and about thirty mm.
44. A graft according to claim 1 wherein the bioactive agent is attached to the surface in the form of a thin, conformal coating.
45. A graft according to claim 1 wherein the coating adds no more than 25% to the original thickness of the material used as the stent cover portion.
46. A graft according to claim 1 wherein the stent cover portion is prepared from a porous material selected from PET and ePFTE.
47. A graft according to claim 1 wherein the bioactive agent is immobilized in a range of about 0.01 \u03bcgcm2 to about 50 \u03bcgcm2.
48. A graft according to claim 1 wherein the photoreactive group is provided on the bioactive agent itself.
49. A graft according to claim 1 wherein the photoreactive group is provided on at least the outer surface of the stent cover portion.
50. A graft according to claim 1 wherein the coating is provided in a manner sufficient to prevent endoleaking.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

What is claimed is:

1. A processing system comprising:
a memory controller adapted to communicate using a packet based RDRAM protocol;
a memory module comprising SDRAM devices; and
an interface device located with the memory controller such that the interface device is not located on the memory module, the interface device translates packet based RDRAM protocol command and data signals from the memory controller into an SDRAM protocol, and the interface device translates data signals received from the memory module into packet based RDRAM protocol data.
2. The processing system of claim 1 wherein the memory controller is provided in an integrated circuit chip set.
3. The processing system of claim 2 wherein the integrated circuit chip set comprises the interface device.
4. The processing system of claim 1 wherein the memory controller and interface device are provided on a motherboard.
5. A processing system comprising:
a memory controller adapted to communicate using a packet based RDRAM protocol;
a memory module comprising SDRAM devices, the memory module is located in a Memory socket; and
an interface device located between the memory controller and the Memory socket, the interface device translates packet based RDRAM protocol command and data signals from the memory controller into an SDRAM protocol, and the interface device translates data signals received from the memory module into packet based RDRAM protocol data.
6. The processing system of claim 5 wherein the memory controller and interface device are provided on a motherboard.
7. The processing system of claim 5 further comprising a second memory module comprising SDRAM devices, the second memory module is located in a second Memory socket
8. The processing system of claim 5 wherein the interface device comprises:
a write demultiplex circuit for converting data received on N data lines from the memory controller to MN data lines;
a read multiplex circuit converting received on the MN data lines from the memory module to the N data lines; and
a command disassembler for converting packet based commands from the memory controller into rowcolumn based commands.
9. A processing system comprising:
a memory controller adapted to communicate using a packet based RDRAM protocol;
a memory module comprising SDRAM devices, the memory module is located in a Memory socket; and
an interface device located between the memory controller and the Memory socket, the interface device translates packet based RDRAM protocol command and data signals from the memory controller into an SDRAM protocol, the interface device comprises:
a write demultiplex circuit for converting data received on N data lines from the memory controller to MN data lines;
a read multiplex circuit converting received on the MN data lines from the memory module to the N data lines; and
a command disassembler for converting packet based commands from the memory controller into rowcolumn based commands.
10. A processing system comprising:
a memory controller adapted to communicate using a packet based RAMBUS DRAM protocol;
a plurality of memory modules each comprising columnrow protocol based DRAM devices, the memory modules are located in in-line memory module sockets; and
a single interface device located between the memory controller and the in-line memory module socket sockets, the interface device translates packet based RAMBUS DRAM protocol command and data signals from the memory controller into the columnrow protocol, and the interface device translates data signals received from the memory modules into packet based RAMBUS DRAM protocol data.
11. A processing system motherboard comprising:
a memory controller adapted to communicate using a packet based RDRAM protocol; and
an interface device which translates packet based RDRAM protocol command and data signals from the memory controller into a columnrow DRAM protocol, and translates data signals received from a memory external to the motherboard into the packet based RDRAM protocol data.
12. The processing system motherboard of claim 11 further comprising a processor.
13. The processing system motherboard of claim 11 wherein the columnrow DRAM protocol is a columnrow SDRAM protocol.
14. A processing system chip set comprising:
a processor;
a memory controller adapted to communicate using a packet based RDRAM protocol; and
an interface device which translates packet based RDRAM protocol command and data signals from the memory controller into a columnrow DRAM protocol, and translates data signals received from an external memory into the packet based RDRAM protocol data.
15. The processing system chip set of claim 14 wherein the interface device comprises:
a write demultiplex circuit for converting data received on N data lines from the memory controller to MN data lines;
a read multiplex circuit converting received on the MN data lines from an external memory to the N data lines; and
a command disassembler for converting packet based RDRAM commands from the memory controller into the rowcolumn DRAM commands.
16. A method of operating a processing system comprising:
receiving packet based commands from a memory controller with an interface device;
translating the packet based commands into columnrow DRAM commands; and
communicating the columnrow DRAM commands to external memory, wherein a memory socket is electrically located between the interface device and the external memory.
17. The method of claim 16 further comprising:
receiving first data on N data lines from the memory controller with the interface device;
demultiplexing the first data and communicating the first data to the external memory on MN data lines;
receiving second data on the MN data lines from the external memory with the interface device; and
multiplexing the second data and communicating the second data to the memory controller on the N data lines.

1. A seed of soybean variety DLL1143, representative sample seed of said variety is deposited under ATCC Accession No. XXXX.
2. A soybean plant, or a part thereof, produced by growing the seed of claim 1.
3. A tissue culture produced from protoplasts or cells from the plant of claim 2, wherein said cells or protoplasts are produced from a plant part selected from the group consisting of leaf, pollen, ovule, embryo, cotyledon, hypocotyl, meristematic cell, root, root tip, pistil, anther, flower, seed, shoot, stem, pod and petiole.
4. A soybean plant regenerated from the tissue culture of claim 3, wherein said soybean plant has all of the physiological and morphological characteristics of the plant of claim 2.
5. A method for producing a soybean seed, comprising crossing two soybean plants and harvesting the resultant soybean seed, wherein at least one soybean plant is the soybean plant of claim 2.
6. A soybean seed produced by the method of claim 5.
7. A soybean plant, or a part thereof, produced by growing said seed of claim 6.
8. The method of claim 5, wherein at least one of said soybean plants further comprises at least one transgene.
9. A method of producing an herbicide resistant soybean plant, wherein said method comprises introducing a gene conferring herbicide resistance into the plant of claim 2.
10. A herbicide resistant soybean plant produced by the method of claim 9, wherein the gene confers resistance to a herbicide selected from the group consisting of glyphosate, sulfonylurea, imidazolinone, dicamba, glufosinate, phenoxy proprionic acid, L-phosphinothricin, cyclohexone, cyclohexanedione, triazine, benzonitrile, an N-(tetrazol-4-yl)- or N-(triazol-3-yl)arylcarboxamide, an N-(1,2,5-oxadiazol-3-yl)benzamide, tembotrione, sulcotrione, topramezone, bicyclopyrone, tefuryltrione, isoxaflutole, pyrasulfotole, and mesotrione.
11. A method of producing a pest or insect resistant soybean plant, wherein said method comprises introducing a gene conferring pest or insect resistance into the soybean plant of claim 2.
12. A pest or insect resistant soybean plant produced by the method of claim 11.
13. The soybean plant of claim 12, wherein the gene encodes a Bacillus thuringiensis (Bt) endotoxin.
14. A method of producing a disease resistant soybean plant, wherein said method comprises introducing a gene which confers disease resistance into the soybean plant of claim 2.
15. A disease resistant soybean plant produced by the method of claim 14.
16. A method of producing a soybean plant with modified fatty acid metabolism or modified carbohydrate metabolism, wherein the method comprises introducing a gene encoding a protein selected from the group consisting of phytase, fructosyltransferase, levansucrase, \u03b1-amylase, invertase and starch branching enzyme or encoding an antisense of stearyl-ACP desaturase into the soybean plant of claim 2.
17. A soybean plant having modified fatty acid metabolism or modified carbohydrate metabolism produced by the method of claim 16.
18. A method of introducing a desired trait into soybean variety DLL1143, wherein the method comprises:
(a) crossing a DLL1143 plant, wherein a representative sample of seed is deposited under ATCC Accession No. XXXX, with a plant of another soybean variety that comprises a desired trait to produce progeny plants wherein the desired trait is selected from the group consisting of male sterility, herbicide resistance, insect resistance, modified fatty acid metabolism, modified carbohydrate metabolism, modified seed yield, modified oil percent, modified protein percent, modified lodging resistance, modified shattering, modified iron-deficiency chlorosis and resistance to bacterial disease, fungal disease or viral disease;
(b) selecting one or more progeny plants that have the desired trait to produce selected progeny plants;
(c) crossing the selected progeny plants with the DLL1143 plant to produce backcross progeny plants;
(d) selecting for backcross progeny plants that have the desired trait and all of the physiological and morphological characteristics of soybean variety DLL1143 listed in Table 1; and
(e) repeating steps (c) and (d) two or more times in succession to produce selected third or higher backcross progeny plants that comprise the desired trait and all of the physiological and morphological characteristics of soybean variety DLL1143 listed in Table 1.
19. A soybean plant produced by the method of claim 18, wherein the plant has the desired trait.
20. The soybean plant of claim 19, wherein the desired trait is herbicide resistance and the resistance is conferred to an herbicide selected from the group consisting of glyphosate, sulfonylurea, imidazolinone, dicamba, glufosinate, phenoxy proprionic acid, L-phosphinothricin, cyclohexone, cyclohexanedione, triazine, benzonitrile, an N-(tetrazol-4-yl)- or N-(triazol-3-yl)arylcarboxamide, an N-(1,2,5-oxadiazol-3-yl)benzamide, tembotrione, sulcotrione, topramezone, bicyclopyrone, tefuryltrione, isoxaflutole, pyrasulfotole, and mesotrione.
21. The soybean plant of claim 19, wherein the desired trait is insect resistance and the insect resistance is conferred by a gene encoding a Bacillus thuringiensis endotoxin.
22. The soybean plant of claim 19, wherein the desired trait is modified fatty acid metabolism or modified carbohydrate metabolism and said desired trait is conferred by a nucleic acid encoding a protein selected from the group consisting of phytase, fructosyltransferase, levansucrase, \u03b1-amylase, invertase and starch branching enzyme or encoding an antisense of stearyl-ACP desaturase.
23. A method of producing a commodity plant product, comprising obtaining the plant of claim 2, or a part thereof, wherein the commodity plant product is protein concentrate, protein isolate, soybean hulls, meal, flour, or oil and producing said commodity plant product therefrom.
24. A plant, or a part thereof, obtained by vegetative reproduction from the plant, or a part thereof, of claim 2, said plant, or a part thereof, expressing all the physiological and morphological characteristics of soybean variety DLL1143.
25. A plant, or a part thereof, obtained by vegetative reproduction from the plant, or a part thereof, of claim 7, said plant, or a part thereof, expressing all the physiological and morphological characteristics of soybean variety DLL1143.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method for forming a semiconductor device comprising the steps of:
providing a region of semiconductor material having a major surface;
forming a trench extending from the major surface;
forming a first layer overlying surfaces of the trench;
forming a spacer layer adjacent the first layer, where the spacer layer comprises a material different than the first layer, where the spacer layer is discontinuous in proximity to a lower surface of the trench;
forming a first region comprising a material different than the spacer layer in proximity to the lower surface of the trench;
forming a first electrode in a lower portion of the trench and adjacent portions of the spacer layer and the first region, where portions of the first layer are between the first electrode and the region of semiconductor material;
forming a dielectric layer above the first electrode; and
forming a second electrode adjacent the first layer and the dielectric layer, where at least a portion of the second electrode is within the trench.
2. The method of claim 1 further comprising the steps of:
forming a body region adjoining the trench; and
forming a source region adjoining the body region and the trench, where the step of forming the first layer comprises forming a gate dielectric layer, and where the step of forming the first electrode includes forming a shield electrode, and where the step of forming the second electrode includes forming a gate electrode.
3. The method of claim 1, where the step of forming the spacer layer includes the steps of:
forming a third layer adjacent the first layer; and
removing a portion of the third layer in proximity to the lower surface of the trench.
4. The method of claim 3 further comprising the steps of forming a non-conformal layer overlying the major surface and adjacent the third layer before the step of removing a portion of the third layer, and where the non-conformal layer is thicker in proximity to upper surfaces of the trench.
5. The method of claim 1 further comprising the step of removing portions of the first layer underlying the spacer layer before the step of forming the first region.
6. The method of claim 1, where the step of forming the first layer includes forming a first layer comprising silicon oxide, and where the step of forming the first region includes forming the first region comprising silicon oxide.
7. The method of claim 6, where the step of forming the spacer layer comprises forming the spacer layer comprising silicon nitride.
8. The method of claim 1 further comprising the step of forming a polycrystalline semiconductor spacer layer adjacent the spacer layer before the step of forming the first region.
9. The method of claim 1 further comprising the steps of:
forming a body region adjoining the trench; and
forming a source region adjoining the body region and the trench, where the source region comprises an extension portion adjoining the trench and a central portion adjoining the extension portion, and where the central portion is shallower than the extension portion.
10. The method of claim 1, where the step of forming the first region includes forming the first region having a thickness that increases along lower sidewall surfaces of the first electrode, and, where the thickness is greatest in proximity to a lowest portion of the trench.
11. The method of claim 1, where the step of forming the first electrode includes forming the first electrode having a stepped shape such that the first electrode decreases in width and is narrower in proximity to the lower surface of the trench.
12. A method for forming a semiconductor device comprising the steps of:
providing a region of semiconductor material having a major surface;
forming a trench extending from the major surface, where the trench has sidewall surfaces and a lower surface;
forming a gate dielectric layer adjoining the sidewall surfaces and the lower surfaces;
forming first spacer layers adjacent the gate dielectric layer, where forming the first spacer layers exposes a segment of the gate dielectric layer in proximity to the lower surface;
removing portions of the first dielectric layer from the lower surface adjacent the first spacer layers and the region of semiconductor material;
forming a first dielectric region adjoining the lower surface, where the first dielectric layer is thicker than the gate dielectric layer;
forming a second dielectric layer adjacent the spacer layers;
forming a first conductive region adjacent the first dielectric region and the second dielectric layer;
forming a second dielectric region adjacent an upper surface of the first conductive region;
removing portions of the second dielectric layer and first spacer layers adjacent upper portions of the trench; and
forming a second conductive region adjacent the first dielectric layer and the second dielectric region.
13. The method of claim 12, where the step of forming the first spacer layers comprises the steps of:
forming a layer of material adjacent the first dielectric layer;
forming a non-conformal layer of material adjacent the layer of material, where the non-conformal layer is thicker in proximity to upper portions of the trench; and
removing portions of the non-conformal layer and the layer of material in proximity to the lower surface.
14. The method of claim 13, where the step of forming the layer of material comprises forming a silicon nitride layer having a thickness of about 0.01 microns to about 0.05 microns, and where step of forming the non-conformal layer of material comprises depositing a silicon oxide using PECVD with a silane source gas.
15. The method of claim 12, where the step of forming the first spacer layers comprises the steps of:
forming a layer of material adjacent the first dielectric layer;
forming polycrystalline semiconductor spacers adjacent the layer of material; and
removing portions of the layer of material in proximity to the lower surface.
16. The method of claim 12, where the step of removing portions of the first dielectric layer from the lower surface adjacent the first spacer layers and the region of semiconductor material comprises removing portions of the first dielectric layer adjacent lower sidewall surfaces of the trench to form undercut portions, and where the step of forming the first dielectric region comprises forming the first dielectric region within the undercut portions and adjacent the lower sidewall surfaces, and where the step of forming the first conductive region comprises forming a shield electrode, and where the step of forming the second conductive region comprising forming a gate electrode, and where the method further comprises the steps of:
forming a body region adjacent the trench; and
forming a source region within the body region and adjacent trench.
17. A method for forming a semiconductor device comprising:
providing a region of semiconductor material having a major surface;
forming a trench extending from the major surface;
forming a first layer overlying surfaces of the trench;
forming a spacer layer adjacent the first layer, where the spaces layer comprises a material different than the first layer;
removing portions of the first layer underlying the spacer layer to form undercut portions between the region semiconductor material and the spacer layer;
forming a first region comprising a material different than the spacer layer in proximity to a lower surface of the trench and within the undercut portions;
forming a first electrode in a lower portion of the trench and adjacent portions of the spacer layer and the first region;
forming a dielectric layer above the first electrode; and
forming a second electrode adjacent the first layer and the dielectric layer, where at least a portion of the second electrode is within the trench.
18. The method of claim 1 further comprising:
forming a body region adjoining the trench; and
forming a source region adjoining the trench and a central portion adjoining the extension portion, and where the central portion is shallower than the extension portion, and where forming the first layer comprises forming a gate dielectric layer, and where forming the first electrode includes forming a shield electrode having a stepped shape such that the first electrode decreases in width and is narrower in proximity to the lower surface of the trench, and where forming the second electrode includes forming a gate electrode.
19. The method of claim 1, where forming the spacer layer includes:
forming a second layer adjacent the first layer;
forming a non-conformal layer overlying the major surface and adjacent the second layer, where the non-conformal layer is thicker in proximity to upper surfaces of the trench;
removing portions of the non-conformal layer and second layer in proximity to the lower surface of the trench.
20. The method of claim 17 further comprising forming a polycrystalline semiconductor spacer layer adjacent the spacer layer before forming the first region.
21. A method for forming a semiconductor device comprising:
providing a region of semiconductor material having a major surface and a trench extending from the major surface;
forming a first dielectric layer overlying surfaces of the trench;
forming a second dielectric layer adjacent the first dielectric layer, wherein the second dielectric layer comprises a material different than the first dielectric layer, and where the second dielectric layer is discontinuous in proximity to the lower surface of the trench;
removing portions of the first dielectric layer underlying the second dielectric layer to form undercut portions between the region of semiconductor material and the spacer layer;
forming a dielectric region in proximity to a lower surface of the trench and within the undercut portions, wherein at least portions of the first dielectric layer, the second dielectric layer and the dielectric region are configured as a shield isolation structure;
forming a shield electrode on the shield isolation structure; and
forming an insulated gate electrode in the trench above the shield electrode.
22. The method of claim 21, further comprising forming a third dielectric layer in the trench, wherein the third dielectric separates at least in part the shield electrode from the second dielectric layer.