1. An instruction for execution on a microprocessor configured to execute concurrent program threads, the instruction comprising:
an opcode, for instructing the microprocessor to allocate resources for a new thread and to schedule execution of said new thread on the microprocessor, said resources comprising a program counter and a register set;
a first operand, for specifying an initial instruction fetch address to be stored into said program counter allocated for said new thread; and
a second operand, for provision to said new thread.
2. The instruction of claim 1, wherein said second operand is provided to said new thread for storage in a register of said register set allocated for said new thread.
3. The instruction of claim 1, wherein the microprocessor raises an exception to the instruction if said resources for said new thread are not available for allocation when the microprocessor executes the instruction.
4. The instruction of claim 1, further comprising:
a third operand, for specifying one of a plurality of storage locations associated with said new thread into which said second operand is to be stored.
5. The instruction of claim 4, wherein said register set comprises a plurality of general purpose registers, wherein said one of said plurality of storage locations specified by said third operand comprises one of said plurality of general purpose registers of said register set allocated for said new thread.
6. The instruction of claim 4, wherein said register set comprises a stack pointer register for specifying a stack memory, wherein said one of said plurality of storage locations specified by said third operand comprises a storage location in said stack memory.
7. The instruction of claim 1, wherein a size of state initially required by said new thread exceeds a size of said second operand, wherein one or more instructions subsequent to the instruction execute to copy said state to said register set allocated to said new thread based on said second operand, rather than the microprocessor automatically copying said state from a register set of a thread including the instruction to said register set allocated to said new thread in response to the instruction.
8. The instruction of claim 1, wherein the microprocessor foregoes copying a contents from a register set of a thread including the instruction to said register set allocated to said new thread in response to the instruction.
9. The instruction of claim 1, wherein said second operand specifies an address in memory of data for use by said new thread.
10. The instruction of claim 1, wherein the instruction occupies a single instruction issue slot in the microprocessor.
11. The instruction of claim 1, wherein the instruction is executable by the microprocessor at a user privilege level.
12. An instruction for execution on a microprocessor configured to execute concurrent program threads, the instruction comprising:
an opcode, for instructing the microprocessor to allocate resources for a new thread and to schedule execution of said new thread on the microprocessor, said resources comprising a program counter and a register set; and
an operand, for specifying an initial instruction fetch address to be stored into said program counter allocated for said new thread;
wherein the microprocessor raises an exception to the instruction if said resources for said new thread are not available for allocation when the microprocessor executes the instruction.
13. The instruction of claim 12, further comprising:
a second operand, for provision to said new thread.
14. The instruction of claim 12, wherein the instruction occupies a single instruction issue slot in the microprocessor.
15. The instruction of claim 12, wherein the instruction is executable by the microprocessor at a user privilege level.
16. A multithreaded microprocessor, comprising:
a plurality of thread contexts, each configured to store a state of a thread and to indicate whether said thread context is available for allocation; and
a scheduler, coupled to said plurality of thread contexts, for allocating one of said plurality of thread contexts to a new thread and scheduling said new thread for execution, in response to a single instruction in a currently executing thread;
wherein the microprocessor takes an exception to said single instruction if none of said plurality of thread contexts is available for allocation.
17. The microprocessor of claim 16, wherein each of said plurality of thread contexts comprises a program counter.
18. The microprocessor of claim 17, wherein said single instruction instructs the microprocessor to store a first operand of said instruction to said program counter of said one of said plurality of thread contexts allocated to said new thread.
19. The microprocessor of claim 18, wherein said single instruction instructs the microprocessor to store a second operand of said instruction into a storage location accessible by said new thread.
20. The microprocessor of claim 19, wherein each of said plurality of thread contexts comprises a plurality of general purpose registers, wherein said single instruction instructs the microprocessor to store said second operand into one of said plurality of general purpose registers of said one of said plurality of thread contexts allocated to said new thread.
21. The microprocessor of claim 20, wherein said one of said plurality of general purpose registers is specified by a third operand of said instruction.
22. The microprocessor of claim 19, wherein each of said plurality of thread contexts comprises a stack pointer register for specifying a stack memory, wherein said single instruction instructs the microprocessor to store said second operand into a location in said stack memory.
23. The microprocessor of claim 22, wherein said location in said stack memory is specified by a third operand of said instruction.
24. The microprocessor of claim 16, wherein the microprocessor allows said instruction to allocate one of said plurality of thread contexts for said new thread and to schedule said new thread for execution even if said currently executing thread is executing at a user privilege level.
25. The microprocessor of claim 16, wherein said instruction occupies a single instruction issue slot in the microprocessor.
26. The microprocessor of claim 16, wherein each of said register sets comprises two read ports and one write port.
27. The microprocessor of claim 16, wherein said fork instruction specifies at most two source register operands and one destination register operand.
28. A multithreaded microprocessor, comprising:
a first program counter, for storing a fetch address of an instruction in a first program thread;
a first register set, including first and second registers specified by said instruction for storing first and second operands, respectively, said first operand specifying a fetch address of a second program thread;
a second program counter, coupled to said first register set, for receiving said first operand from said first register in response to said instruction;
a second register set, coupled to said first register set, including a third register, for receiving said second operand from said second register in response to said instruction; and
a scheduler, coupled to said first and second register set, for causing the microprocessor to fetch and execute instructions from said second program thread fetch address stored in said second program counter in response to said instruction.
29. The microprocessor of claim 28, further comprising:
an exception indicator, coupled to said scheduler, for causing the microprocessor to take an exception to said instruction if said second program counter and register set are not available for receiving said first and second operands in response to said instruction.
30. The microprocessor of claim 28, further comprising:
an exception indicator, coupled to said scheduler, for causing the microprocessor to take an exception to said instruction if said second program counter and register are already in use by another thread in response to said instruction.
31. The microprocessor of claim 28, wherein said third register is specified by said instruction.
32. The microprocessor of claim 28, wherein said first and second registers sets comprise general purpose register sets, wherein in response to said instruction said second general purpose register set receives only said second operand from said first general purpose register set.
33. A method for creating a new thread of execution on a multithreaded microprocessor, the method comprising:
decoding a single instruction executing in a first program thread;
allocating for a second program thread a program counter and register set of the microprocessor, in response to said decoding;
storing a first operand of the instruction into a register of the register set, in response to said allocating;
storing a second operand of the instruction into the program counter, in response to said allocating; and
scheduling the second program thread for execution on the microprocessor, after said storing said first and second operand.
34. The method of claim 33, further comprising:
determining whether a program counter and register set is available for allocation, in response to said decoding.
35. The method of claim 34, further comprising:
raising an exception to the instruction if no program counter and register set is available for allocation.
36. The method of claim 33, wherein said allocating, said storing the first and second operands, and said scheduling are all performed in a single clock cycle of the microprocessor.
37. A method for creating a new thread of execution on a multithreaded microprocessor, the method comprising:
decoding a single instruction executing in a first program thread;
allocating for a second program thread a program counter, in response to said decoding;
determining whether said allocating was successful;
storing an operand of the instruction into the program counter and scheduling the second program thread for execution on the microprocessor, if said allocating was successful; and
raising an exception to the instruction, if said allocating was not successful.
38. The method of claim 37, further comprising:
providing a second operand of the instruction to the second thread, if said allocating was successful.
39. The method of claim 38, further comprising:
allocating a register set for the second program thread, in response to said decoding;
wherein said providing the second operand of the instruction to the second thread comprises storing the second operand into a register of said register set allocated for the second program thread.
40. The method of claim 38, further comprising:
allocating a stack pointer for the second program thread, in response to said decoding, the stack pointer specifying a stack memory associated with the second thread;
wherein said providing the second operand of the instruction to the second thread comprises storing the second operand into the stack memory.
41. A multithreaded processing system, comprising:
a memory, configured to store a fork instruction of a first thread and a data structure, said fork instruction specifying a register storing a memory address of said data structure and an initial instruction address of a second thread, said data structure including initial general purpose register values of said second thread; and
a microprocessor, coupled to said memory, configured to: (1) allocate a free thread context for said second thread, (2) store said second thread initial instruction address into a program counter of said thread context, (3) store said data structure memory address into a register of said thread context, and (4) schedule said second thread for execution, in response to said fork instruction.
42. The processing system of claim 41, wherein a number of said initial register values of said second thread included in said data structure is fewer than a number of general purpose registers of said thread context.
43. The processing system of claim 41, wherein said thread context allocated to said second thread is distinct from a thread context of said first thread.
44. The processing system of claim 43, wherein said memory is further configured to store program instructions of said second thread for copying said initial register values of said data structure from said memory into general purpose registers of said thread context, thereby enabling said microprocessor to forego copying the entire thread context of said first thread to said thread context of said second thread in response to said fork instruction.
45. The processing system of claim 41, wherein said microprocessor is further configured to raise an exception to said fork instruction if no free thread context is available for allocation to said second thread.
46. A computer program product for use with a computing device, the computer program product comprising:
a computer usable medium, having computer readable program code embodied in said medium, for causing a multithreaded microprocessor, said computer readable program code comprising:
first program code for providing a first program counter, for storing a fetch address of an instruction in a first program thread;
second program code for providing a first register set, including first and second registers specified by said instruction for storing first and second operands, respectively, said first operand specifying a fetch address of a second program thread;
third program code for providing a second program counter, coupled to said first register set, for receiving said first operand from said first register in response to said instruction;
fourth program code for providing a second register set, coupled to said first register set, including a third register, for receiving said second operand from said second register in response to said instruction; and
fifth program code for providing a scheduler, coupled to said first and second register set, for causing the microprocessor to fetch and execute instructions from said second program thread initial fetch address stored in said second program counter in response to said instruction.
47. The computer program product of claim 46, wherein said computer readable program code further comprises:
sixth program code for providing a status register, for receiving an address space identifier from said second program thread, in response to said instruction.
48. The computer program product of claim 46, wherein said computer readable program code further comprises:
sixth program code for providing a status register, for receiving an execution privilege level identifier from said second program thread, in response to said instruction.
49. A computer data signal embodied in a transmission medium, comprising:
computer-readable program code for providing a multithreaded microprocessor for executing a fork instruction, said program code comprising:
first program code for providing an opcode, for instructing the microprocessor to allocate resources for a new thread and to schedule execution of said new thread on the microprocessor, said resources comprising a program counter and a register set;
second program code for providing a first operand, for specifying an initial instruction fetch address to be stored into said program counter allocated for said new thread; and
third program code for providing a second operand, for storing in a register of said register set allocated for said new thread.
50. The computer data signal of claim 49, wherein said computer readable program code further comprises:
fourth program code for providing a third operand for specifying which said register of said register set said second operand is to be stored into.
51. The computer data signal of claim 49, wherein said computer readable program code further comprises:
fourth program code for providing a status register associated with said register set allocated for said new thread, wherein said status register includes an indicator for indicating whether said register set has been written to since allocation for said new thread.
52. The computer program product of claim 49, wherein said computer readable program code further comprises:
fourth program code for providing an exception indicator, for raising an exception to the fork instruction if no program counter and register set are free for allocation to said new thread.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1-12. (canceled)
13. A multi-speed transmission (1), of countershaft design for a double clutch transmission, having a main countershaft (9) and a hollow countershaft (12) arranged concentrically thereto, and having two load-shift elements (2, 3), in which a first half of the load-shift elements (2, 3) is in active connection with a drive unit and a second half of the load-shift elements (2,3) is connected to a gearbox input shaft (5, 6), respectively, and in which the gearbox input shafts (5, 6); the countershafts (9, 12) are mounted in a housing (16) and are actively connected to gear wheels (7, 8, 9B to 9E, 10, 11, 12A, 13A to 13E), which respectively intermesh in pairs as gear wheel pairs (ZP1 to ZP7) and can be either connected or disconnected in order to reduce an overall gear ratio of a power flow, the main countershaft (9) is mounted directly on the housing (16) via a first bearing mechanism (15) in an area of a first end and in a hollow countershaft (12) via a second bearing mechanism (17) and a third bearing mechanism (18) in an area of a second end, while the hollow countershaft (12) is mounted directly in the housing (16) via a fourth bearing mechanism (19) in an area end that faces toward an end of the main countershaft (12) that is mounted in the hollow countershaft (9).
14. The multi-speed transmission according to 13, wherein the first bearing mechanism (15) and the fourth bearing mechanism (19) are fixed bearings and the second bearing mechanism (17) and the third bearing mechanism (18) are floating bearings.
15. The multi-speed transmission according to 13, wherein the first bearing mechanism (15) is a fixed bearing and the second bearing mechanism (17), the third bearing mechanism (18), and the fourth bearing mechanism (19) are all floating bearings.
16. The multi-speed transmission according to 15, wherein the hollow countershaft (12) is additionally supported in an axial direction on the main countershaft (9) via two thrust bearing mechanisms (20, 21).
17. The multi-speed transmission according to 15, wherein the hollow countershaft is additionally supported in an axial direction on the housing via two thrust bearing mechanisms.
18. The multi-speed transmission according to 13, wherein the first bearing mechanism (15), the second bearing mechanism (17), and the fourth bearing mechanism (19) are respectively configured as a bearing that support loads that act in a radial direction and in a defined axial direction.
19. The multi-speed transmission according to 18, wherein the first bearing mechanism (15) is configured so that axial forces that act in a direction of an end of the main countershaft (9) that is directly mounted on the housing (16) can be supported in the housing (16) via the first bearing mechanism (15).
20. The multi-speed transmission according to 18, wherein the fourth bearing mechanism (19) is configured so that axial forces acting in a direction of an end of the main countershaft (9) mounted in the hollow countershaft (12) can be supported in the housing (16) via the fourth bearing mechanism (19).
21. The multi-speed transmission according to claim 18, wherein the second bearing mechanism (17) is configured so that the axial forces that act respectively on one of the main countershaft (9) or the hollow countershaft (12) can be conducted via the second bearing mechanism (17) to one of the hollow countershaft (12) or the main countershaft (9), respectively.
22. The multi-speed transmission according to claim 18, wherein the third bearing mechanism (18) is a floating bearing.
23. The multi-speed transmission according to claim 13, wherein the hollow countershaft (12) is actively connected via a second gear wheel pair (ZP2) directly to a main gearbox input shaft (5) and the main countershaft (9) is in active connection via a first gear wheel pair (ZP1) directly with a hollow gearbox input shaft (6).
24. The multi-speed transmission according to claim 13, wherein a gearbox output shaft (13) is arranged coaxially with respect to the gearbox input shaft (5, 6).