1. A microprocessor for executing byte-compiled Java code as hardware, the microprocessor comprising:
a processor core with an associated processor control unit configurable to execute a first set of Java instructions in the processor core when in a Java state and to execute both native instructions and a second set of Java instructions as native microcode in the processor core when in a native processor state, the processor control unit responsive to processor state control information contained in a system status register that designates the processor state at any given time;
a register file in a data path of the processor core and including a plurality of register elements, the register file accessible by the processor control unit by means of register addresses specified by either Java or native microcode instructions;
a Java operand stack pointer register that contains information pointing to a register element in the register file which is the current top of a Java operand stack; and
a register remap unit for each register access port of the register file and coupled to the processor control unit to receive instruction-specified register addresses therefrom and coupled to the register access ports to supply physical address values of register elements in the register file therefore;
wherein register addresses specified by native microcode executing Java instructions of the second set are remapped by the register remap unit as corresponding physical addresses relative to the current top of the Java operand stack.
2. The microprocessor as in claim 1 wherein said native processor state is a RISC state, the native instructions are RISC instructions, and the native microcode for executing the second set of Java instructions are RISC microcode.
3. A microprocessor for executing byte-compiled Java code as hardware, the microprocessor comprising:
a processor core;
a Java control module to execute a first set of Java instructions in the processor core;
a native control module to execute native instructions in the processor core and to execute a second set of Java instructions in the processor core as native microcode;
a set of system registers accessible to said Java and native control modules, including a status register containing processor state control information designating which one of said control modules is operative at any given time; and
a register file in a data path of the processor core and accessible by both control modules, said register file including a plurality of register elements, the native control module viewing the plurality of register elements as storage registers, the Java control module viewing a first portion of the register elements as a Java operand stack and a second portion of the register elements as storage registers;
wherein the set of system registers also includes a Java operand stack pointer that points to that register element in the register file which is current top of the stack, and the status register also contains a Java register remap bit, such that whenever the remap bit is set, the native control module executing Java instructions of the second set as native microcode treats register numbers specified by instructions in the native microcode as corresponding to a specified register element relative to the top of the stack.
4. The microprocessor as in claim 3, such that whenever the remap bit is set, the corresponding register relative to the top of the stack that is accessed by a native microcode instruction is the maximum value of the operand stack pointer minus the register number specified by the Java operand stack pointer.
5. The microprocessor as in claim 3, such that whenever the remap bit has been reset, the native control module treats register numbers specified by native instructions as designating a corresponding storage element of the register file.
6. The microprocessor as in claim 3, wherein the remap bit is disregarded by the Java control module.
7. The microprocessor as in claim 3, wherein Java instructions of the second set are more complex than those of the first set, the instructions of the second set being incapable of being executed in the processor core within one clock cycle.
8. The microprocessor as in claim 7, wherein the second set of Java instructions includes instructions for creating and manipulating Java objects.
9. The microprocessor as in claim 7, wherein the second set of Java instructions includes instructions that operate upon long and floating-point data types.
10. The microprocessor as in claim 7, wherein the second set of Java instructions include double-type instructions.
11. The microprocessor as in claim 3, wherein the processor core is a RISC processor, the native instructions are RISC instructions, and the native microcode for implementing the second set of Java instructions are RISC microcode.
12. The microprocessor as in claim 3, wherein the register file includes, as one of the register elements, a program counter containing a memory address of an instruction to be executed.
13. The microprocessor as in claim 3, wherein the register file includes, as one of the register elements, a link register containing a return address for execution after completion of a subprogram call.
14. The microprocessor as in claim 3, wherein the register file includes, as one of the register elements, a native stack pointer to point to a temporary memory location for accessing local variables whenever the register file is full.
15. The microprocessor as in claim 3, wherein the set of system registers includes Java local variable registers in the data path of the processor core and accessible by the Java control module for temporary storage of Java local variables and parameters outside of said Java operand stack.
16. The microprocessor as in claim 3, wherein the set of system registers includes a Java trap base-address register containing a memory base address to microcode for the second set of Java instructions.
17. A method of executing Java instructions in a microprocessor, wherein a subset of said Java instructions is executed as microcode in a native processor state, the method comprising:
(a) providing a processor control unit to control execution by said microprocessor of native instructions in the native processor state, of a first subset of Java instructions in a Java processor state, and of a second subset of Java instructions as native microcode in the native processor state, the processor control unit responding to processor state control information contained in a system status register that designates the processor state at any given time, the microprocessor having a register file in a data path thereof, a Java operand stack pointer, and a register remap unit, all accessible to the processor control unit, the register file including a plurality of register elements accessed by register addresses specified by any of the instructions;
(b) executing a first set of Java instructions by the microprocessor in a Java state until the processor control unit recognizes a second subset Java instruction;
(c) upon recognizing any second subset Java instruction, switching the microprocessor to a native processor state and executing native microcode corresponding to said second subset Java instruction, such that registers specified by instructions of the native microcode are remapped by the register remap unit relative to a current top-of-stack location designated by the Java operand stack pointer;
(d) upon completion of the native microcode for the second subset Java instruction, returning the microprocessor to the Java state and resuming execution of Java instructions; and
(e) repeating steps (b) through (d) until the completion of all Java instructions.
18. The method of claim 17 further comprising executing in a native processor state any native instructions other than native microcode corresponding to second subset Java instructions such that registers addresses specified by any such other native instructions directly correspond to the register elements indicated by such addresses without remapping.
19. The method of claim 17 wherein executing native microcode corresponding to a second subset Java instruction includes accessing the microcode from a memory by the processor control unit, the accessing including applying an offset specified for that particular second subset Java instruction to a Java-trap base address contained in a register accessible to the processor control unit to obtain an offset address indicating a memory location where the corresponding microcode begins.
20. The method of claim 17 wherein the microprocessor is a RISC processor with its native state being a RISC state, the native instructions being RISC instructions and the native microcode being RISC microcode.
21. A method of executing Java instructions in a microprocessor, wherein a subset of said Java instructions is executed as microcode native to said microprocessor, the method comprising:
(a) providing a Java control module to control direct execution by said microprocessor of a first subset of Java instructions, and a native control module to control direct execution by said microprocessor of native instructions, the native control module also controlling execution of a second subset of Java instructions as native microcode, the microprocessor having a register file in a data path of the microprocessor and a set of system registers, both accessible by said Java and native control modules, the register file including a plurality of register elements, such that the native control module views the plurality of register elements as storage registers and the Java control module views a first portion of the register elements as a Java operand stack and the second portion of the register elements as storage registers, the set of system registers including a Java operand stack pointer that points to a register element in the register file that which is a current top of the stack, the set of system registers also including a status register containing a Java register remap bit;
(b) executing a first set of Java instructions by the microprocessor under control of the Java control module until a Java instruction of the second set is recognized;
(c) upon recognizing a Java instruction of the second set, accessing corresponding native microcode for that Java instruction, setting the Java register remap bit, turning operation over to the native control unit, and executing the native microcode, such that, when executing native instructions in said microcode, registers specified by those native instructions are treated as corresponding to a specified register element of the register file that is relative to the current top of the stack;
(d) upon completion of the microcode for the Java instruction of the second set, returning operation to said Java control unit and resuming execution at the next Java instruction; and
(e) repeating steps (b) through (d) until the completion of all Java instructions.
22. The method of claim 21, wherein turning operation over to the native control unit and returning operation to the Java control unit are mediated by processor state control information in the status register.
23. The method of claim 21, wherein the set of system registers includes a Java trap base-address register containing a memory base address to the native microcode, and accessing the corresponding native microcode for a particular Java instruction of the second set involves applying an offset specified for that instruction to the base address and then accessing memory at the resulting offset address.
24. The method of claim 21, such that whenever the remap bit is set, the corresponding register relative to the top of the stack which is accessed by the native microcode instruction is the maximum value of the operand stack pointer minus the register number specified by the Java operand stack pointer.
25. The method of claim 21, wherein Java instructions of the second set are more complex than those of the first set, the instructions of the second set being incapable of being executed by the microprocessor within one clock cycle as atomic instructions.
26. The method of claim 25, wherein the second set of Java instructions includes instructions for creating and manipulating Java objects.
27. The method of claim 26, wherein the second set of Java instructions includes instructions that operate upon long and floating-point data types.
28. The method of claim 27, wherein the second set of Java instructions includes double-type instructions.
29. The method of claim 28, wherein the microprocessor is a RISC processor, the native instructions are RISC instructions, and the native microcode for implementing the second set of Java instructions are RISC microcode.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A vehicular rotatable lamp unit comprising:
a main seat adapted to be mounted on a vehicle;
a lamp seat assembly connected pivotally to said main seat;
a conducting wire having a first end connected electrically to said lamp seat assembly, and a second end opposite to said first end;
a first contact assembly mounted on said main seat, and including a first contact member connected electrically to said second end of said conducting wire and movable along with said lamp seat assembly to rotate relative to said main seat;
a second contact assembly adapted to be connected to a power source of the vehicle, and including a second contact member contacting directly said first contact member, said second contact member being mounted on said main seat and being nonrotatable relative to said main seat; and
an electrical wire connected to said second contact member and adapted to be connected to the power source of the vehicle;
wherein said first contact member is rotatable relative to said second contact member; and
wherein said second contact assembly further includes a resilient arm having one end mounted on said main seat and another end connected to said second contact member to press said second contact member against said first contact member so as to maintain electrical connection between said first and second contact members, said second contact member being nonrotatable relative to said resilient arm.
2. The vehicular rotatable lamp unit as claimed in claim 1, wherein said second contact assembly further includes a second contact holder connected to said another end of said resilient arm, said second contact member being welded to said second contact holder.
3. The vehicular rotatable lamp unit as claimed in claim 2, wherein said electrical wire is fastened to said second contact holder to form an electrical connection with said second contact member.
4. The vehicular rotatable lamp unit as claimed in claim 1, wherein said main seat includes top and bottom plates, said lamp seat assembly including a lamp seat holder having top and bottom horizontal plates pivoted respectively to said top and bottom plates of said main seat, and two curved plates interconnecting said top and bottom horizontal plates of said lamp seat holder.
5. The vehicular rotatable lamp unit as claimed in claim 4, wherein said first contact assembly further includes a first contact holder connected to said lamp seat holder and having a top cavity, and a hollow insulation seat disposed within said top cavity, said first contact holder having a bottom flange fixed to said bottom horizontal plate of said lamp seat holder, said insulation seat having a top recess, said first contact member being received in said top recess.