1. A honeycomb structure comprising a plurality of honeycomb segments having porous partition walls separating and forming a plurality of cells functioning as fluid passages and an outer peripheral wall located in the outermost periphery, the cells including first cells each open in an end portion on one side and plugged in the other end portion on the other side and second cells each plugged in the end portion on the one side and open in the other end portion on the other side, and the first cells and the second cells being alternately disposed with the first cells having an area larger than that of the second cells in a cross section perpendicular to the central axial direction;
wherein the outer peripheral wall has protruding portions along an external shape of the first cells and depressed portions along an external shape of the second cells,
the honeycomb segments are disposed with side faces thereof facing each other and bonded to each other with a bonding member at the side faces facing each other, and
a distance between the depressed portions on adjacent side faces that are bonded to each other is equal to two times a height of the protruding portions plus a distance between the protruding portions of the adjacent side faces.
2. The honeycomb structure according to claim 1, wherein the protruding portions of the outer peripheral wall has a height of 0.1 to 1.0 mm based on the depressed portions of the outer peripheral wall.
3. The honeycomb structure according to claim 1, wherein, in a pair of side faces facing each other of adjacent honeycomb segments, the distance from the depressed portion of one of the side faces to the depressed portion of the other side face is 0.3 to 3.0 mm.
4. The honeycomb structure according to claim 2, wherein, in a pair of side faces facing each other of adjacent honeycomb segments, the distance from the depressed portion of one of the side faces to the depressed portion of the other side face is 0.3 to 3.0 mm.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A design data creating method of creating design data of a semiconductor device, comprising:
extracting an AND region of an upper layer wiring pattern and a lower layer wiring pattern that sandwich a contact hole layer pattern included in a pattern layer;
extracting the contact hole layer pattern included in the AND region; and
moving, by a computer, the contact hole layer pattern in such a manner that a center of the AND region coincides with a center of the contact hole layer pattern.
2. The method according to claim 1, wherein the AND region is extracted after increasing widths of the upper layer wiring pattern and the lower layer wiring pattern that sandwich the contact hole layer pattern included in the pattern layer.
3. The method according to claim 1, wherein the AND region is extracted by using a Boolean operation.
4. The method according to claim 1, wherein at least one of the upper layer wiring pattern and the lower layer wiring pattern is a metal wiring pattern.
5. A design data creating method of creating design data of a semiconductor device, comprising:
extracting an AND region of an upper layer wiring pattern and a lower layer wiring pattern that sandwich a contact hole layer pattern included in a pattern layout;
extracting the contact hole layer pattern included in the AND region; and
moving, by a computer, the contact hole layer pattern in such a manner that the contact hole layer pattern approximates a center of the AND region on a maximum level to satisfy predetermined design restrictions.
6. The method according to claim 5, wherein the AND region is extracted after increasing widths of the upper layer wiring pattern and the lower layer wiring pattern that sandwich the contact hole layer pattern included in the pattern layer.
7. The method according to claim 5, wherein the AND region is extracted by using a Boolean operation.
8. The method according to claim 5, wherein at least one of the upper layer wiring pattern and the lower layer wiring pattern is a metal wiring pattern.
9. A design data creating method of creating design data of a semiconductor device, comprising:
simulating a pattern shape of each of an upper layer wiring pattern and a lower layer wiring pattern that sandwich a contact hole layer pattern included in a pattern layout under a plurality of process conditions considering a predetermined process error;
determining a process condition under which a contact area of the upper layer wiring pattern, the lower layer wiring pattern, and the contact hole layer pattern becomes minimum from the plurality of process conditions based on a result of the simulation;
extracting an AND region of a simulated shape of the upper layer wiring pattern and a simulated shape of the lower layer wiring pattern under the determined process condition;
obtaining a gravity point of the AND region; and
moving, by a computer, the contact hole layer pattern in such a manner that the gravity point of the AND region coincides with a center of the contact hole layer pattern.
10. The method according to claim 9, further comprising:
increasing widths of the upper layer wiring pattern and the lower layer wiring pattern that sandwich the contact hole layer pattern included in the pattern layer, thereafter performing an optical proximity effect correction with respect to the processed pattern, thereby determining a pattern shape to perform the simulation.
11. The method according to claim 9, wherein the AND region is extracted by using a Boolean operation.
12. The method according to claim 9, wherein at least one of the upper layer wiring pattern and the lower layer wiring pattern is a metal wiring pattern.
13. A computer storage medium comprising a program that, when executed by a computer, causes the computer to execute:
extracting an AND region of an upper layer wiring pattern and a lower layer wiring pattern that sandwich a contact hole layer pattern included in a pattern layout of a semiconductor device;
extracting the contact hole layer pattern included in the AND region; and
moving the contact hole layer pattern in such a manner that a center of the AND region coincides with a center of the contact hole layer pattern, thereby creating design data of the semiconductor device.
14. A computer storage medium comprising a program that, when executed by a computer, causes the computer to execute:
extracting an AND region of an upper layer wiring pattern and a lower layer wiring pattern that sandwich a contact hole layer pattern included in a pattern layout;
extracting the contact hole layer pattern included in the AND region; and
moving the contact hole layer pattern in such a manner that the contact hole layer pattern approximates a center of the AND region on a maximum level to satisfy predetermined design restrictions.
15. A computer storage medium comprising a program that, when executed by a computer, causes the computer to execute:
simulating a pattern shape of each of an upper layer wiring pattern and a lower layer wiring pattern that sandwich a contact hole layer pattern included in a pattern layout under a plurality of process conditions considering a predetermined process error;
determining a process condition under which a contact area of the upper layer wiring pattern, the lower layer wiring pattern, and the contact hole layer pattern becomes minimum from the plurality of process conditions based on a result of the simulation;
extracting an AND region of a simulated shape of the upper layer wiring pattern and a simulated shape of the lower layer wiring pattern under the determined process condition;
obtaining a gravity point of the AND region; and
moving the contact hole layer pattern in such a manner that the gravity point of the AND region coincides with a center of the contact hole layer pattern.
16. A manufacturing method of a semiconductor device for forming a pattern on a semiconductor substrate by using a photomask, the photomask being manufactured by using design data of the semiconductor device created by:
extracting an AND region of an upper layer wiring pattern and a lower layer wiring pattern that sandwich a contact hole layer pattern included in a pattern layout;
extracting the contact hole layer pattern included in the AND region; and
moving, by a computer, the contact hole layer pattern in such a manner that a center of the AND region coincides with a center of the contact hole layer pattern.
17. A manufacturing method of a semiconductor device for forming a pattern on a semiconductor substrate by using a photomask, the photomask being manufactured by using design data of the semiconductor device created by:
extracting an AND region of an upper wiring pattern and a lower wiring pattern that sandwich a contact hole layer pattern included in a pattern layout;
extracting the contact hole layer pattern included in the AND region; and
moving, by a computer, the contact hole layer pattern in such a manner that the contact hole layer pattern approximates a center of the AND region on a maximum level to satisfy predetermined design restrictions.
18. A manufacturing method of a semiconductor device for forming a pattern on a semiconductor substrate by using a photomask, the photomask being manufactured by using design data of the semiconductor device created by:
simulating a pattern shape of each of an upper wiring pattern and a lower wiring pattern that sandwich a contact hole layer pattern included in a pattern layout under a plurality of process conditions considering a predetermined process error;
determining a process condition under which a contact area of the upper wiring pattern, the lower wiring pattern, and the contact hole layer pattern becomes minimum from the plurality of process conditions based on a result of the simulation;
extracting an AND region of a simulated shape of the upper wiring pattern and a simulated shape of the lower wiring pattern under the determined process condition;
obtaining a gravity point of the AND region; and
moving, by a computer, the contact hole layer pattern in such a manner that the gravity point of the AND region coincides with a center of the contact hole layer pattern.