What is claimed is:
1. A process for labeling with signal amplification a ribonucleic acid (RNA), comprising:
fragmenting the RNA to form RNA fragments,
fixing a first ligand to a terminal phosphate located at least one of the 3 end and the 5 end of each of a plurality of said RNA fragments, said terminal phosphate having been released during the fragmentation, and
binding a plurality of labeling agents to said first ligand on each of a plurality of said fragments.
2. A process according to claim 1, wherein the binding of the labeling agents to said first ligand is effected indirectly.
3. A process according to claim 2, wherein a first antiligand is bound to said first ligand, a second ligand is bound to said first antiligand, and the labeling agent comprises a second antiligand bearing at least one label and able to react with said second ligand.
4. A process according to claim 3, wherein first ligandfirst antiligand and second ligandsecond antiligand combinations are selected from the group consisting of biotinstreptavidin, haptenantibody, antigenantibody, peptideantibody, sugarlectin and polynucleotidecomplementary polynucleotide.
5. A process according to claim 4, wherein the first and second ligands are the same.
6. A process according to claim 4, wherein the first and second ligands are different.
7. A process according to claim 6, wherein the first ligand is a derivative of fluorescein and the second ligand is a derivative of biotin.
8. A process according to claim 1, wherein the first ligand is a derivative of biotin and the labeling agent is a derivative of streptavidin.
9. A process according to claim 1, wherein the fragmenting and the fixing are effected in one step.
10. A process according to claim 1, wherein the fragmenting and the fixing are effected in two steps.
11. A process according to claim 1, wherein the binding of the labeling agent to the first ligand is covalent.
12. A process according to claim 1, wherein the binding of the labeling agent to the first ligand is non-covalent.
13. A process according to claim 1, wherein the fixing is effected by reacting a reactive function, which is carried by said first ligand, to a phosphate which is in the 2 position, in the 3 position or in the cyclic monophosphate 2-3 position, with respect to a ribose at the 3 end or the 5 end of the RNA fragment.
14. A process according to claim 1, wherein at least one of the fragmenting and the fixing is effected by reacting a nucleophilic, electrophilic or halide function which is carried by said first ligand to a phosphate in the 2 position, in the 3 position or in the cyclic monophosphate 2-3 position, with respect to a ribose at the 3 end or the 5 end of the RNA fragment.
15. A process according to claim 1, wherein the fragmenting is effected enzymatically, chemically or physically.
16. A process according to claim 15, wherein the fragmenting is carried out enzymatically with at least one nuclease.
17. A process according to claim 15, wherein the fragmenting is carried out chemically with metal cations optionally combined with a chemical catalyst.
18. A process according to claim 1, wherein the fragmenting is carried out with metal cations selected from the group consisting of Mg, Mn, Cu, Co and Zn ions, and a chemical catalyst comprised of imidazole, a substituted imidazole analogue, or any chemical molecule which has an affinity for the RNA and which carries an imidazole nucleus or a substituted imidazole analogue.
19. A process according to claim 15, wherein the fragmenting is carried out physically by sonication or irradiation.
20. A process according to claim 1, wherein the fixing is effected by reacting a molecule R-X to a phosphate which is linked to the 2 position, to the 3 position or to the cyclic monophosphate 2-3 position of a ribose at the 3 end or the 5 end of the RNA fragment, where R is the first ligand and X is a reactive function selected from the group consisting of hydroxyl, amine, hydrazine, alkoxylamine, alkyl halide, phenylmethyl halide, iodoacetamide and maleimide.
21. A process according to claim 20, wherein R-X is selected from the group consisting of 5-(bromofluorescein) and derivatives of iodoacetyl biotin.
22. A labeled RNA fragment which is obtained by the process of claim 1, wherein the RNA fragment comprises at the 3 end or the 5 end a single nucleotide which is labeled at the terminal phosphate released during the fragmentation.
23. An RNA fragment according to claim 22, comprised of from 10 to 150 nucleotides.
24. An RNA fragment according to claim 22, wherein the RNA fragment comprises at least one nucleotide having a thiophosphate moiety, wherein said thiophosphate moiety is attached to a biotin bound to a streptavidin.
25. A labeled RNA fragment comprising at 3 end a phosphate or a thiophosphate bearing a fluorescein bound to an anti-fluorescein antibody bearing at least one biotin, said antibody bound to a labeled streptavidin.
26. A method of detecting at least one member selected from the group consisting of an RNA, a DNA, an RNA fragment and a DNA fragment, comprising probing a sample suspected of containing said member with a labeled RNA fragment according to claim 22.
27. A method of detecting at least one member selected from the group consisting of an RNA, a DNA, an RNA fragment and a DNA fragment, comprising probing a sample suspected of containing said member with a labeled RNA fragment according to claim 25.
28. A method of binding a labeled target to a capture probe, comprising exposing said labeled target to said capture probe, wherein said labeled target is a labeled RNA fragment according to claim 22.
29. A method of binding a labeled target to a capture probe, comprising exposing said labeled target to said capture probe, wherein said labeled target is a labeled RNA fragment according to claim 25.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A shift register circuit comprising:
a first clock terminal and first and second output terminals;
a first transistor for supplying a first clock signal inputted to said first clock terminal to said first output terminal;
a second transistor for discharging said first output terminal;
a third transistor for supplying said first clock signal to said second output terminal;
a fourth transistor for discharging said second output terminal;
a first driving circuit connected to a control electrode of said first transistor, for driving said first transistor;
a second driving circuit connected to a control electrode of said third transistor, for driving said third transistor;
said first driving circuit and said second driving circuit perform chargedischarge of said control electrode of said first transistor and chargedischarge of said control electrode of said third transistor, respectively, at the same timing;
said first driving circuit includes a sixth transistor coupled to said control electrode of said first transistor and discharges said control electrode of said first transistor;
said second driving circuit includes an eighth transistor coupled to the control electrode of said third transistor and discharges said control electrode of said third transistor; and
a control electrode of said sixth transistor is connected to a control electrode of said eighth transistor.
2. The shift register circuit according to claim 1, wherein
a control electrode of said second transistor and a control electrode of said fourth transistor are connected to each other,
a node connected to said control electrode of said first transistor is a first node,
a node connected to said control electrodes of said second and fourth transistors is a second node,
a node connected to said control electrode of said third transistor is a third node,
said first driving circuit includes
a fifth transistor having a control electrode connected to a predetermined input terminal, for charging said first node;
said sixth transistor having said control electrode connected to said second node, for discharging said first node, and
said second driving circuit includes
a seventh transistor having a control electrode connected to said input terminal, for charging said third node; and
said eighth transistor having said control electrode connected to said second node, for discharging said third node.
3. The shift register circuit according to claim 2, wherein
said first driving circuit further includes a ninth transistor having a control electrode connected to a predetermined reset terminal, for discharging said first node,
said shift register circuit further comprising
an inverter using said first node as an input end and said second node as an output end.
4. The shift register circuit according to claim 1, further comprising
a first capacitive element connected between said control electrode of said first transistor and said first output terminal.
5. The shift register circuit according to claim 1, further comprising
a second capacitive element connected between said control electrode of said third transistor and said second output terminal.
6. The shift register circuit consisting of a plurality of shift register circuits according to claim 1 which are connected in cascade.
7. The shift register circuit according to claim 1, wherein
a control electrode of said second transistor and a control electrode of said fourth transistor are connected to each other,
a node connected to said control electrode of said first transistor is a first node,
a node connected to said control electrodes of said second and fourth transistors is a second node,
a node connected to said control electrode of said third transistor is a third node,
said first driving circuit includes
a fifth transistor connected between said first node and a first input terminal, having a control electrode connected to a second input terminal;
said sixth transistor having said control electrode connected to a predetermined reset terminal, for discharging said first node, and
said second driving circuit includes
a seventh transistor connected between said third node and said first or second input terminal, having a control electrode connected to said second input terminal; and
said eighth transistor having said control electrode connected to said predetermined reset terminal, for discharging said third node.
8. The shift register circuit according to claim 7, wherein
said second node is connected to said reset terminal.
9. The shift register circuit according to claim 7, wherein
said second node is connected to a second clock terminal to which a second clock signal different from said first clock signal in phase is inputted.
10. The shift register circuit according to claim 9, wherein
said second transistor is connected between said first output terminal and said first clock terminal, and
said fourth transistor is connected between said second output terminal and said first clock terminal.
11. The shift register circuit according to claim 7, further comprising
an inverter using said first or third node as an input end and said second node as an output end.
12. The shift register circuit according to claim 11, further comprising:
a ninth transistor having a control electrode connected to said second node, for discharging said first node; and
a tenth transistor having a control electrode connected to said second node, for discharging said third node.
13. The shift register circuit according to claim 7, further comprising:
a first capacitive element connected between a third clock terminal to which a third clock signal different from said first clock signal in phase is inputted and said first node; and
a second capacitive element connected between said third clock terminal and said third node.
14. The shift register circuit which is a multistage shift register circuit, each stage of which is the shift register circuit according to any one of claims 7 to 13, wherein
in said each stage,
said first input terminal is connected to said first output terminal of its preceding stage,
said second input terminal is connected to said second output terminal of its preceding stage, and
said reset terminal is connected to said first output terminal of its succeeding-stage.
15. The shift register circuit according to claim 14, wherein
in said each stage,
an output signal from said second output terminal is faster in speed of level change than an output signal from said first output terminal.
16. The shift register circuit according to any one of claims 7 to 13, wherein
said sixth transistor is connected between said first node and said first or second input terminal,
said eighth transistor is connected between said third node and said first or second input terminal, and
a fourth clock signal different from said first clock signal in phase is inputted to said reset terminal.
17. The shift register circuit which is a multistage shift register circuit, each stage of which is the shift register circuit according to claim 16, wherein
in said each stage,
said first input terminal is connected to said first output terminal of its preceding stage,
said second input terminal is connected to said second output terminal of its preceding stage, and
said fourth clock signal has the same phase as that of a signal inputted to said first clock terminal of its preceding stage.
18. The shift register circuit according to claim 17, wherein
in said each stage,
an output signal from said second output terminal is faster in speed of level change than an output signal from said first output terminal.
19. An image display apparatus comprising
a gate line driving circuit formed of a multistage shift register circuit,
wherein each stage of said multistage shift register circuit comprises
a first clock terminal and first and second output terminals;
a first transistor for supplying a first clock signal inputted to said first clock terminal to said first output terminal;
a second transistor for discharging said first output terminal;
a third transistor for supplying said first clock signal to said second output terminal;
a fourth transistor for discharging said second output terminal;
a first driving circuit connected to a control electrode of said first transistor, for driving said first transistor;
a second driving circuit connected to a control electrode of said third transistor, for driving said third transistor;
said first driving circuit and said second driving circuit perform chargedischarge of said control electrode of said first transistor and chargedischarge of said control electrode of said third transistor, respectively, at the same timing;
said first driving circuit includes a sixth transistor coupled to said control electrode of said first transistor and discharges said control electrode of said first transistor;
said second driving circuit includes an eighth transistor coupled to the control electrode of said third transistor and discharges said control electrode of said third transistor; and
a control electrode of said sixth transistor is connected to a control electrode of said eighth transistor.
20. The image display apparatus according to claim 19, wherein
in said each stage,
said first output terminal is connected to a gate line of a display panel, and
said second output terminal is connected to a input terminal of its succeeding-stage shift register circuit.
21. The image display apparatus according to claim 19, wherein
in said each stage,
a control electrode of said second transistor and a control electrode of said fourth transistor are connected to each other,
a node connected to said control electrode of said first transistor is a first node,
a node connected to said control electrodes of said second and fourth transistors is a second node,
a node connected to said control electrode of said third transistor is a third node,
said first driving circuit includes
a fifth transistor connected between said first node and a first input terminal, having a control electrode connected to a second input terminal; and
said sixth transistor having said control electrode connected to a predetermined reset terminal, for discharging said first node, and
said second driving circuit includes
a seventh transistor connected between said third node and said first or second input terminal, having a control electrode connected to said second input terminal; and
said eighth transistor having said control electrode connected to said predetermined reset terminal, for discharging said third node.
22. The image display apparatus according to claim 21, wherein
in said each stage,
said first input terminal is connected to said first output terminal of its preceding stage,
said second input terminal is connected to said second output terminal of its preceding stage, and
said reset terminal is connected to said first output terminal of its succeeding-stage,
and wherein each of gate lines of a display panel is connected to said first output terminal of said each stage.
23. The image display apparatus according to claim 22, wherein
in said each stage,
an output signal from said second output terminal is faster in speed of level change than an output signal from said first output terminal.
24. The image display apparatus according to claim 21, wherein
in said each stage,
said sixth transistor is connected between said first node and said first or second input terminal,
said eighth transistor is connected between said third node and said first or second input terminal,
said first input terminal is connected to said first output terminal of its preceding stage,
said second input terminal is connected to said second output terminal of its preceding stage, and
a fourth clock signal having the same phase as that of a signal inputted to said first clock terminal of its preceding stage is inputted to said reset terminal,
and wherein each of gate lines of a display panel is connected to said first output terminal of said each stage.
25. The image display apparatus according to claim 24, wherein
in said each stage,
an output signal from said second output terminal is faster in speed of level change than an output signal of said first output terminal.