1. An image-forming device comprising:
an image-carrying member having a surface on which an electrostatic latent image is formed and developed into a developer image by a developer;
a developer-carrying member having an outer surface including a layer forming region for carrying a layer of developer to the surface of the image-carrying member, the layer forming region having a first width in a widthwise direction;
a belt configured to circulate in a moving direction orthogonal to the widthwise direction and transfer the developer image onto a recording medium, the belt having an outer surface including a cleanable region; and
a cleaning unit comprising:
a cleaning member that contacts the cleanable region of the belt and receives the developer from the outer surface of the belt, the cleaning member having a second width in the widthwise direction;
a removing member that removes the developer from the cleaning member and having a third width in the widthwise direction; and
wherein the first width is narrower than the second width, and the second width is narrower than the third width.
2. The image-forming device according to claim 1, wherein the cleaning member comprises a first rotating element and a second rotating element, the first rotating element receiving the developer from the outer surface of the belt and having a fourth width in the widthwise direction, the second rotating element receiving the developer from the first rotating element and having a fifth width in the widthwise direction, the fourth width being narrower than the fifth width, and the fifth width being narrower than the third width.
3. The image-forming device according to claim 2, wherein the cleaning unit further comprises a backup member for supporting the belt at a position opposite to the first rotating element with respect to the belt, the back up member having a sixth width in the widthwise direction narrower than the fourth width.
4. The image-forming device according to claim 3, wherein the belt comprises a belt body having a widthwise end portions in the widthwise direction, and guiding ribs each being provided at each widthwise end portions, the two guiding ribs being separated from each other by a seventh width; and,
the image forming device further comprising tension rollers that drive and stretch the belt, each guiding rib being positioned outside of the tension roller in the widthwise direction, the sixth width being narrower than the seventh width, and the backup member being disposed between the guiding ribs.
5. The image-forming device according to claim 1, wherein the developer is a polymerized toner.
6. The image-forming device according to claim 1, wherein the developer carrying member contacts the image-carrying member for forming a developer image corresponding to the electrostatic latent image.
7. The image-forming device according to claim 1, wherein the cleaning member is disposed at a position such that each widthwise end of the cleaning member is positioned within the widthwise ends of the belt.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
We claim:
1. A Phase-Locked Loop (PLL) integrated with testing apparatus comprising in a loop:
i) a Phase-Frequency Detector (PFD), the PFD having first and second signal inputs, a test control input and an output, wherein the test control input is used to switch the PFD between a normal operating mode, in which the output delivers an output signal containing the phase and frequency difference between first and second signals applied respectively to the first and second signal inputs, and a transparent mode, in which only one of the first and second signal inputs is coupled to the output such that the corresponding signal is coupled through to the output unaltered;
ii) a Voltage Controlled Oscillator (VCO), the VCO having an input and an output, the input of the VCO connected to the output of the PFD;
iii) a frequency divider, the frequency divider having an input and an output, the input of the frequency divider connected to the output of the VCO; and
iv) a first multiplexer (MUX), the first MUX having first and second signal inputs, a control input and an output, the output of the first MUX connected to the second signal input of the PFD, the first signal input of the first MUX connected to the output of the frequency divider, the second signal input coupled to receive a bias signal, and the control input coupled to receive a control signal;
wherein the control signal coupled to the control input of the first MUX is set to select which one of the first and second signal inputs is coupled to the output of the first MUX.
2. The PLL of claim 1 further comprising a charge pump, the charge pump having an input and an output, the charge pump connected between the PFD and the VCO.
3. The PLL of claim 1 further comprising a loop filter connected to the input of the VCO.
4. The PLL of claim 1 further comprising a loop filter connected between the PFD and the VCO.
5. The PLL of claim 1 further comprising a second MUX between VCO and the frequency divider, the second MUX having first and second signal inputs, a control input and an output, the output of the second MUX connected to the input of the frequency divider, the first signal input of the second MUX connected to the output of the VCO, the second signal input of the second MUX coupled to receive a first test signal, and the control input of the second MUX coupled to receive a second control signal, wherein the second control signal coupled to the control input of the second MUX is set to select which one of the first and second signal inputs is coupled to the output of the second MUX.
6. The PLL of claim 1 further comprising a third MUX having first and second signal inputs, a control input and an output, the output of the third MUX connected to the first input of the PFD, the first signal input of the third MUX coupled to receive a reference signal, the second signal input of the third MUX coupled to receive a second bias signal, and the control input of the third MUX coupled to receive a third control signal, wherein the third control signal coupled to the control input of the third MUX is set to select which one of the first and second signal inputs is coupled to the output of the third MUX.
7. The PLL of claim 6 further comprising a reference divider circuit, the reference divider having an input and an output, the input coupled to receive the reference signal and the output connected to the first signal input of the third MUX to provide a signal to the third MUX derived from the reference signal.
8. The PLL of claim 5 further comprising a mixer connected between the VCO and the second MUX, the mixer having two inputs and an output, the output of the mixer connected to the first signal input of the second MUX, the first input of the mixer coupled to receive the output of the VCO and the second input of the mixer coupled to receive a local reference signal.
9. The PLL of claim 8 further comprising a local oscillator, the local oscillator providing the local reference signal.
10. The PLL of claim 9 further comprising a fourth MUX between the local oscillator and the second input of the mixer, the fourth MUX having first and second signal input, a control input and an output, the first signal input of the fourth MUX coupled to receive the local reference signal, the second signal input of the fourth MUX coupled to receive a fourth bias signal, the output of the fourth MUX connected to the second input of the mixer, and the control input of the fourth MUX coupled to receive a fourth control signal, the fourth control signal set to select which of the two signal inputs is coupled to the output of the fourth MUX.
11. A Phase-Locked Loop (PLL) integrated with testing apparatus comprising in a loop:
i) a Phase-Frequency Detector (PFD), the PFD having first and second signal inputs, a test control input and an output, wherein the test control input is used to switch the PFD between a normal operating mode, in which the output delivers an output signal containing the phase and frequency difference between first and second signals applied respectively to the first and second signal inputs, and a transparent mode, in which only one of the first and second signal inputs is coupled to the output such that the corresponding signal is coupled through to the output unaltered;
ii) a Voltage Controlled Oscillator (VCO), the VCO having an input and an output, the input of the VCO connected to the output of the PFD;
iii) a frequency divider, the frequency divider having an input and an output, the output of the frequency divider connected to the second signal input of the PFD; and
iv) a first multiplexer (MUX), the first MUX having first and second signal inputs, a control input and an output, the output of the first MUX connected to the input of the frequency divider, the first signal input of the first MUX is connected to the output of the VCO, the second signal input of the first MUX coupled to receive a first test signal, and the control input of the first MUX coupled to receive a first control signal, wherein the first control signal coupled to the control input of the first MUX is set to select which one of the first and second signal inputs is coupled to the output of the first MUX.
12. The PLL of claim 11 further comprising a charge pump, the charge pump having an input and an output, the charge pump connected between the PFD and the VCO.
13. The PLL of claim 11 further comprising a loop filter connected to the input of the VCO.
14. The PLL of claim 11 further comprising a loop filter connected between the PFD and the VCO.
15. The PLL of claim 11 further comprising a third MUX having first and second signal inputs, a control input and an output, the output of the third MUX connected to the first input of the PFD, the first signal input of the third MUX is coupled to receive a reference signal, the second signal input of the third MUX coupled to receive a second bias signal, and the control input of the third MUX coupled to receive a third control signal, wherein the third control signal coupled to the control input of the third MUX is set to select which one of the first and second signal inputs is coupled to the output of the third MUX.
16. The PLL of claim 15 further comprising a reference divider circuit, the reference divider having an input and an output, the input coupled to receive the reference signal and the output connected to the first signal input of the third MUX to provide a signal to the third MUX derived from the reference signal.
17. A Phase-Frequency Detector (PFD), the PFD having first and second signal inputs, a test control input and an output, wherein the test control input is used to switch the PFD between a normal operating mode, in which the output delivers an output signal containing the phase and frequency difference between first and second signals applied respectively to the first and second signal inputs, and a transparent mode, in which only one of the first and second signal inputs is coupled to the output such that the corresponding signal is coupled through to the output unaltered.
18. The PFD of claim 17 further adapted to operate upon digital signals.
19. The PFD of claim 17 further adapted to operate upon analogue signals.