1. A magnetic tunnel junction (MTJ) device for a magnetic random access memory (MRAM) device, comprising:
a substrate having a first metal interconnect;
a first dielectric passivation barrier layer formed on the substrate, the first dielectric passivation barrier layer having a first contact via opening formed with a first mask pattern to expose the first metal interconnect;
a first electrode layer formed on the first dielectric passivation barrier layer and extending through the first contact via opening, the first electrode layer in communication with the first metal interconnect;
a fixed magnetization layer formed on the first electrode layer;
a tunnel barrier layer formed on the fixed magnetization layer;
a free magnetization layer formed on the tunnel barrier layer;
a second electrode layer formed on the free magnetization layer, at least the second electrode layer and the free magnetization layer having a shape based upon a second mask pattern and being located over the first contact via opening; and
a second dielectric passivation barrier layer formed on the fixed magnetization layer and around the tunnel barrier layer, the free magnetization layer and the second electrode layer, the second dielectric passivation barrier layer only partially covering the second electrode layer, the second dielectric passivation barrier layer and at least a first portion of the fixed magnetization layer having a shape based upon a third mask pattern.
2. The magnetic tunnel junction device of claim 1, in which a tunnel barrier layer shape is based upon the second mask pattern.
3. The magnetic tunnel junction device of claim 1, in which the first contact via opening is at least as wide as the first metal interconnect.
4. The magnetic tunnel junction device of claim 1, in which at least a second portion of the fixed magnetization layer has a shape defined by the second mask pattern.
5. The magnetic tunnel junction device of claim 1, further comprising a third electrode layer formed on the second dielectric passivation barrier layer in communication with the second electrode layer, the third electrode layer having a shape defined by the third mask pattern.
6. The magnetic tunnel junction device of claim 5, further comprising a global dielectric passivation barrier layer disposed over the third electrode layer.
7. The magnetic tunnel junction device of claim 6, further comprising:
a second interlayer dielectric deposited on the global dielectric passivation barrier layer; and
a via opening in the global dielectric passivation barrier layer to expose a portion of the third electrode layer.
8. The magnetic tunnel junction device of claim 1, in which the second mask pattern has an ellipsoid shape.
9. The magnetic tunnel junction device of claim 1, in which the MRAM device is a spin-torque-transfer (STT) MRAM device.
10. The magnetic tunnel junction device of claim 1, integrated into a semiconductor die.
11. The magnetic tunnel junction device of claim 1, integrated into a device selected from a group consisting of a set top box, music player, video player, entertainment unit, navigation device, communications device, personal digital assistant (PDA), fixed location data unit, and a computer.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A data encoding device for coding of LDPC codes that have a plurality of code rates and whose all parity check matrices are composed of a plurality of cyclic matrices, the data encoding device comprising:
circuitry performing coding by converting data words into code words such that
the relationships 1<w0 and w1<w0 are satisfied where a maximum column weight of the cyclic matrices in the certain check matrix whose code rate is not a minimum value among the LDPC codes is defined as w0 and a maximum column weight of the cyclic matrices in the check matrix of a code having a code rate lower than the code rate is defined as w1, and further wherein one or more of the check matrices is obtained based on row splitting.
2. The data encoding device according to claim 1, wherein
when one side of the cyclic matrix in a parity check row is defined as m, based on assumption that a certain row address indicating a position of bit 1 in a certain column in the parity check matrix of a code having a high code rate is b, a row address indicating a position of bit 1 in the column in the parity check matrix of a code having a lower code rate can be represented as b+cm with use of an integer c that is constant for each cyclic matrix and is equal to or larger than 0.
3. The data encoding device according to claim 2, wherein
a value of b or c is so adjusted that all of positions of parity in the check matrices of the codes are on a right side on the check matrix, or on a left side, or with constant intervals.
4. The data encoding device according to claim 3, wherein
the number of cyclic matrices in the parity check matrix of a code having a highest code rate is only one in a row direction, and 2<w0 is satisfied.
5. The data encoding device according to claim 4, wherein
column weight of the cyclic matrices in the parity check matrix of a code having a lowest code rate is 0 or 1.
6. The data encoding device according to claim 5, wherein
column weight of the parity check matrix is constant for the codes of all of the code rates.
7. The data encoding device according to claim 6, wherein
a column weight of the parity check matrix is 3.
8. The data encoding device according to claim 7, wherein
all of the codes are self-orthogonal.
9. The data encoding device according to claim 8, wherein
a minimum hamming distance of all of the codes is at least 6.
10. The data encoding device according to claim 4, wherein
coding is performed, including a code that is obtained by changing length m of one side of an identity matrix and has a different code length.