1. A server system for transferring a communication message in a communication session, the server system being connected to a communication network, the server system comprising:
a first server to
store, in a first storage, a logical number and address information of a proxy server connected to the communication network;
in association with each other,
receive a first communication message including first address information of a first proxy server,
generate first session information for controlling a first session corresponding to the received first communication message,
extract the first address information included in the received first communication message,
retrieve a first logical number from the first storage on the basis of the extracted first address information, and
store, in a second storage, the retrieved first logical number and the generated first session information in association with each other.
2. The server system of claim 1, wherein
the first server further
extracts a second logical number from the second storage,
retrieves second address information from the first storage on the basis of the extracted second logical number, and
generates a second communication message including the retrieved second address information.
3. The server system of claim 1, further comprising:
a second server to copy information stored in the first storage to a third storage, and information stored in the second storage to a fourth storage.
4. The server system of claim 1, wherein
the communication session is a SIP session,
the first communication message is an INVITE request, and
the first address information is a header value of a Record-Route header.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method, comprising:
transmitting a first signal representative of a test operation from a test circuit to a memory via a first signal path;
transmitting a second signal, synchronized with the first signal, from the test circuit to the memory via a second signal path; and
initiating the test operation on the memory in response to the second signal arriving at the memory.
2. The method of claim 1 wherein the second signal is synchronized with an end of the first signal.
3. The method of claim 1 wherein transmitting the first signal representative of the test operation from the test circuit to the memory via the first signal path includes storing at least one of a control, address and data bit of the test operation in an input register coupled to the memory input.
4. The method of claim 3 further comprising storing at least one of a control, address and data bit of a subsequent test operation in a shadow register coupled to an input of the input register.
5. The method of claim 4 further comprising:
initiating the subsequent test operation on the memory in response to a signal, synchronized with the subsequent test operation, arriving at the memory;
wherein the test operation and subsequent test operation are performed as back-to-back operations.
6. The method of claim 1 wherein:
the first signal path is defined by a first set of one or more latches included in each of one or more communication path registers; and
the second signal path is defined by a second set of one or more latches included in each of the one or more communication path registers.
7. The method of claim 1 wherein initiating the test operation on the memory in response to the second signal arriving at the memory includes employing the second signal to trigger loading test data into the memory.
8. A method, comprising:
transmitting a first signal representative of stored test data from a memory to a test circuit via a first signal path;
transmitting a second signal, synchronized with the first signal, from the memory to the test circuit via a second signal path; and
employing the second signal to indicate arrival of the first signal at the test circuit.
9. The method of claim 8 further comprising comparing the first signal with expected values.
10. The method of claim 8 wherein transmitting the first signal representative of stored test data from the memory to the test circuit via the first signal path includes, in response to the second signal, storing the stored test data in an output register coupled to the memory output.
11. The method of claim 8 wherein:
the first signal path is defined by a first set of one or more latches included in each of one or more communication path registers; and
the second signal path is defined by a second set of one or more latches included in each of the one or more communication path registers.
12. A method, comprising:
transmitting a first signal representative of a test operation from a test circuit to a memory via a first signal path;
transmitting a second signal, synchronized with the first signal, from the test circuit to the memory via a second signal path;
initiating the test operation on the memory in response to the second signal arriving at the memory;
transmitting a third signal representative of stored test data from the memory to the test circuit via the first signal path;
transmitting the second signal, synchronized with the third signal, from the memory to the test circuit via the second signal path; and
employing the second signal transmitted from the memory to indicate arrival of the third signal at the test circuit.
13. The method of claim 12 wherein the second signal transmitted to the memory is synchronized with an end of the first signal.
14. The method of claim 12 wherein transmitting the first signal representative of the test operation from the test circuit to the memory via the first signal path includes storing at least one of a control, address and data bit of the test operation in an input register coupled to the memory input.
15. The method of claim 14 further comprising storing at least one of a control, address and data bit of a subsequent test operation in a shadow register coupled to an input of the input register.
16. The method of claim 15 further comprising:
initiating the subsequent test operation on the memory in response to a signal, synchronized with the subsequent test operation, arriving at the memory;
wherein the test operation and subsequent test operation are to be performed as back-to-back operations.
17. The method of claim 12 wherein:
the first signal path is defined by a first set of one or more latches included in each of one or more communication path registers; and
the second signal path is defined by a second set of one or more latches included in each of the one or more communication path registers.
18. The method of claim 12 wherein initiating the test operation on the memory in response to the second signal arriving at the memory includes employing the second signal to trigger loading test data into the memory.
19. The method of claim 12 further comprising comparing the third signal with an expected value.
20. The method of claim 12 wherein transmitting the third signal representative of stored test data from the memory to the test circuit via the first signal path includes, in response to the second signal transmitted from the memory, storing the stored test data in an output register coupled to the memory output.
21. A method, comprising:
transmitting a first signal representative of a test operation from a test circuit to a first memory via a first signal path;
transmitting a second signal, synchronized with the first signal, from the test circuit to the first memory via a second signal path;
transmitting the first signal from the test circuit to a second memory via a third signal path;
transmitting a third signal, synchronized with the first signal, from the test circuit to the second memory via a fourth signal path;
initiating the test operation on the first memory in response to the second signal arriving at the first memory; and
initiating the test operation on the second memory in response to the third signal arriving at the second memory.
22. The method of claim 21 wherein:
the first signal path is shorter than the third signal path; and
the second signal path is shorter than the fourth signal path.
23. The method of claim 21 further comprising:
transmitting a fourth signal representative of stored test data from the first memory to the test circuit via the first signal path;
transmitting the second signal, synchronized with the fourth signal, from the memory to the test circuit via the second signal path;
transmitting a fifth signal representative of stored test data from the second memory to the test circuit via the third signal path;
transmitting the third signal, synchronized with the fifth signal, from the second memory to the test circuit via the fourth signal path;
employing the second signal to indicate arrival of the fourth signal at the test circuit; and
employing the third signal to indicate arrival of the fifth signal at the test circuit.
24. An apparatus, comprising:
a test circuit;
a test circuit interface adapted to couple to the test circuit and a memory; and
a plurality of registers, each of which includes a plurality of latches, adapted to define a first signal path and a second signal path and couple to the test circuit interface and the test circuit;
wherein the apparatus is adapted to:
transmit a first signal representative of a test operation from the test circuit to the memory via the first signal path;
transmit a second signal, synchronized with the first signal, from the test circuit to the memory via the second signal path; and
initiate the test operation on the memory in response to the second signal arriving at the memory.
25. The apparatus of claim 24 wherein the second signal is synchronized with an end of the first signal.
26. The apparatus of claim 24 wherein:
the test circuit interface includes an input register coupled to the first signal path and a memory input; and
the apparatus is further adapted to store at least on of a control, address and data bit of the test operation in the input register.
27. The apparatus of claim 26 wherein:
the test circuit interface includes a shadow register coupled to the first signal path and an input of the input register; and
the apparatus is further adapted to store at least one of a control, address and data bit of a subsequent test operation in the shadow register.
28. The apparatus of claim 27 wherein the apparatus is further adapted to:
initiate the subsequent test operation on the memory in response to a signal, synchronized with the subsequent test operation, arriving at the memory;
wherein the test operation and subsequent test operation are back-to-back operations.
29. The apparatus of claim 24 wherein the first signal path is defined by a first set of one or more latches included in each of the plurality of registers; and
the second signal path is defined by a second set of one or more latches included in each of the plurality of registers.
30. The apparatus of claim 24 wherein the apparatus is further adapted to employ the second signal to load test data into the memory.
31. An apparatus, comprising:
a test circuit;
a test circuit interface adapted to couple to the test circuit and a memory; and
a plurality of registers, each of which includes a plurality of latches, adapted to define a first signal path and a second signal path and couple to the test circuit interface and the test circuit;
wherein the apparatus is adapted to:
transmit a first signal representative of stored test data from the memory to the test circuit via the first signal path;
transmit a second signal, synchronized with the first signal, from the memory to the test circuit via the second signal path; and
employ the second signal to indicate arrival of the first signal at the test circuit.
32. The apparatus of claim 31 wherein the apparatus is further adapted to compare the first signal with an expected value.
33. The apparatus of claim 31 wherein:
the test circuit interface includes an output register coupled to a memory output and the first signal path; and
the apparatus is further adapted to, in response to the second signal, store the stored test data in the output register.
34. The apparatus of claim 31 wherein:
the first signal path is defined by a first set of one or more latches included in the plurality of registers; and
the second signal path is defined by a second set of one or more latches included in the plurality of registers.
35. An apparatus, comprising:
a test circuit;
a test circuit interface adapted to couple to the test circuit and a memory; and
a plurality of registers, each of which includes a plurality of latches, adapted to define a first signal path and a second signal path and couple to the test circuit interface and the test circuit;
wherein the apparatus is adapted to:
transmit a first signal representative of a test operation from the test circuit to the memory via the first signal path;
transmit a second signal, synchronized with the first signal, from the test circuit to the memory via the second signal path; and
initiate the test operation on the memory in response to the second signal arriving at the memory;
transmit a third signal representative of stored test data from the memory to the test circuit via the first signal path;
transmit the second signal, synchronized with the third signal, from the memory to the test circuit via the second signal path; and
employ the second signal to indicate arrival of the third signal at the test circuit.
36. The apparatus of claim 35 wherein the second signal is synchronized with an end of the first signal.
37. The apparatus of claim 35 wherein:
the test circuit interface includes an input register coupled to the first signal path and a memory input; and
the apparatus is further adapted to store at least one of a control, address and data bit of the test operation in the input register.
38. The apparatus of claim 37 wherein:
the test circuit interface includes a shadow register coupled to the first signal path and an input of the input register; and
the apparatus is further adapted to store at least one of a control, address and data bit of a subsequent test operation in the shadow register.
39. The apparatus of claim 38 wherein the apparatus is further adapted to:
initiate the subsequent test operation on the memory in response to a signal, synchronized with the subsequent test operation, arriving at the memory;
wherein the test operation and subsequent test operation are to be performed as back-to-back operations.
40. The apparatus of claim 35 wherein:
the first signal path is defined by a first set of one or more latches included in the plurality of registers; and
the second signal path is defined by a second set of one or more latches included in the plurality of registers.
41. The apparatus of claim 35 wherein the apparatus is further adapted to employ the second signal to load test data into the memory.
42. The apparatus of claim 35 wherein the apparatus is further adapted to compare the third signal with an expected value.
43. The apparatus of claim 35 wherein:
the test circuit interface includes an output register coupled to a memory output and the first signal path; and
the apparatus is further adapted to, in response to the second signal, store the stored test data in the output register.
44. An apparatus, comprising:
a test circuit;
a first test circuit interface adapted to couple to the test circuit and a first memory; and
a first plurality of registers, each of which includes a first plurality of latches, adapted to define a first signal path and a second signal path and couple to the first test circuit interface and the test circuit;
a second test circuit interface adapted to couple to the test circuit and a second memory; and
a second plurality of registers, each of which includes a second plurality of latches, adapted to define a third signal path and a fourth signal path and couple to the second test circuit interface and the test circuit;
wherein the apparatus is adapted to:
transmit a first signal representative of a test operation from the test circuit to the first memory via the first signal path;
transmit a second signal, synchronized with the first signal, from the test circuit to the first memory via the second signal path;
transmit the first signal from the test circuit to the second memory via the third signal path;
transmit a third signal, synchronized with the first signal, from the test circuit to the second memory via the fourth signal path;
initiate the test operation on the first memory in response to the second signal arriving at the first memory; and
initiate the test operation on the second memory in response to the third signal arriving at the second memory.
45. The apparatus of claim 44 wherein:
the first signal path is shorter than the third signal path; and
the second signal path is shorter than the fourth signal path.
46. The apparatus of claim 44 wherein the apparatus is further adapted to:
transmit a fourth signal representative of stored test data from the first memory to the test circuit via the first signal path;
transmit the second signal, synchronized with the fourth signal, from the memory to the test circuit via the second signal path;
transmit a fifth signal representative of stored test data from the second memory to the test circuit via the third signal path;
transmit the third signal, synchronized with the fifth signal, from the second memory to the test circuit via the fourth signal path;
employ the second signal to indicate arrival of the fourth signal at the test circuit; and
employ the third signal to indicate arrival of the fifth signal at the test circuit.
47. The method of claim 4 wherein the shadow register includes a single latch for storing a data bit.
48. The method of claim 15 wherein the shadow register includes a single latch for storing a data bit.
49. The apparatus of claim 27 wherein the shadow register includes a single latch for storing a data bit.
50. The apparatus of claim 38 wherein the shadow register includes a single latch for storing a data bit.