1. A lithography method for selectively exposing parts of first and second targets, comprising:
performing a first patterning of a first target, wherein the first patterning includes:
directing light from a light source through a re-configurable reflective condenser in a first configuration to a first reflective reticle portion; and
reflecting the light from the first reflective reticle portion to a first target portion to be selectively exposed;
after performing the first patterning, re-configuring the reflective condenser to a second configuration, wherein the re-configuring results in altering of light characteristics of light exiting the reflective condenser; and
after the re-configuring, performing a second patterning of a second target, wherein the second patterning includes:
directing light from a light source through the re-configurable reflective condenser in the second configuration to a second reflective reticle portion; and
reflecting the light from the second reflective reticle portion to a second target portion to be selectively exposed.
2. The method of claim 1, wherein the re-configuring includes configuring reflective facets of a multi-faceted mirror that is part of the reflective condenser.
3. The method of claim 2, wherein the configuring the facets includes selectively actuating piezoelectric pushers of the multi-faceted mirror, wherein each of the reflective facets has multiple of the piezoelectric pushers coupled thereto.
4. The method of claim 2, wherein the configuring the facets includes using a controller that is coupled to the mirror to control the re-configuring the reflective facets.
5. The method of claim 4, wherein the controller is also operatively coupled to the reflective reticle portions.
6. The method of claim 1, wherein the re-configuring from the first configuration of the reflective condenser to the second configuration of the reflective condenser results in a change of a degree of partial coherence of the light output from the reflective condenser.
7. The method of claim 1, wherein the re-configuring from the first configuration of the reflective condenser to the second configuration of the reflective condenser results in a change of a light distribution at the pupil.
8. The method of claim 1, wherein the light produced by the light source is extreme ultraviolet (EUV) radiation, having a wavelength in the range of about 30 to 700 Angstroms (3\u201370 nm).
9. The method of claim 1, wherein the first patterning and the second patterning includes passing the light through optics between the reticle portions and the targets.
10. The method of claim 1, wherein the reflective reticle portions are different portions of a single reflective reticle.
11. The method of claim 1, wherein the reflective reticle portions are portions of different reflective reticles.
12. The method of claim 1, wherein the target portions are wafer portions covered with resist.
13. The method of claim 12, wherein the wafer portions are portions of a single wafer.
14. The method of claim 12, wherein the wafer portions are portions of different wafers.
15. A method of lithography comprising:
re-configuring, between lithography operations, reflective facets of a multi-faceted mirror that is part of a reflective condenser, wherein the re-configuring results in altering of light characteristics of light exiting the reflective condenser to strike a reflective reticle.
16. The method of claim 15, wherein the re-configuring results in changing a degree of partial coherence of the light.
17. The method of claim 15, wherein the reconfiguring results in changing a distribution of light at the pupil of the imaging system.
18. The method of claim 15, further comprising performing one of the lithography operations prior to the re-configuring, and performing another of the lithography operations after the configuring.
19. The method of claim 18, wherein both of the lithography operations involve selective exposure of different parts of a single wafer.
20. The method of claim 19, wherein the lithography operations involve reproductions of different types of features.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
What is claimed is:
1. An offset compensation circuit compensating for an offset voltage of a drive circuit outputting a potential according to an input potential, comprising:
first to N-th capacitors where N is an integer of at least two, said capacitors each having one electrode and the other electrode, the first capacitor having one electrode connected to an input node of said drive circuit, and second to N-th capacitors each having one electrode connected to the other electrode of a preceding capacitor;
a first switch circuit supplying a predetermined potential to the input node of said drive circuit and connecting the other electrode of said first capacitor to an output node of said drive circuit to charge said first capacitor to said offset voltage;
a second switch circuit successively selecting said second to N-th capacitors each for a predetermined period of time, supplying said input potential to one electrode of a selected capacitor and connecting the other electrode of the selected capacitor to the output node of said drive circuit to charge said first to N-th capacitors to said offset voltage; and
a third switch circuit supplying said input potential to the other electrode of said N-th capacitor.
2. The offset compensation circuit according to claim 1, wherein
said predetermined potential is said input potential.
3. The offset compensation circuit according to claim 1, wherein
said predetermined potential is a reference potential.
4. The offset compensation circuit according to claim 1, wherein
said second switch circuit connects respective other electrodes of said first to N-th capacitors commonly to the output node of said drive circuit to reset a voltage between one electrode and the other electrode of said second to N-th capacitors each to 0 V, and thereafter successively selects said second to N-th capacitors each for a predetermined period of time to disconnect one electrode of a selected capacitor from the output node of said drive circuit and supply said input potential to one electrode of the selected capacitor, thereby charging said first to N-th capacitors to said offset voltage.
5. A drive circuit with offset-compensation capability, comprising:
a drive circuit outputting a potential according to an input potential; and
an offset compensation circuit recited in claim 1 compensating for an offset voltage of said drive circuit.
6. The drive circuit with offset-compensation capability according to claim 5, wherein
said drive circuit includes
a first transistor of a first conductivity type having its drain receiving a first power-supply potential, its source connected to said output node and its gate connected to said input node, and
a first constant-current source connected between said output node and a line of a second power-supply potential.
7. The drive circuit with offset-compensation capability according to claim 6, wherein
said drive circuit further includes a level shift circuit provided between said input node and the gate of said first transistor and supplying to the gate of said first transistor a potential obtained by level-shifting said input potential toward said first power-supply potential by a predetermined first voltage, and
said level shift circuit includes
a second constant-current source connected between a line of a third power-supply potential and the gate of said first transistor and
a second transistor of a second conductivity type having its source connected to the gate of said first transistor, its drain connected to a line of a fourth power-supply potential and its gate receiving said input potential.
8. The drive circuit with offset-compensation capability according to claim 7, wherein
said drive circuit further includes a third transistor of the second conductivity type inserted between the source of said first transistor and said output node and having its gate connected to said output node, and
said level shift circuit further includes a fourth transistor of the first conductivity type inserted between the gate of said first transistor and the source of said second transistor and having its gate connected to the gate of said first transistor.
9. The drive circuit with offset-compensation capability according to claim 5, wherein
said drive circuit includes
a transistor connected between a line of a first power-supply potential and said output node,
a constant-current source connected between said output node and a line of a second power-supply potential, and
a differential amplifier circuit controlling a gate potential of said transistor to allow a potential on said output node to be equal to said input potential.
10. A liquid-crystal display device comprising:
a drive circuit with offset-compensation capability recited in claim 5; and
a liquid-crystal cell having a light-transmission factor changing according to an output potential of said drive circuit with offset-compensation capability.