1. A method for encoding data blocks communicated over a network having a network layer and lower layers comprising:
intercepting with an intermediate device a plurality of different communication sessions;
extracting data blocks from the different communication sessions;
determining whether there is a match between the contents of each of the extracted data blocks and contents of at least one previously transmitted data block;
responsive to a match, encoding the respective extracted data block and transmitting the encoded respective extracted data block to at least one decoder module; and
responsive to no match, transmitting the respective extracted data block in intercepted form,
wherein the steps of intercepting, extracting, determining, encoding, and transmitting are performed in the network layer or lower layers.
2. The method of claim 1, wherein each extracted block has a destination address supported for decoding, further comprising passing through data not having a supported destination address.
3. The method of claim 1, further comprising responsive to a match, transmitting an indicator for identifying that the contents of a respective data block have been previously transmitted.
4. The method of claim 1, further comprising storing the contents of one or more data blocks previously transmitted.
5. The method of claim 4, wherein storing the contents of one or more data blocks previously transmitted comprises storing one or more previously transmitted unique data blocks in a least recently used data structure, the least recently used data structure having a maximum capacity, and each of the previously transmitted unique data blocks having a unique identifier and a position in an order of most recently used to least recently used of the one or more stored data blocks.
6. The method of claim 5, further comprising, responsive to a match, associating the previously transmitted data block having the matching contents with a position in the least recently used data structure indicating the most recently used previously transmitted data block.
7. The method of claim 5, further comprising, responsive to no match, storing the extracted data block in the least recently used data structure, and associating the position of most recently used with the extracted data block.
8. The method of claim 1, further comprising:
receiving routing information over the network from each of one or more corresponding decoder modules; and
determining one or more addresses supported by each respective decoder module from the routing information.
9. The method of claim 8, further comprising responsive to multiple decoder modules in the network supporting the same address, determining a destination decoder module for one or more extracted data blocks based upon network topology information and routing criteria.
10. The method of claim 1, further comprising:
storing a data structure for associating a signature with one or more of the previously transmitted data blocks;
computing a signature for the respective extracted data block;
comparing the computed signature with at least one signature associated with the one or more previously transmitted data blocks; and
responsive to a match in signature, selecting the one or more previously transmitted data blocks having the match in signature for content comparison with the respective extracted data block.
11. A method for decoding data communicated over a network having a network layer and lower layers comprising:
receiving data blocks for different communication sessions from an encoder module;
determining at a decoder module whether the contents of each of the received data blocks is encoded;
when a data block is encoded, selecting the contents of a matching previously received block as the contents for the encoded block; and
when a data block is unencoded, storing the contents of the respective received data block as a previously received data block,
wherein the steps of receiving, storing, determining, and selecting are performed in the network layer or lower layers.
12. The method of claim 11, further comprising storing the contents of one or more data blocks previously received from the encoder module.
13. The method of claim 12, wherein storing the contents of one or more data blocks previously received comprises storing one or more previously received unique data blocks in a least recently used data structure, the least recently used data structure having a maximum capacity, and each of the previously received unique data blocks having a unique identifier and a position in an order of most recently used to least recently used of the one or more previously received blocks.
14. The method of claim 11, further comprising responsive to data block being encoded, associating the previously received data block having the matching contents with a position in the least recently used data structure indicating the most recently used previously received data block.
15. The method of claim 11, further comprising responsive to the data block being unencoding, storing the respective received data block in the least recently used data structure, and associating the position of most recently used with the respective received data block.
16. A system for decreasing one or more repetitive data blocks in data communicated over a network having a network layer and lower layers comprising:
an encoder module coupled in the network; and
at least one corresponding decoder module coupled in the network,
wherein the encoder module intercepts the data, extracts data blocks from different communication sessions from the intercepted data, and determines whether there is a match between the contents of each of the extracted data blocks and the contents of at least one previously transmitted data block,
wherein responsive to a match, the encoder module encodes the respective extracted data block and transmits the encoded respective extracted data block to at least one decoder module,
wherein responsive to no match, the encoder module transmits the respective extracted data block in intercepted form to the at least one decoder module,
wherein the at least one corresponding decoder module receives data blocks for different communication sessions from the encoder module and determines whether the contents of each of the received data blocks is in encoded form,
wherein when a data block is encoded, the decoder module selects the contents of a matching previously received block as the contents for the encoded block,
wherein when the data block is unencoded, the decoder module stores the contents of the respective received data block as a previously received data block, and
wherein the steps of intercepting, extracting, determining, encoding, transmitting, receiving, and storing are performed in the network layer or lower layers.
17. The system of claim 16, wherein each extracted data block has a destination address supported for decoding by the at least one corresponding decoder module, and wherein the
encoder module passes through data not having a supported destination address.
18. The system of claim 16, further comprising responsive to a match, transmitting from the encoder module an indicator for identifying that the contents of a respective data block have been previously transmitted.
19. The system of claim 16, further comprising:
a first memory accessible to the encoder module for storing the contents of one or more data blocks previously transmitted by the encoder module; and
a second memory accessible to the decoder module for storing the contents of one or more data blocks previously received from the encoder module.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. An amplifier, comprising:
a front-end gain stage; and
an AC-coupled push-pull output stage, comprising:
a first transistor, having a source, a drain and a gate, wherein the source of the first transistor is coupled to a first voltage level;
a second transistor, having a source, a drain and a gate, wherein the source of the second transistor is coupled to a second voltage level, the gate of the second transistor is coupled to the front end gain stage, and the drain of the second transistor is coupled to the drain of the first transistor to form an output terminal of the amplifier; and
an AC-coupled capacitor, which is a passive two terminal electrical component coupled between the front-end gain stage and the gate of the first transistor.
2. The amplifier as claimed in claim 1, further comprising:
a resistance component, coupling the gate of the first transistor to a bias voltage level.
3. The amplifier as claimed in claim 1, further comprising:
a compensation circuit, coupled between the front-end gain stage and the output terminal of the amplifier.
4. The amplifier as claimed in claim 1, wherein:
the first transistor is a P-type transistor;
the second transistor is an N-type transistor; and
the first voltage level is higher than the second voltage level.
5. The amplifier as claimed in claim 1, wherein:
the first transistor is an N-type transistor;
the second transistor is a P-type transistor; and
the first voltage level is lower than the second voltage level.
6. A fully-differential amplifier, comprising:
a front-end gain stage, having a first terminal and a second terminal outputting a differential signal that has been amplified by the front-end gain stage;
a first AC-coupled push-pull output stage, comprising:
a first transistor, having a source, a drain and a gate, wherein the source of the first transistor is coupled to a first voltage level;
a second transistor, having a source, a drain and a gate, wherein the source of the second transistor is coupled to a second voltage level, the gate of the second transistor is coupled to the first terminal of the front-end gain stage, and the drain of the second transistor is coupled to the drain of the first transistor to form a first output terminal of the fully-differential amplifier; and
a first AC-coupled capacitor, coupled between the first terminal of the front-end gain stage and the gate of the first transistor; and
a second AC-coupled push-pull output stage, comprising:
a third transistor, having a source, a drain and a gate, wherein the source of the third transistor is coupled to the first voltage level;
a fourth transistor, having a source, a drain and a gate, wherein the source of the fourth transistor is coupled to the second voltage level, the gate of the fourth transistor is coupled to the second terminal of the front-end gain stage, and the drain of the fourth
transistor is coupled to the drain of the third transistor to form a second output terminal of the fully-differential amplifier; and
a second AC-coupled capacitor, coupled between the second terminal of the front-end gain stage and the gate of the third transistor;
wherein the fully-differential amplifier outputs a differential output signal via the first and second output terminals.
7. The fully-differential amplifier as claimed in claim 6, wherein:
the first AC-coupled push-pull output stage further comprises a first resistance component, coupling the gate of the first transistor to a bias voltage level; and
the second AC-coupled push-pull output stage further comprises a second resistance component, coupling the gate of the third transistor to the bias voltage level.
8. The fully-differential amplifier as claimed in claim 6, further comprising:
a first compensation circuit, coupled between the first terminal of the front-end gain stage and the first output terminal of the fully-differential amplifier; and
a second compensation circuit, coupled between the second terminal of the front-end gain stage and the second output terminal of the fully differential amplifier.
9. The fully-differential amplifier as claimed in claim 6, wherein:
the first and third transistors are P-type transistors;
the second and fourth transistors are N-type transistors; and
the first voltage level is higher than the second voltage level.
10. The fully-differential amplifier as claimed in claim 6, wherein:
the first and third transistors are N-type transistors;
the second and fourth transistors are P-type transistors; and
the first voltage level is lower than the second voltage level.
11. A delta-sigma modulator, comprising:
a feed-forward loop filter, comprising a plurality of integrators, wherein at least one of the plurality of integrators comprises the fully-differential amplifier as claimed in claim 5;
a quantizer coupled after the feed-forward loop filter; and
a z-delay component and a first digital-to-analog converter and a second digital-to-analog converter, wherein the z-delay component couples an output signal of the quantizer to the first and second digital-to-analog converters, respectively, to feedback control the feed-forward loop filter and the quantizer.
12. The delta-sigma modulator as claimed in claim 11, wherein a first-stage integrator between the plurality of integrators comprises the fully-differential amplifier.