1. A individual artificial composite log for use in vented and vent free gas log fire comprising:
a individual artificial gas log made of high temperature cement and a filler aggregate wet mix cast in a flexible mold to simulated a real log having at least one cut out in the log body where an inorganic ceramic fiber vacuum formed decorative pad which simulates the outer appearance of a real log is secured firmly inside the cut out;
a high temperature thin walled sleeve lining;
wherein a high temperature cement is used to secure the inorganic ceramic fiber vacuum formed pad to the concrete log;
wherein a high temperature thin walled sleeve lining may be installed;
wherein at least one high temperature coloring agent is used to simulate the outer and inner wood color of a real log;
wherein at least one cut out section provides at least one secondary air chamber, wherein the at least one secondary air chamber is at least 12 millimeters deep and at least 12 millimeters wide and the height of the secondary air chamber will be determined by the overall (size) diameter of the girth of the composite concrete log.
2. A individual composite concrete log as set forth in claim 1 in which the artificial concrete log is fitted with at least one inorganic ceramic fiber vacuum formed decorative pad which is secured in the main body cut out simulates an outer log surface and whereas the back surface of the inorganic ceramic fiber vacuum formed pad provides sufficient contact surface in the main body of the concrete log cut out to provide at least one vertical secondary air chamber having an open entry at the bottom of the concrete log and an open exit at the top of the concrete log.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method for modulating a work function of a fully silicided gate electrode comprising:
providing a layer on a gate dielectric, the layer comprising at least one lanthanide, a semiconductor material selected from the group consisting of Si, Ge, and SiGe, and a metal, and
transforming said layer into a fully silicided gate electrode by siliciding said semiconductor material, wherein an amount of the lanthanide and an amount of the metal present in the layer are selected such that the fully silicided gate electrode thus obtained has a predetermined work function.
2. The method according to claim 1, wherein providing a layer comprises:
implanting lanthanide ions into a surface of a semiconductor material provided on a gate dielectric, said semiconductor material selected from the group consisting of Si, Ge, and SiGe, and
depositing a metal layer upon said semiconductor material.
3. The method according to claim 2, wherein said step of implanting lanthanide ions is performed after the transforming step.
4. The method according to claim 2, wherein said step of implanting lanthanide ions is performed between the step of depositing said metal and the transforming step.
5. The method according to claim 2, wherein said gate dielectric is a high-k dielectric layer.
6. The method according to claim 2, wherein said gate dielectric is a high-k dielectric layer wherein k is greater than about 3.9.
7. The method according to claim 2, wherein said lanthanide is Yb.
8. The method according to claim 2, wherein the metal is Ni.
9. The method according to claim 2, wherein siliciding said semiconductor material comprises providing a thermal budget to convert substantially all of said semiconductor material into a silicide, and removing any unreacted metal.
10. The method according to claim 2, wherein the step of transforming said layer into a fully silicided gate electrode comprises:
providing a first thermal budget to partially convert said semiconductor material into a suicide,
removing any unreacted metal, and
providing a second thermal budget for completion of the conversion of said semiconductor material into a suicide.
11. The method according to claim 1, wherein providing the layer comprises depositing a layer comprising at least one lanthanide and a metal capable of silicidation upon or over a surface of a semiconductor material provided on a gate dielectric.
12. The method according to claim 11, wherein depositing said metal and said lanthanide comprises alternately depositing at least one layer of metal and at least one layer of lanthanide.
13. The method according to claim 12, wherein a last layer deposited in said alternating sequence is a metal layer.
14. The method according to claim 12, wherein said metal layer and said lanthanide layer arc deposited using sputtering.
15. The method according to claim 11, wherein said metal and said lanthanide are co-deposited.
16. The method according to claim 15, wherein said metal and said lanthanide are simultaneously sputtered.
17. The method according to claim 11 further comprising forming a capping layer over said deposited metal and said deposited lanthanide before the step of transforming said layer into a fully silicided gate electrode.
18. The method according to claim 11, further comprising selectively removing unreacted metal and unreacted lanthanide after forming the fully silicided gate electrode.
19. The method according to claim 11, wherein said gate dielectric is a high-k dielectric layer.
20. The method according to claim 11, wherein said gate dielectric is a high-k dielectric layer wherein K is greater than about 3.9.
21. The method according to claim 11, wherein said at least one lanthanide is Yb.
22. The method according to claim 11, wherein said metal is Ni.
23. The method according to claim 1, wherein the filly silicided gated electrode forms part of a nMOSFET device, and wherein the predetermined work function is smaller than about 4.5 eV.
24. The method according to claim 1, wherein the filly silicided gated electrode forms part of a nMOSFET device, and wherein the predetermined work function is from about 3.9 eV to about 4.5 eV.
25. The method according to claim 1, wherein the fully silicided gated electrode forms part of a nMOSFET device, and wherein the predetermined work function is from about 4 eV to about 4.2 eV.
26. The method according to claim 1, wherein the fully silicided gated electrode is an alloy of formula NixYbySi1-x-y wherein 0.3<x<0.7 and 0.005<y<0.2.
27. The method according to claim 26, wherein x=0.55 and y=0.12.
28. The method according to claim 2, wherein the filly silicided gate electrode comprises part of a NiYbSi FUSI gate.