1. A circuit for a compact and low power receiver, the circuit comprising:
a low-power low-noise amplifier (LNA) configured to amplify radio-frequency (RF) signals received from an RF antenna; and
a quadrature mixer coupled to a first and a second trans-impedance amplifiers (TIAs), wherein:
input and output nodes of the first and the second TIAs are cross-coupled via a first and a second resistor, and
the cross coupling is configured to create a complex impedance that replaces one or more LNA load inductors corresponding to one or more frequency bands of the receiver.
2. The circuit of claim 1, wherein the input and out nodes of the first cross coupled TIA are coupled to output and input nodes of the second cross coupled TIA, via the first and the second resistors, respectively.
3. The circuit of claim 1, wherein the created complex impedance is configured to replace the one or more LNA load inductors and to result in a substantial chip area reduction.
4. The circuit of claim 1, wherein the low power LNA comprises a complementary inverter-based LNA with no degeneration inductors.
5. The circuit of claim 4, wherein impedance matching is provided through one or more feedback capacitances including at least one of a parasitic capacitance or an additional on-chip feedback capacitance.
6. The circuit of claim 5, wherein the additional on-chip feedback capacitance is implemented parallel to the parasitic capacitance, and wherein the parasitic capacitance comprises a parasitic gate-drain capacitances.
7. The circuit of claim 5, wherein the low power LNA comprises a complementary inverter-based LNA, and wherein the parasitic capacitance comprises at least one of a parasitic gate-drain capacitance of NMOS or PMOS transistors of the complementary inverter-based LNA.
8. The circuit of claim 5, wherein the impedance matching comprises tunable matching and is provided through one or more programmable feedback capacitances.
9. The circuit of claim 1, wherein the LNA comprises a complementary inverter-based LNA, wherein the complementary inverter-based LNA is implemented on a substantially smaller area and is configured to consume approximately 50% less power, as compared to an inductor degenerated LNA.
10. A method for providing a compact and low power receiver, the method comprising:
providing a low-power low-noise amplifier (LNA);
configured the LNA to amplify radio-frequency (RF) signals received from an RF antenna;
coupling a quadrature mixer to a first and a second trans-impedance amplifiers (TIAs);
cross coupling input and output nodes of the first and the second TIAs via a first and a second resistor; and
configuring the cross coupling to create a complex impedance that replaces one or more LNA load inductors corresponding to one or more frequency bands of the compact and low power receiver.
11. The method of claim 10, further comprising coupling the input and out nodes of the first cross coupled TIA to output and input nodes of the second cross coupled TIA, via the first and the second resistors, respectively.
12. The method of claim 10, further comprising configuring the created complex impedance to substantially reduce chip area by replacing the one or more LNA load inductors.
13. The method of claim 10, further comprising implementing the low power LNA using a complementary inverter-based LNA with no degeneration inductors.
14. The method of claim 13, further comprising providing impedance matching through one or more feedback capacitances including at least one of a parasitic capacitance or an additional on-chip feedback capacitance.
15. The method of claim 14, further comprising implementing the additional on-chip feedback capacitance parallel to the parasitic capacitance, and wherein the parasitic capacitance comprises a parasitic gate-drain capacitances.
16. The method of claim 15, further comprising implementing the low power LNA using a complementary inverter-based LNA, and wherein the parasitic capacitance comprises at least one of a parasitic gate-drain capacitance of NMOS or PMOS transistors of the complementary inverter-based LNA.
17. The method of claim 10, further comprising providing impedance matching through a tunable matching provided through one or more programmable feedback capacitances.
18. The method of claim 10, further comprising:
implementing the low power LNA using a complementary inverter-based LNA; and
implementing the complementary inverter-based LNA on a substantially smaller area,
wherein the complementary inverter-based LNA is configured to consume approximately 50% less power, as compared to an inductor degenerated LNA.
19. A communication device comprising:
an radio-frequency (RF) antenna; and
a compact and low power receiver coupled to the RF antenna, the receiver comprising:
a low-power low-noise amplifier (LNA) configured to amplify RF signals received from the RF antenna; and
a quadrature mixer coupled to a first and a second trans-impedance amplifiers (TIAs),
wherein:
input and output nodes of the first and the second TIAs are cross-coupled via a first and a second resistor, and
the cross coupling is configured to create a complex impedance that replaces one or more LNA load inductors corresponding to one or more frequency bands of the receiver.
20. The communication device of claim 19, wherein:
the input and out nodes of the first cross coupled TIA are coupled to output and input nodes of the second cross coupled TIA, via the first and the second resistors, respectively, and
the low power LNA comprises a complementary inverter-based LNA with no degeneration inductors.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1-20. (canceled)
21. A film formation method comprising:
forming a film structure including a first metal contained film on a substrate;
processing the film structure to form a pattern of the film structure and a side wall on the substrate, the side wall contacting with a side surface of the first metal contained film in the pattern of the film structure; and
irradiating gas cluster ions into the side wall on the substrate.
22. The method according to claim 21, wherein
the film structure includes a second metal contained film, and the side wall contacts with the second metal contained film.
23. The method according to claim 21, wherein
the side wall where the gas cluster ions are irradiated is an insulating film.
24. The method according to claim 21, wherein
the gas cluster ions include nitrogen.
25. The method according to claim 21, wherein
the gas cluster ions include oxygen.
26. The method according to claim 21, wherein
the side wall is modified by irradiating the gas cluster ions into the side wall.
27. The method according to claim 21, wherein
an electrical insulation property of the side wall is improved by irradiating the gas cluster ions into the side wall.
28. The method according to claim 21, wherein
a number of atoms contained in the gas cluster ions is not less than 100 and not more than 20,000.
29. The method according to claim 21, wherein
a kinetic energy per atom contained in the gas cluster ions immediately before the irradiation is not less than 1 eV and not more than 30 eV.
30. The method according to claim 21, wherein
the first metal contained film is a lower electrode, the second metal contained film is an upper electrode in a memory unit of a resistance change memory.
31. The method according to claim 22, wherein
the pattern of the film structure further includes a metal oxide film between the first metal contained film and the second metal contained film.
32. The method according to claim 21, wherein
the pattern of the film structure includes a memory cell.
33. The method according to claim 22, wherein
the memory cell is a MTJ element unit of a resistance change memory or a memory unit of a resistance change memory,
the MTJ element unit including:
a lower electrode;
an alloy layer provided on the lower electrode;
a recording layer provided on the alloy layer, the recording layer including CoFeB;
a metal oxide film provided on the recording layer, the metal oxide film including MgO; and
a reference layer including CoFeB, or
the memory unit including:
a lower electrode;
a metal oxide film provided on lower electrode, the metal oxide film including at least one of MgO, TiO2, ZrO2, V2O5, Nb2O5, Ta2O5, TiO2, ZrO, VO, NbO, and TaO; and
an upper electrode provided on the metal oxide film.
34. The method according to claim 21, wherein
the film structure is processed by reactive ion etching to form the pattern of the film structure.
35. A memory device comprising:
a substrate;
a memory cell including a first metal contained film on a substrate; and
a side wall contacting with a side surface of the first metal contained film, and the side wall being irradiated by gas cluster ions.
36. The device according to claim 35, wherein
the memory cell includes a second metal contained film, and the side wall contacts with the second metal contained film.
37. The device according to claim 35, wherein
the side wall where the gas cluster ions are irradiated is an insulating film.
38. The device according to claim 35, wherein
the gas cluster ions include at least one of nitrogen and oxygen.
39. The device according to claim 36, wherein
the memory cell further includes a metal oxide film between the first metal contained film and the second metal contained film.
40. The device according to claim 35, further comprising:
a metal film electrically connected to the first metal contained film.