1. An apparatus comprising:
a virtually imaged phased array (VIPA) generator receiving an input light at a respective wavelength and having a double-hump shaped far field distribution, and producing a corresponding collimated output light traveling from the VIPA generator in a direction determined by the wavelength of the input light; and
a reflecting surface reflecting the output light back to the VIPA generator.
2. An apparatus as in claim 1, further comprising:
a lens or mirror focusing the output light traveling from the VIPA generator onto the reflecting surface so that the reflecting surface reflects the output light, the reflected light being directed by said lens or mirror back to the VIPA generator.
3. An apparatus as in claim 1, further comprising:
means for causing the input light received by the VIPA generator to have a double-hump shaped far field distribution.
4. An apparatus as in claim 1, further comprising:
at least one phase mask causing the input light received by the VIPA generator to have a double-hump shaped far field distribution.
5. An apparatus as in claim 1, further comprising:
a fiber providing the input light to the VIPA generator; and
at least one phase mask on the fiber to cause the input light received by the VIPA generator to have a double-hump shaped far field distribution.
6. An apparatus as in claim 1, further comprising:
at least one phase mask on a surface of the VIPA generator to cause the input light received by the VIPA generator to have a double-hump shaped far field distribution.
7. An apparatus comprising:
a virtually imaged phased array (VIPA) generator receiving an input light at a respective wavelength and having a double-hump shaped far field distribution, and producing a corresponding collimate output light traveling from the VIPA generator in a direction determined by the wavelength of the input light, the output light thereby being spatially distinguishable from an output light produced for an input light at a different wavelength;
a reflecting surface; and
a lens or mirror focusing the output light traveling from the VIPA generator onto the reflecting surface so that the reflecting surface reflects the output light, the reflected light being directed by said lens or mirror back to the VIPA generator.
8. An apparatus as in claim 7, further comprising:
means for causing the input light received by the VIPA generator to have a double-hump shaped far field distribution.
9. An apparatus as in claim 7, further comprising:
at least one phase mask causing the input light received by the VIPA generator to have a double-hump shaped far field distribution.
10. An apparatus as in claim 7, further comprising:
a fiber providing the input light to the VIPA generator; and
at least one phase mask on the fiber to cause the input light received by the VIPA generator to have a double-hump shaped far field distribution.
11. An apparatus as in claim 7, further comprising:
at least one phase mask on a surface of the VIPA generator to cause the input light received by the VIPA generator to have a double-hump shaped far field distribution.
12. An apparatus comprising:
an angular dispersive component having a passage area to receive light into, and to output light from, the angular dispersive component, the angular dispersive component receiving, through the passage area, an input light having a respective wavelength within a continuous range of wavelengths and having a double-hump shaped far field distribution, and causing multiple reflection of the input light to produce self-interference that forms a collimated output light which travels from the angular dispersive component along a direction determined by the wavelength of the input light and is thereby spatially distinguishable from an output light formed for an input light having any other wavelength within the continuous range of wavelengths; and
a reflecting surface reflecting the output light back to the angular dispersive component to undergo multiple reflection in the angular dispersive component and then be output from the passage area.
13. An apparatus as in claim 12, further comprising:
a lens or mirror focusing the output light traveling from the angular dispersive component onto the reflecting surface so that the reflecting surface reflects the output light, the reflected light being directed by said lens or mirror back to the angular dispersive component.
14. An apparatus as in claim 12, further comprising:
means for causing the input light received by the angular dispersive component to have a double-hump shaped far field distribution.
15. An apparatus as in claim 12, further comprising:
at least one phase mask causing the input light received by the angular dispersive component to have a double-hump shaped far field distribution.
16. An apparatus as in claim 12, further comprising:
a fiber providing the input light to the angular dispersive component; and
at least one phase mask on the fiber to cause the input light received by the angular dispersive component to have a double-hump shaped far field distribution.
17. An apparatus as in claim 12, further comprising:
at least one phase mask on a surface of the angular dispersive component to cause the input light received by the angular dispersive component to have a double-hump shaped far field distribution.
18. An apparatus comprising:
an angular dispersive component having a passage area to receive light into, and to output light from, the angular dispersive component, the angular dispersive component receiving, through the passage area, a line focused input light having a double-hump shaped far field distribution and causing multiple reflection of the input light to produce self-interference that forms a collimated output light which travels from the angular dispersive component along a direction determined by the wavelength of the input light and is thereby spatially distinguishable from an output light formed for an input light having a different wavelength; and
a reflecting surface reflecting the output light back to the angular dispersive component to undergo multiple reflection in the angular dispersive component and then be output from the passage area.
19. An apparatus as in claim 18, further comprising:
a lens or mirror focusing the output light traveling from the angular dispersive component onto the reflecting surface so that the reflecting surface reflects the output light, the reflected light being directed by the lens or mirror back to the angular dispersive component.
20. An apparatus as in claim 18, further comprising:
means for causing the input light received by the angular dispersive component to have a double-hump shaped far field distribution.
21. An apparatus as in claim 18, further comprising:
at least one phase mask causing the input light received by the angular dispersive component to have a double-hump shaped far field distribution.
22. An apparatus as in claim 18, further comprising:
a fiber providing the input light to the angular dispersive component; and
at least one phase mask on the fiber to cause the input light received by the angular dispersive component to have a double-hump shaped far field distribution.
23. An apparatus as in claim 18, further comprising:
at least one phase mask on a surface of the angular dispersive component to cause the input light received by the angular dispersive component to have a double-hump shaped far field distribution.
24. An apparatus comprising:
first and second reflecting surfaces, the second reflecting surface having a reflectivity which causes a portion of light incident thereon to be transmitted therethrough, where
an input light at a respective wavelength is focused into a line and has a double-hump shaped far field distribution, and
the first and second reflecting surfaces are positioned so that the input light radiates from the line to be reflected a plurality of times between the first and second reflecting surfaces and thereby cause a plurality of lights to be transmitted through the second reflecting surface, the plurality of transmitted lights interfering with each other to produce a collimated output light which travels from the second reflecting surface along a direction determined by the wavelength of the input light, and is thereby specially distinguishable from an output light formed for an input light having a different wavelength; and
a mirror surface reflecting output the light back to the second reflecting surface to pass through the second reflecting surface and undergo multiple reflection between the first and second reflecting surfaces.
25. An apparatus as in claim 24, further comprising:
a lens or light directing mirror focusing the output light traveling from the second reflecting surface onto the mirror surface so that the mirror surface reflects the output light, the reflected light being directed by said lens or light directing mirror back to the second reflecting surface.
26. An apparatus as in claim 24, further comprising:
means for causing the input light to have a double-hump shaped far field distribution.
27. An apparatus as in claim 24, further comprising:
at least one phase mask causing the input light to have a double-hump shaped far field distribution.
28. An apparatus as in claim 24, further comprising:
a fiber providing the input light to be focused into the line; and
at least one phase mask on the fiber to cause the input light to have a double-hump shaped far field distribution.
29. An apparatus as in claim 24, further comprising:
at least one phase mask on one of the group consisting of first and second reflecting surfaces, to cause the input light to have a double-hump shaped far field distribution.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method of operating digital logic circuitry to execute a finite field scalar multiplication of a multiplicand representative of a point in the finite field by a binary-valued scalar, comprising the steps of:
initializing one or more memory locations storing components of a sum, the sum representative of a point in the finite field; and
operating the digital logic circuitry to execute a plurality of operations comprising, for each of a plurality of bit positions in the scalar:
doubling an operand representative of one of the sum and the multiplicand;
responsive to the bit position having a \u201c1\u201d value, adding first and second operands, the first and second operands representative of the sum and the multiplicand; and
then advancing to a next bit position in the scalar;
wherein the doubling step is executed using an atomic pattern consisting of:
a first addition;
then a first multiplication followed by a second multiplication;
then a second addition;
then a third multiplication followed by a fourth multiplication;
then a third addition;
then a fifth multiplication;
then a fourth addition;
then a sixth multiplication followed by a seventh multiplication followed by an eighth multiplication;
then a fifth addition;
then a ninth multiplication;
then a sixth addition followed by a seventh addition;
then a tenth multiplication; and
then an eighth addition;
wherein the adding step is executed using an atomic pattern consisting of:
a first addition;
then a first multiplication followed by a second multiplication;
then a second addition;
then a third multiplication followed by a fourth multiplication;
then a third addition;
then a fifth multiplication;
then a fourth addition;
then a sixth multiplication followed by a seventh multiplication followed by an eighth multiplication;
then a fifth addition;
then a ninth multiplication;
then a sixth addition followed by a seventh addition;
then a tenth multiplication; and
then an eighth addition;
and wherein, following the executing step, the memory locations storing components of a sum represent the product of the multiplication.
2. The method of claim 1, wherein the second and fifth multiplications are squaring operations.
3. The method of claim 2, wherein the second and fifth through eighth additions comprises a subtracting operation.
4. The method of claim 1, wherein the second and fifth through eighth additions comprises a subtracting operation.
5. The method of claim 1, wherein the digital logic circuitry comprises a processor and a register file;
wherein the initializing step comprises:
loading projective coordinates corresponding to the multiplicand into first, second, and third register locations of the register file;
wherein each of the addition and multiplication operations that comprise the doubling and addition steps operate on operands comprising the contents stored in the register file;
wherein the results of the doubling and adding steps are stored in the first, second, and third register locations;
and wherein the operating step is performed for each of the second most significant to least significant bit positions of the scalar.
6. The method of claim 5, wherein constant register locations store coordinates of the multiplicand as constants;
wherein the doubling step doubles the sum;
and wherein the first operand of the adding step corresponds to the sum and the second operand of the adding step corresponds to the contents of the constant register locations.
7. The method of claim 1, wherein the multiplicand represents a point in a cyclic group that is a subset of points on an elliptic curve over the finite field, the elliptic curve represented by an equation of the short Weierstrass form.
8. The method of claim 1, wherein the plurality of operations executed by the digital logic circuitry further comprises subtracting the first and second operands using an atomic pattern consisting of:
a first addition;
then a first multiplication followed by a second multiplication;
then a second addition;
then a third multiplication followed by a fourth multiplication;
then a third addition;
then a fifth multiplication;
then a fourth addition;
then a sixth multiplication followed by a seventh multiplication followed by an eighth multiplication;
then a fifth addition;
then a ninth multiplication;
then a sixth addition followed by a seventh addition;
then a tenth multiplication; and
then an eighth addition.
9. A method of communicating a digital message with a digital signature, comprising the steps of:
generating a privatepublic key pair;
selecting a random number r;
executing a finite field scalar multiplication of a generator point in the finite field by the random number r to calculate a product point R in the finite field by performing a plurality of operations comprising:
initializing one or more memory locations storing components of a sum, the sum representative of a point in the finite field; and
operating digital logic circuitry to execute a plurality of operations comprising, for each of a plurality of bit positions in the random number r:
doubling an operand representative of one of the sum and the generator point;
responsive to the bit position having a \u201c1\u201d value, adding first and second operands, the first and second operands representative of the sum and the generator point; and
then advancing to a next bit position in the random number r;
computing a signature component by combining an inverse modulo of the random number r, a coordinate component of the product point R, and the private key k; and
transmitting the digital signature in combination with a digital signature comprising the coordinate component of the product point R and the computed signature component;
wherein the doubling step is executed using an atomic pattern consisting of:
a first addition;
then a first multiplication followed by a second multiplication;
then a second addition;
then a third multiplication followed by a fourth multiplication;
then a third addition;
then a fifth multiplication;
then a fourth addition;
then a sixth multiplication followed by a seventh multiplication followed by an eighth multiplication;
then a fifth addition;
then a ninth multiplication;
then a sixth addition followed by a seventh addition;
then a tenth multiplication; and
then an eighth addition;
and wherein the adding step is executed using an atomic pattern consisting of:
a first addition;
then a first multiplication followed by a second multiplication;
then a second addition;
then a third multiplication followed by a fourth multiplication;
then a third addition;
then a fifth multiplication;
then a fourth addition;
then a sixth multiplication followed by a seventh multiplication followed by an eighth multiplication;
then a fifth addition;
then a ninth multiplication;
then a sixth addition followed by a seventh addition;
then a tenth multiplication; and
then an eighth addition.
10. The method of claim 9, wherein the second and fifth multiplications are squaring operations.
11. The method of claim 10, wherein the second and fifth through eighth additions comprises a subtracting operation.
12. The method of claim 9, wherein the second and fifth through eighth additions comprises a subtracting operation.
13. The method of claim 9, wherein the digital logic circuitry comprises a processor and a register file;
wherein the initializing step comprises:
loading projective coordinates corresponding to the generator point into first, second, and third register locations of the register file;
wherein each of the addition and multiplication operations that comprise the doubling and addition steps operate on operands comprising the contents stored in the register file;
wherein the results of the doubling and adding steps are stored in the first, second, and third register locations;
and wherein the operating step is performed for each of the second most significant to least significant bit positions of the random number r.
14. The method of claim 9, further comprising:
storing x and y coordinates of the generator point in memory locations;
wherein the doubling step doubles the sum;
and wherein the first operand of the adding step corresponds to the sum, and the second operand of the adding step corresponds to the x and y coordinates of the generator point.
15. The method of claim 9, wherein the generator point represents a point in a cyclic group that is a subset of points on an elliptic curve over the finite field, the elliptic curve represented by an equation of the short Weierstrass form.
16. The method of claim 9, wherein the plurality of operations executed by the digital logic circuitry further comprises subtracting the first and second operands using an atomic pattern consisting of:
a first addition;
then a first multiplication followed by a second multiplication;
then a second addition;
then a third multiplication followed by a fourth multiplication;
then a third addition;
then a fifth multiplication;
then a fourth addition;
then a sixth multiplication followed by a seventh multiplication followed by an eighth multiplication;
then a fifth addition;
then a ninth multiplication;
then a sixth addition followed by a seventh addition;
then a tenth multiplication; and
then an eighth addition.