1. A multiple switch device for controlling and linking a plurality of switches disposed on a circuit board, comprising:
an operation button, comprising a handle and a rod fixed to the handle;
a shaft, comprising a connecting plate disposed at an end of the shaft, and a plurality of protruding plates disposed on the shaft;
wherein the rod is engaged with the connecting plate to securely connect the shaft and the operation button; and each of the protruding plates aligns with a corresponding one of the plurality of switches; and
at least one fixing base, supporting the shaft on the circuit board.
2. The multiple switch device as claimed in claim 1, wherein the rod of the operation button comprises a recessed portion, formed in a vicinity of an end of the rod.
3. The multiple switch device as claimed in claim 2, wherein the connecting plate comprises a U-shaped hole, defined in the recessed portion of the rod.
4. The multiple switch device as claimed in claim 1, wherein the at least one fixing base is L-shaped.
5. The multiple switch device as claimed in claim 1, wherein the at least one fixing base comprises a bottom portion and a slot formed therein.
6. An electronic device, comprising:
an operation button, comprising a handle and a rod fixed to the handle;
a faceplate, comprising a hole; wherein the operation button is inserted through the hole;
a shaft, comprising a connecting plate disposed at an end of the shaft, and a plurality of protruding plates disposed on the shaft; wherein the rod is engaged with the connecting plate to securely connect the shaft and the operation button;
at least one fixing base, supporting the shaft; and
a printed circuit board, comprising a plurality of switches disposed thereon; wherein each of the protruding plates aligns with a corresponding one of the plurality of switches, and when the shaft is moved by the handle, the protruding plates are controlled to operate the switches.
7. The electronic device as claimed in claim 6, wherein the rod comprises a pair of positioning pins and a recessed portion, the positioning pins are symmetrically disposed at an end of the rod in vicinity of the handle, and the recessed portion is disposed at the other end of the rod.
8. The electronic device as claimed in claim 7, wherein the faceplate further comprises at least one pair of concave portions formed in a wall encompassing the hole.
9. The electronic device as claimed in claim 7, wherein the connecting plate comprises a U-shaped hole, formed in the recessed portion of the rod.
10. The electronic device as claimed in claim 7, wherein the faceplate further comprises a restraining pin, corresponding to the positioning pins and restricting movement of the operation button in a clockwise or counterclockwise motion.
11. The electronic device as claimed in claim 6, wherein the at least one fixing base is L-shaped.
12. The electronic device as claimed in claim 6, wherein the at least one fixing base comprises a bottom portion and a slot disposed therein.
13. The electronic device as claimed in claim 7, wherein the hole of the faceplate is a threaded hole.
14. The electronic device as claimed in claim 13, further comprising a nut, inserted in the hole of the faceplate.
15. The electronic device as claimed in claim 14, wherein the nut comprises at least one pair of concave portions, receiving the positioning pins of the rod.
16. The electronic device as claimed in claim 15, wherein the nut further comprises a restraining pin, disposed between the concave portions.
17. An electronic device comprising:
a faceplate of said electronic device extending along a user-accessible side of said electronic device to cover said side of said electronic device;
at least two switches installable in said electronic device and spaced from said faceplate respectively;
an operation button installable at said faceplate and partially exposable out of said electronic device, said operation button movable through said faceplate to partially extend in said electronic device; and
a shaft extending in said electronic device beside said at least two switches and reachable to each of said at least two switches to simultaneously control switching of said at least two switches, said shaft connectively engagable with said operation button extending in said electronic device so as to move together with said operation button in order for simultaneously controlling said switching of said at least two switches based on user-drivable movement of said operation button.
18. The electronic device as claimed in claim 17, wherein said operation button comprises a positioning pin extending therefrom to engage with said faceplate for controlling said user-drivable movement of said operation button.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method of manufacturing an integrated circuit device, comprising:
providing a substrate; and
forming a free magnetic tunnel junction (MTJ) layer configured to switch between at least two different magnetic orientations over the substrate;
forming an insulating MTJ barrier layer arranged over the free MTJ layer; and
forming a pinned MTJ layer having a fixed magnetic orientation over the insulating MTJ barrier layer;
wherein the insulating MTJ barrier layer and the pinned MTJ layer have substantially aligned sidewalls which are disposed on an upper surface of the free MTJ layer.
2. The method of claim 1, wherein the substantially aligned sidewalls of the insulating MTJ barrier layer and the pinned MTJ layer are spaced apart from sidewalls of the free MTJ layer.
3. The method of claim 1, further comprising:
forming a mask over the pinned MTJ layer;
etching through at least the pinned MTJ layer where the pinned MTJ layer is exposed through the mask, the etch stopping above the free MTJ layer; and
forming a first sidewall barrier layer above the free MTJ layer and covering the sidewalls of the pinned MTJ layer.
4. The method of claim 3, wherein the first sidewall barrier layer is formed in-situ after etching through at least the pinned MTJ layer.
5. The method of claim 3, further comprising a masked etch through the free MTJ layer with the first sidewall barrier layer forming part of the mask.
6. The method of claim 5, further comprising forming a second sidewall barrier layer that covers the sidewalls of the free MTJ layer exposed by the masked etch.
7. The method of claim 6, wherein the second sidewall barrier layer is formed in-situ with the masked etch through the free MTJ layer.
8. The method of claim 3, further comprising treating the free MTJ layer in a region where it is exposed past the first sidewall barrier layer, whereby a portion of the free MTJ layer corresponding to the exposed region is rendered into a non-ferromagnetic state.
9. The method of claim 3, further comprising oxidizing the free MTJ layer through its entire thickness in a region where it is exposed past the first sidewall barrier layer.
10. The method of claim 1, further comprising:
forming a transistor in the substrate; and
coupling the transistor to the free MTJ layer through a bottom electrode.
11. A method of manufacturing an integrated circuit device, comprising:
receiving a semiconductor substrate;
forming a metal interconnect layer over the semiconductor substrate;
forming an interlayer dielectric (ILD) layer over the metal interconnect layer;
forming a bottom electrode layer over the ILD layer;
forming a free layer configured to switch between at least different magnetic orientations over the ILD layer;
forming an insulating barrier layer over the free layer; and
forming a pinned layer having a fixed magnetic orientation over the insulating barrier layer;
wherein the insulating barrier layer and the pinned layer have substantially aligned sidewalls.
12. An integrated circuit device, comprising:
a substrate;
a magnetic tunneling junction (MTJ) formed over a surface of the substrate, the MTJ comprising;
a free layer configured to switch between at least two different magnetic orientations, arranged over the surface of the substrate;
an insulating barrier layer arranged over the free layer; and
a pinned layer having a fixed magnetic orientation, arranged over the insulating barrier layer, wherein the pinned layer and the insulating barrier layer have substantially aligned sidewalls.
13. The integrated circuit of claim 12, wherein the MTJ further comprises a bottom electrode arranged between the free layer and the substrate, wherein the free layer is coupled directly to the bottom electrode.
14. The integrated circuit of claim 12, wherein the MTJ further comprises a top electrode disposed over the pinned layer.
15. The integrated circuit of claim 14, wherein the insulating barrier layer, the pinned layer, and the top electrode constitute a stack having substantially aligned sidewalls.
16. The integrated circuit of claim 12:
wherein the pinned layer and the insulating barrier layer have a first width measured between the substantially aligned sidewalls; and
wherein the free layer has a second width measured between its outer sidewalls, wherein the second width is greater than the first width.
17. The integrated circuit of claim 16, further comprising:
a first set of spacers resting on outer upper edges of free layer, and extending upwardly along the substantially aligned sidewalls of the pinned layer and the insulating barrier layer.
18. The integrated circuit of claim 16, further comprising:
a bottom electrode arranged between the free layer and the substrate, wherein the bottom electrode has a third width between its outer sidewalls, the third width being greater than the second width.
19. The integrated circuit of claim 18, further comprising:
a second set of spacers resting on outer upper edges of bottom electrode, and extending upwardly along outer sidewalls of free layer.
20. The integrated circuit of claim 19, further comprising:
a first set of spacers resting on outer upper edges of free layer, and extending upwardly along the substantially aligned sidewalls of the pinned layer and the insulating barrier layer, wherein the first set of spacers separates the second set of spacers from the substantially aligned sidewalls of pinned layer and insulating barrier layer.