1. A wide range input current circuitry for an analog to digital converter (ADC), the wide range input current circuitry comprising:
a port for receiving an input current;
a control circuitry;
a first resistor having a first resistance;
a first electronically controlled switch arranged to couple, responsive to said control circuitry, said port to said first resistor so as to provide a first current path for a first portion of the received input current, said first electronically controlled switch having a first area;
a second resistor having a second resistance, said second resistor coupled to the input of the ADC; and
a second electronically controlled switch arranged to couple said port to said second resistor so as to provide a second current path for a second portion of the received input current, said second electronically controlled switch having a second area,
wherein the ratio between the first area and the second area is equal to the ratio between the second resistance and the first resistance,
wherein said control circuitry is arranged to operate in a high current mode in the event that the input current exhibits an intensity within a first predetermined range and is arranged to operate in a low current mode in the event that the input current exhibits an intensity within a second predetermined range, said second predetermined range lower than the first predetermined range,
wherein in said high current mode said control circuitry is arranged to close said first electronically controlled switch so as to couple said port to said first resistor and thereby provide the first current path for the first portion of the received input current, and
wherein in said low current mode said control circuitry is arranged to open said first electronically controlled switch, said first electronically controlled switch arranged when opened to prevent the flow of the first portion of the received input current through said first resistor.
2. The circuitry of claim 1, wherein said second electronically controlled switch is responsive to said control circuitry.
3. The circuitry of claim 1, wherein a first end of said first resistor is coupled to a first terminal of said first electronically controlled switch, a first end of said second resistor is coupled to a first terminal of said second electronically controlled switch and a second terminal of said first electronically controlled switch is coupled to a second terminal of said second electronically controlled switch,
wherein the common node of said second resistor and said second electronically controlled switch is coupled to the input of the ADC, and
wherein the second terminal of said first electronically controlled switch and the second terminal of said second electronically switch are commonly coupled to said port.
4. The circuitry of claim 3, further comprising a differential amplifier, a first input of said differential amplifier coupled to a reference voltage, a second input of said differential amplifier coupled to the common node of said second resistor and said second electronically controlled switch and the output of said differential amplifier coupled to a control input of each of said first electronically controlled switch and said second electronically controlled switch,
wherein the output of said differential amplifier is arranged to control the amount of current flowing through each of said first electronically controlled switch and said second electronically controlled switch responsive to the difference between the reference voltage and the voltage across said second resistor.
5. The circuitry of claim 1, wherein said second electronically controlled switch is responsive to said control circuitry,
wherein said control circuitry is arranged in both said high current mode and low current mode to close said second electronically controlled switch,
wherein a first end of said first resistor is coupled to a first terminal of said first electronically controlled switch, a first end of said second resistor is coupled to a first terminal of said second electronically controlled switch and a second terminal of said first electronically controlled switch is coupled to a second terminal of said second electronically controlled switch,
wherein the common node of said second resistor and said second electronically controlled switch is coupled to the input of the ADC, and
wherein the second terminal of said first electronically controlled switch and the second terminal of said second electronically switch are commonly coupled to said port.
6. A method of providing a wide range of input currents for an analog to digital converter (ADC), the method comprising:
in the event that an input current exhibits an intensity within a first predetermined range, providing
a first current path for the input current through a first resistor, the first resistor having a first resistance, said first current path provided via a first electronically controlled switch having a first area, and
a second current path through a second resistor, the second resistor having a second resistance, said second current path provided via a second electronically controlled switch having a second area, the second resistor coupled to an input of the ADC, said first current path parallel to said second current path; and
in the event that the input current exhibits an intensity within a second predetermined range, lower than the first predetermined range, providing the second current path for the input current through the second resistor and not providing the first current path,
wherein the ratio between the area of the first electronically controlled switch and the area of the second electronically controlled switch is equal to the ratio between the second resistance and the first resistance.
7. The method of claim 6, wherein said providing the first current path through the first resistor comprises closing said first electronically controlled switch, and
wherein said providing the second current path through the second resistor comprises closing said second electronically controlled switch.
8. The method of claim 6, wherein a first end of the first resistor is coupled to a first terminal of the first electronically controlled switch, a first end of the second resistor is coupled to a first terminal of the second electronically controlled switch and a second terminal of the first electronically controlled switch is coupled to a second terminal of the second electronically controlled switch,
wherein the common node of the second resistor and the second electronically controlled switch is coupled to the input of the ADC, and
wherein the second terminal of the first electronically controlled switch and the second terminal of the second electronically switch are commonly coupled to receive the input current.
9. The method of claim 8, further comprising controlling the amount of current flowing through each of the first electronically controlled switch and the second electronically controlled switch responsive to the difference between the voltage across the second resistor and a reference voltage.
10. The method of claim 6, wherein said providing said first current path through the first resistor comprises closing said first electronically controlled switch,
wherein said providing the current path through the second resistor comprises closing said second electronically controlled switch,
wherein a first end of the first resistor is coupled to a first terminal of the first electronically controlled switch, a first end of the second resistor is coupled to a first terminal of the second electronically controlled switch and a second terminal of the first electronically controlled switch is coupled to a second terminal of the second electronically controlled switch,
wherein the common node of the second resistor and the second electronically controlled switch is coupled to the input of the ADC, and
wherein the second terminal of the first electronically controlled switch and the second terminal of the second electronically switch are commonly coupled to receive the input current.
11. A wide range input current circuitry for an analog to digital converter (ADC), the wide range input current circuitry comprising:
a means for receiving an input current;
a control means;
a first means for providing electrical resistance having a first resistance;
a first field effect transistor (FET) arranged to couple, responsive to said control circuitry, said means for receiving to said first means for providing electrical resistance so as to provide a first current path for a first portion of the received input current, said first FET having a first area;
a second means for providing electrical resistance, having a second resistance, coupled to the input of the ADC; and
a second FET arranged to couple said port to said means for receiving to said second means for providing electrical resistance so as to provide a second current path for a second portion of the received input current , said second FET having a second area;
wherein the ratio between the first area and the second area is equal to the ratio between the second resistance and the first resistance,
wherein said control means is arranged to operate in a high current mode in the event that the input current exhibits an intensity within a first predetermined range and is arranged to operate in a low current mode in the event that the input current exhibits an intensity within a second predetermined range, lower than the first predetermined range,
wherein in said high current mode said control circuitry is arranged to close said first FET thereby providing the second current path parallel to the first current path, and
wherein in said low current mode said control circuitry is arranged to open said first FET thereby preventing the presentation of the second current path parallel to the first current path.
12. The circuitry of claim 11,
wherein, responsive to both the high current mode and low current mode of said control circuitry, said control means is arranged to close said second FET so as to provide the first current path.
13. The circuitry of claim 11, wherein a first end of said first means for providing an electrical resistance is coupled to a first terminal of said first FET, a first end of said second means for providing an electrical resistance is coupled to a first terminal of said second FET and a second terminal of said first FET is coupled to a second terminal of said second FET,
wherein the common node of said second means for providing electrical resistance and said second FET is coupled to the input of the ADC, and
wherein the second terminal of said first FET and the second terminal of said second FET are arranged to receive the input current.
14. The circuitry of claim 13, further comprising a means for amplifying a voltage difference, a first input of said means for amplifying a voltage difference coupled to a reference voltage, a second input of said means for amplifying a voltage difference coupled to the common node of said second means for providing electrical resistance and said second FET and the output of said means for amplifying a voltage difference coupled to a control input of each of said first FET and said second FET,
wherein the output of said means for amplifying a voltage difference is arranged to control the amount of current flowing through each of said first FET and said second FET responsive to the difference between the reference voltage and the voltage across said second means for providing electrical resistance.
15. The circuitry of claim 11,
wherein said control means is arranged in both said high current mode and low current mode to close said second FET to thereby provide the second current path for the input current through said second means for providing electrical resistance,
wherein a first end of said first means for providing an electrical resistance is coupled to a first terminal of said first FET, a first end of said second means for providing an electrical resistance is coupled to a first terminal of said second FET and a second terminal of said first FET is coupled to a second terminal of said second FET,
wherein the common node of said second means for providing electrical resistance and said second FET is coupled to the input of the ADC, and
wherein the second terminal of said first FET and the second terminal of said second FET are commonly coupled to receive the input current.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A package comprising:
a die having a center, wherein the die comprises:
a first metal pad, wherein in a top view of the die, the first metal pad has a first center having a first distance from the center of the die;
a first metal pillar overlapping a portion of the first metal pad, with the first metal pillar being a non-solder metal pillar, wherein the first metal pillar has a second center having a second distance from the center of the die, and in a top view of the die, the first center and the second center have a connecting line perpendicular to an edge of the die;
a second metal pad having a third center shifted away from the center of the die; and
a second metal pillar overlapping a portion of the second metal pad, with the second metal pillar being a non-solder metal pillar, wherein the second metal pillar is electrically coupled to the second metal pad, and the second metal pillar has a fourth center shifted away from the third center, and in a top view of the die, the third center and the fourth center have a connecting line parallel to a line connecting the center of the die and a corner of the die.
2. The package of claim 1, wherein the second distance is greater than the first distance.
3. The package of claim 1, wherein an edge of the first metal pillar is shifted beyond a respective edge of the first metal pad.
4. The package of claim 1, wherein the first metal pillar is a copper-containing pillar.
5. The package of claim 1 further comprising:
a third metal pad having a fifth center shifted away from the center of the die; and
a third metal pillar overlapping a portion of the third metal pad, with the third metal pillar being a non-solder metal pillar, wherein the third metal pillar is electrically coupled to the third metal pad, and the third metal pillar has a sixth center aligned to the fifth center.
6. The package of claim 5, wherein the third metal pad has a third distance from the center of the die, with the third distance being smaller than the first distance and the second distance.
7. A package comprising:
a die having a center, wherein the die comprises:
a first metal pad having a first center in a top view of the die, wherein the first metal pad is elongated with a lengthwise size greater than a widthwise size, and wherein the first metal pad has a lengthwise direction parallel to a direction pointing from the center of the die to the center of the first metal pad;
a passivation layer over the first metal pad;
a polymer layer over the passivation layer; and
a first electrical connector extending into the passivation layer and the polymer layer to electrically couple to the first metal pad, wherein the first electrical connector has a second center in the top view of the die, with the second center shifted away from the first center in the direction pointing from the center of the die to the center of the first metal pad.
8. The package of claim 7, wherein the first electrical connector is elongated, and a lengthwise direction of the first electrical connector is parallel to the direction pointing from the center of the die to the center of the first metal pad.
9. The package of claim 7 further comprising:
a package component comprising an additional metal pad, wherein the additional metal pad of the package component has an additional center misaligned with the second center of the first electrical connector; and
a solder region bonding the first electrical connector to the additional metal pad of the package component.
10. The package of claim 7, wherein the first electrical connector comprises a copper pillar.
11. The package of claim 7, wherein edges of the first electrical connector are substantially perpendicular to a top surface of the first metal pad.
12. The package of claim 7 further comprising:
a second metal pad in the die, wherein the second metal pad has a third center in a top view of the die; and
a second electrical connector extending into the passivation layer and the polymer layer to electrically couple to the second metal pad, wherein the second electrical connector has a fourth center in the top view of the die, with the fourth center aligned to the third center.
13. The package of claim 12, wherein the third center and the fourth center are closer to the center of the die than the first center and the second center.
14. The package of claim 7, wherein an edge of the first electrical connector is shifted beyond a respective edge of the first metal pad.
15. A package comprising:
a die comprising:
a first metal pad;
a passivation layer comprising a portion over the first metal pad, wherein the passivation layer has an opening, with the opening having a first center in a top view of the die;
an Under-Bump Metallurgy (UBM) extending into the passivation layer to contact the first metal pad; and
a non-solder metal pillar over and contacting the UBM, wherein the non-solder metal pillar has a second center in the top view of the die, with the second center misaligned with the first center;
a package substrate comprising a second metal pad, wherein the second metal pad of the package substrate has a third center misaligned with the second center; and
a solder region bonding the non-solder metal pillar to the second metal pad.
16. The package of claim 15, wherein the die comprises a center and a corner, and the first center and the second center are aligned to a line connecting the center of the die and the corner of the die.
17. The package of claim 15, wherein the second center is between the first center and the third center.
18. The package of claim 15, wherein the first center is aligned to a line connecting a center of the die to the second center of the non-solder metal pillar.
19. The package of claim 18, wherein the line connecting a center of the die to the second center of the non-solder metal pillar is aligned to an additional line connecting the center of the die to a corner of the die.
20. The package of claim 15, wherein the first center is aligned to a center of the first metal pad.