1. A surgical instrument, comprising:
a handle portion;
a proximal frame portion coupled to said handle portion and defining a longitudinal axis;
an end effector for performing a surgical operation;
a lower rigid bar pivotally attached to said proximal frame portion and said end effector and extending therebetween, said lower rigid bar lying along a first plane; and
an upper rigid bar lying along a second plane that is not coplanar with said first plane and being pivotally attached to said proximal frame portion and said end effector and extending therebetween such that one end of at least one said upper and lower rigid bars is attached to said proximal frame portion along said longitudinal axis.
2. A surgical instrument, comprising:
a handle portion;
a proximal frame portion coupled to said handle portion and defining a longitudinal axis;
an end effector for performing a surgical operation;
an upper rigid bar having a distal end pivotally attached to said end effector for pivotal travel relative thereto about a first axis substantially transverse to said longitudinal axis and a proximal end pivotally attached to said proximal frame portion for pivotal travel relative thereto about a second axis that is substantially transverse to said longitudinal axis; and
a lower rigid bar having a distal end pivotally attached to said end effector for pivotal travel relative thereto about a third axis that is substantially transverse to said longitudinal axis and a proximal end pivotally attached to said proximal frame portion for pivotal travel relative thereto about a fourth axis that is substantially transverse to said longitudinal axis.
3. The surgical instrument of claim 2 wherein said proximal frame portion extends through a proximal closure tube segment operably coupled to said handle portion and wherein said surgical instrument further comprises a distal closure tube segment pivotally coupled to said proximal closure tube segment and constructed to apply closing and opening motions to said end effector.
4. The surgical instrument of claim 3 further comprising a flexible cover member extending between said proximal closure tube segment and said distal closure tube segment for preventing debris from entering therebetween.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. An integrated circuit package comprising:
a semiconductor chip having an integrated circuit formed thereon;
at least one pad in electrical communication with said integrated circuit;
an insulating layer overlaying said semiconductor chip, said insulating layer having an attachment surface for attaching said semiconductor chip to a substrate;
at least one via extending through said insulating layer from said attachment surface to said pad, said via comprising a first via opening proximate said pad and a second via opening proximate said attachment surface, wherein the centre of said second opening is laterally offset from the centre of said first opening in a direction away from a centre of said semiconductor chip;
a substrate;
a metallic material received in said via mechanically and electrically interconnecting said pad to said substrate, and attaching said semiconductor chip to said substrate.
2. The integrated circuit package of claim 1, wherein said via comprises a first via portion extending away from said pad along a first longitudinal axis and a second via portion extending away from said attachment surface along a second longitudinal axis, wherein said second longitudinal axis is laterally offset from the centre of said first longitudinal axis in a direction away from a centre of said semiconductor chip.
3. The integrated circuit package of claim 2, wherein said second longitudinal axis is offset from said first longitudinal axis outwardly along a line that passes through said centre of said semiconductor chip and said first longitudinal axis.
4. The integrated circuit package of claim 2, wherein said first longitudinal axis is laterally offset away from a centre of said pad in a direction away from said centre of said semiconductor chip.
5. The integrated circuit package of claim 2, wherein said pad is a back end of line (BEOL) pad.
6. The integrated circuit package of claim 2, wherein said second via portion has a cross-sectional area greater than a cross-sectional area of said first via portion.
7. The integrated circuit package of claim 6, wherein each one of said first and second via portions is frustoconical in shape and the minimum cross sectional area of said second via portion is greater than the maximum cross-sectional area of said first via portion.
8. The integrated circuit package of claim 2, wherein said insulating layer is formed of a polyimide.
9. The integrated circuit package of claim 2, wherein said insulating layer comprises first and second sub-layers, said first via portion extending through said first sub-layer and said second via portion extending through said second sub-layer.
10. The integrated circuit package of claim 2, further comprising a central via extending through said insulating layer from said attachment surface to one of said at least one pads, said central via comprising a first via portion extending away from said pad along a central longitudinal axis passing through the centre of said semiconductor chip, and a second via portion extending away from said attachment surface along said central longitudinal axis.
11. The integrated circuit package of claim 1, comprising at least one inter-layer dielectric (ILD) layer formed between said semiconductor chip and said insulating layer, wherein said ILD layer is formed of a material having a dielectric constant less than 2.7.
12. A method of manufacturing an integrated circuit die comprising a semiconductor chip having an integrated circuit formed thereon and at least one pad in electrical communication with said integrated circuit, said method comprising:
forming a first insulating layer overlaying said semiconductor chip;
forming a first via extending from said pad through said first insulating layer along a first longitudinal axis;
forming a second insulating layer overlaying said first insulating layer; and
forming a second via in communication with said first via, said second via extending through said second insulating layer along a second longitudinal axis, said second longitudinal axis offset away from said first longitudinal axis in a direction away from a centre of said die.
13. The method of claim 12, further comprising:
depositing a flowable metallic interconnecting structure in said first and second via;
inverting said integrated circuit die; and
interconnecting said integrated circuit die to a substrate by way of said interconnecting structure.
14. The method of claim 12, wherein said first longitudinal axis is offset from said pad in a direction away from said centre of said die.
15. The method of claim 12, wherein said forming said first via comprises exposing said first insulating layer using a photo-lithographic process and removing exposed regions of said first insulating layer using a developer and wherein said forming said second via comprises exposing said second insulating layer using a photo-lithographic process and removing exposed regions of said second insulating layer using a developer.
16. The method of claim 12, wherein said pad is a back end of line (BEOL) pad.
17. The method of claim 12, wherein said first and second vias are frustoconical in shape and the minimum cross-sectional area of said second via is greater than the maximum cross-sectional area of said first via.
18. An integrated circuit die, comprising:
a semiconductor chip with an integrated circuit thereon;
a plurality of pads in electrical communication with said integrated circuit;
an insulating layer overlying said integrated circuit die, said insulating layer having an attachment surface for attaching said semiconductor chip to a substrate;
a plurality of vias, each one of said vias extending through said insulating layer to a corresponding one of said pads for receiving a metallic structure to interconnect said integrated circuit die with a substrate;
wherein each one of said vias has a first opening proximate said semiconductor chip and a second opening proximate said attachment surface and a centre of said second opening is located farther from a centre of said integrated circuit die than the centre of said first opening.
19. An integrated circuit package, comprising:
a substrate;
a die comprising:
a semiconductor chip;
an insulating layer overlying said semiconductor chip;
a plurality of vias through said insulating layer;
a plurality of metallic interconnecting structures, each one of said interconnecting structures received in a corresponding one of said vias and each one of said metallic interconnecting structures bonded to said die at a first end and to said substrate at a second end, wherein said second end is located farther from the geometric centre of said die than said first end.
20. An integrated circuit die, comprising:
a semiconductor chip with an integrated circuit thereon;
a plurality of pads in electrical communication with said integrated circuit;
an insulating layer overlying said integrated circuit die, said insulating layer having an attachment surface for attaching said semiconductor chip to a substrate;
a first plurality of vias, arranged in a pattern, each one of said first plurality of vias extending through said insulating layer to a corresponding one of said pads for receiving a metallic structure to interconnect said integrated circuit die with a substrate;
wherein each one of said first plurality of vias has a first opening proximate said semiconductor chip and a second opening proximate said attachment surface and a centre of said first opening is laterally offset relative to a centre of said second opening by a first distance in a direction towards the centre of said integrated circuit die;
a second plurality of vias, arranged in a pattern concentric with said pattern of said first plurality of vias, each one of said second plurality of vias extending through said insulating layer to a corresponding one of said pads for receiving a metallic structure to interconnect said integrated circuit die with a substrate;
wherein each one of said second plurality of vias has a first opening proximate said semiconductor chip and a second opening proximate said attachment surface and a centre of said first opening is laterally offset relative to a centre of said second opening by a second distance different from said first distance in a direction towards the centre of said integrated circuit die.
21. The integrated circuit die of claim 20, wherein each one of said first plurality of vias is closer to said centre of said integrated circuit die than each one of said second plurality of vias and said second distance is larger than said first distance.
22. The integrated circuit die of claim 20, wherein at least one of said pattern of said first plurality of vias and said pattern of said second plurality of vias is generally rectangular.
23. An integrated circuit die, comprising:
a semiconductor chip with an integrated circuit thereon;
a plurality of pads in electrical communication with said integrated circuit;
an insulating layer overlying said integrated circuit die, said insulating layer having an attachment surface for attaching said semiconductor chip to a substrate;
a plurality of vias, each one of said vias extending through said insulating layer to a corresponding one of said pads for receiving a metallic structure to interconnect said integrated circuit die with a substrate;
wherein said plurality of vias are arranged in at least a first pattern centred at a centre of said integrated circuit die and a second pattern concentric with said first pattern, and each one of said vias has a first opening proximate said semiconductor chip and a second opening proximate said attachment surface, wherein a centre of said first opening is laterally offset from the centre of said second opening in a direction towards the centre of said integrated circuit die and wherein said offset is by a first distance in said vias arranged in said first pattern and by a second distance different from said first distance in said vias arranged in said second pattern.
24. The integrated circuit die of claim 23, wherein each one of said vias arranged in said second pattern is located farther from a centre of said integrated circuit die than each one of said vias arranged in said first pattern and said second distance is larger than said first distance.
25. The integrated circuit die of claim 23, wherein at least one of said first pattern and said second pattern is generally rectangular.