1460751846-0eb8c7c3-b7fa-4da4-b167-350acf8e8190

1. A computer system, comprising:
a server located in a first network that communicates with a client over a constant stateful connection that extends from a second private enterprise network through a gateway located between the second private enterprise network and the first network;
the server further communicating over a wireless connection initiated from a mobile device located outside the second private enterprise network over a mobile network and to the first network;
the mobile device accessing the second private enterprise network by using the server to route transactions between the mobile device and the local client over the wireless connection, through the gateway, and over the established constant stateful connection;
the server continuously maintaining the constant stateful connection independently of the connectivity status of the wireless connection with the mobile device and regardless of file transaction inactivity between any of the local client, the mobile device and the server so that a connection oriented and stateful communication path between the mobile device and the local client is completed through the server whenever new wireless connections are established between the mobile device and the server.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method of injecting one or more errors in data flowing into or out of a chip for the purpose of testing logic without breaking a link to or from the chip, comprising:
generating an error injection pattern indicating one or more bits of data on which a pseudo-random error is to be inserted; and
generating an error injection trigger indicating when the pseudo-random error is to be inserted,
wherein generating the error injection trigger includes generating the error injection trigger based on a pseudo-random number and a time mask, wherein the time mask indicates a frequency with which the pseudo-random error is inserted in the data.
2. The method of claim 1 further comprising inserting the pseudorandom error in the data based on the error injection pattern and the error injection trigger.
3. The method of claim 2 wherein inserting the pseudo-random error in the data includes inserting the pseudo-random error in the data on consecutive cycles or non-consecutive cycles.
4. The method of claim 1 wherein generating the error injection pattern includes generating the error injection pattern based on a fixed error injection mask, a rotated version of the fixed error injection mask, a randomized version of the fixed error injection mask or a randomized version of the rotated version of the fixed error injection mask.
5. The method of claim 1 further comprising reducing an amount of chip space required to insert the pseudo-random error in the data.
6. An apparatus for injecting one or more errors in data flowing into or out of a chip, comprising:
error injection logic including:
at least one register; and
at least one multiplexer coupled to the at least one register;
wherein the register is adapted to store a mask or a pseudo random number;
wherein the multiplexer is adapted to select an error injection mode;

wherein the apparatus is adapted to:
generate an error injection pattern indicating one or more bits of data on which a pseudo-random error is to be inserted; and
generate an error injection trigger indicating when the pseudorandom error is to be inserted.
7. The apparatus of claim 6 further comprising a logic gate coupled to the error injection logic;
wherein the apparatus is further adapted to employ the logic gate to insert the pseudo-random error in the data based on the error injection pattern and the error injection trigger.
8. The apparatus of claim 7 wherein the apparatus is further adapted to employ the logic gate to insert the pseudo-random error in the data on consecutive cycles or non-consecutive cycles.
9. The apparatus of claim 6 wherein the apparatus is further adapted to generate the error injection pattern based on a pseudo-random number.
10. The apparatus of claim 6 wherein the apparatus is further adapted to generate the error injection trigger based on a pseudo-random number and a time mask, wherein the time mask indicates a frequency with which the pseudo-random error is inserted in the data.
11. The apparatus of claim 6 wherein the apparatus is further adapted to generate the error injection pattern based on a fixed error injection mask, a rotated version of the fixed error injection mask, a randomized version of the fixed error injection mask or a randomized version of the rotated version of the fixed error injection mask.
12. The apparatus of claim 6 wherein the apparatus is further adapted to reduce an amount of chip space required to insert the pseudo-random error in the data.
13. A system for injecting one or more errors in data, comprising:
a first chip; and
a second chip coupled to the first chip and adapted to receive data from andor transmit data to the first chip;
wherein the second chip includes an apparatus for injecting one or more errors in data flowing into or out of the second chip having:
error injection logic including:
at least one register; and
at least one multiplexer coupled to the at least one register;
wherein the register is adapted to store a mask or a pseudo random number;
wherein the multiplexer is adapted to select an error injection mode;