What is claimed:
1. A method of manufacturing a semiconductor memory device, including (i) a memory cell comprised of a first MISFET and a (ii) second MISFET for a peripheral circuit, comprising the steps of:
(a) providing a semiconductor substrate, having a memory cell forming region and a peripheral circuit forming region, (i) with a first gate insulating film of said first MISFET formed on said memory cell forming region, a floating gate electrode of said first MISFET formed on said first gate insulating film, a second gate insulating film of said first MISFET formed on said floating gate electrode, and a control gate electrode of said first MISFET formed on said second gate insulating film, and (ii) with a third gate insulating film, associated with said second MISFET, formed on said peripheral circuit forming region, and a gate electrode of said second MISFET formed on said third gate insulating film;
(b) introducing an impurity into said memory cell forming region for forming a first semiconductor region in said substrate;
(c) introducing an impurity into said memory cell forming region for forming a second semiconductor region in said substrate,
wherein a dose introduced in said step (b) is higher than the dose in said step (c) such that a part of said first semiconductor region which is positioned under said floating gate electrode has an impurity concentration higher than that of a part of said second semiconductor region which is positioned under said floating gate electrode, and
wherein a channel forming region of said first MISFET is formed between said first semiconductor region and said second semiconductor region;
(d) introducing an impurity into said peripheral circuit forming region for forming a third semiconductor region in said substrate,
wherein a dose introduced in said step (b) is higher than the dose in said step (d);
(e) after said steps (b), (c), and (d), forming first side wall spacers on both of opposing side surfaces of said control gate electrode and said floating gate electrode of said first MISFET, and forming second side wall spacers on both of opposing side surfaces of said gate electrode of said second MISFET; and
(f) after said step (e), introducing an impurity into said peripheral circuit forming region for forming a fourth semiconductor region in said substrate,
wherein said first, second, third, and fourth semiconductor regions have a same conductivity type, respectively,
wherein said third and fourth semiconductor regions together serve as a drain region of said second MISFET, and
wherein carriers stored in said floating gate electrode are transferred between said floating gate electrode and said first semiconductor region by tunneling through said first gate insulating film.
2. A method of manufacturing a semiconductor memory device according to claim 1,
wherein in a writing operation hot carriers generated in said substrate are injected in said floating gate electrode, and
wherein in an erase operation said carriers stored in said floating gate electrode are transferred between said floating gate electrode and said first semiconductor region by tunneling through said first gate insulating film.
3. A method of manufacturing a semiconductor memory device according to claim 2, wherein said impurity in said step (b) is arsenic, and said impurity in said step (c) is arsenic.
4. A method of manufacturing a semiconductor memory device according to claim 1, wherein said impurity in said step (b) is arsenic, and said impurity in said step (c) is arsenic.
5. A method of manufacturing a semiconductor device according to claim 1,
wherein said first, second, third and fourth regions have the same conductivity type, respectively, taken from either an n-type or p-type conductivity.
6. A method of manufacturing a semiconductor memory device, including (i) a memory cell comprised of a first MISFET and (ii) a second MISFET for a peripheral circuit, comprising steps of:
(a) providing a semiconductor substrate, having a memory cell forming region and a peripheral circuit forming region, (i) with a first gate insulating film of said first MISFET formed on said memory cell forming region, a floating gate electrode of said first MISFET formed on said first gate insulating film, a second gate insulating film of said first MISFET formed on said floating gate electrode, and a control gate electrode of said first MISFET formed on said second gate insulating film, and (ii) with a third gate insulating film, associated with said second MISFET, formed on said peripheral circuit forming region, and a gate electrode of said second MISFET formed on said third gate insulating film;
(b) introducing an impurity into said memory cell forming region for forming a first semiconductor region in said substrate;
(c) introducing an impurity into said memory cell forming region for forming a second semiconductor region in said substrate,
wherein a dose introduced in said step (b) is higher than the dose in said step (c) such that a part of said first semiconductor region which is positioned under said floating gate electrode has an impurity concentration higher than that of a part of said second semiconductor region which is positioned under said floating gate electrode,
wherein a junction depth of said first semiconductor region is greater than a junction depth of said second semiconductor region such that an overlap area, in a plane view in parallel with a main surface of said substrate, between said floating gate electrode and said first semiconductor region is greater than an overlap area, in a plane view in parallel with said main surface, between said floating gate electrode and said second semiconductor region, and
wherein a channel forming region of said first MISFET is formed between said first semiconductor region and said second semiconductor region;
(d) introducing an impurity into said peripheral circuit forming region for forming a third semiconductor region in said substrate,
wherein a dose introduced in said step (b) is higher than the dose in said step (d);
(e) after said steps (b), (c), and (d), forming first side wall spacers on both of opposing side surfaces of said control gate electrode and said floating gate electrode of said first MISFET, and forming second side wall spacers on both of opposing side surfaces of said gate electrode of said second MISFET; and
(f) after said step (e), introducing an impurity into said peripheral circuit forming region for forming a fourth semiconductor region in said substrate,
wherein said first, second, third, and fourth semiconductor regions have a same conductivity type, respectively,
wherein said third and fourth semiconductor regions together serve as a drain region of said second MISFET, and
wherein carriers stored in said floating gate electrode are transferred between said floating gate electrode and said first semiconductor region by tunneling through said first gate insulating film.
7. A method of manufacturing a semiconductor memory device according to claim 6, wherein said impurity in said step (b) is arsenic, and said impurity in said step (c) is arsenic.
8. A method of manufacturing a semiconductor memory device according to claim 7,
wherein in a writing operation hot carriers generated in said substrate are injected in said floating gate electrode, and
wherein in an erase operation said carriers stored in said floating gate electrode are transferred between said floating gate electrode and said first semiconductor region by tunneling through said first gate insulating film.
9. A method of manufacturing a semiconductor memory device according to claim 6,
wherein in a writing operation hot carriers generated in said substrate are injected in said floating gate electrode, and
wherein in an erase operation said carriers stored in said floating gate electrode are transferred between said floating gate electrode and said first semiconductor region by tunneling through said first gate insulating film.
10. A method of manufacturing a semiconductor memory device according to claim 6,
wherein said first, second, third and fourth regions have the same conductivity type, respectively, taken from either an n-type or p-type conductivity.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A leadframe comprising:
a planar pad operable for mounting a workpiece, which has a predetermined range of operating temperature; and
a plurality of non-coplanar members operable as mechanical stabilizers configured to secure inserted objects, said members adjoining said pad.
2. The leadframe according to claim 1 wherein said members have shapes resembling elongated protrusions, dimples, or thorns, project from said leadframe at an angle and abut said pad.
3. The leadframe according to claim 1 wherein said non-coplanarity is provided by a bend in said members near their attachment to said leadframe pad.
4. The leadframe according to claim 2 wherein said angle is selected between an acute angle and a right angle.
5. An apparatus comprising:
a leadframe comprising a planar pad of a certain size, said leadframe pad operable for mounting a heat-generating workpiece, and a plurality of non-coplanar members operable as mechanical stabilizers configured to secure inserted objects, said members adjoining said pad;
a heat spreader having a planar pad of a size matching said leadframe pad size, and contours suitable for insertion of said leadframe members; and
said leadframe members inserted into said spreader contours so that said spreader pad touches said leadframe pad across said pad size.
6. The apparatus according to claim 5 wherein said heat spreader has contours, which match said leadframe members in number, location, and size so that said members fit into said contours to stabilize and secure said heat spreader relative to said leadframe during the encapsulation process.
7. The apparatus according to claim 5 wherein said spreader contours are shaped as indentations including grooves or holes.
8. The apparatus according to claim 5 further comprising an attachment of said spreader pad to said leadframe pad by a thermally conductive adhesive.
9. The apparatus according to claim 5 wherein said heat spreader is made of a material and has a size and thickness to operate as a heat sink during the first operational phase of said heat-generating workpiece.
10. A semiconductor device comprising:
a leadframe having first and second surfaces, a planar pad of a certain size, and a plurality of non-coplanar members adjoining said pad;
a heat spreader having first and second surfaces and a planar pad of a size matching said leadframe pad size, said spreader further having contours into which said leadframe members are inserted so that said first spreader pad surface touches said second leadframe pad surface across said pad size;
a semiconductor chip mounted on said first leadframe pad surface; and
encapsulation material covering said chip and uncovering said second spreader surface.
11. The device according to claim 10 wherein said second spreader surface is operable for attachment to external parts.
12. The device according to claim 10 wherein said heat spreader is made of a material and has a thickness to operate as a heat sink during the first operational phase of said semiconductor chip.
13. A method for fabricating a semiconductor device comprising the steps of:
providing a leadframe made from a planar metal sheet, said leadframe including a pad of a certain size, having first and second surfaces and a plurality of non-coplanar members operable as mechanical stabilizers configured to secure inserted objects, said members adjoining said pad;
providing a heat spreader having first and second surfaces, a planar pad of a size matching said leadframe pad size, and contours suitable for insertion of said leadframe members;
inserting said leadframe members into said spreader contours so that said first spreader pad surface touches said second leadframe pad surface across said pad size;
providing a semiconductor chip and mounting said chip on said first leadframe pad surface; and
encapsulating said mounted chip, while leaving said second spreader surface uncovered.
14. The method according to claim 13 further comprising the step of:
attaching said first spreader pad surface to said second leadframe pad surface using a thermally conductive adhesive.
15. The method according to claim 13 wherein said step of encapsulating comprises the steps of:
placing said spreader together with said inserted leadframe and the mounted chip on the bottom of the mold cavity so that said second spreader surface rests on the mold bottom;
closing said mold and transferring molding compound into said cavity, whereby movements of said spreader relative to said leadframe are inhibited by said leadframe members inserted into said spreader; and
polymerizing and hardening said molding compound.