1. An integrated circuit comprising a field-effect transistor including a source region, a drain region, and a channel region, the field effect transistor comprising:
a gate electrode having a lower edge below a lower edge of at least one of the source and drain regions;
a gate dielectric arranged between the channel region and the gate electrode;
a first insulator structure arranged between the gate electrode and at least a section of the source region; and
a second insulator structure arranged between the gate electrode and at least a section of the drain region, wherein at least one of the first and second insulator structures is structurally different from the gate dielectric and the first and the second insulator structures are asymmetric with respect to each other.
2. The integrated circuit of claim 1, wherein at least one geometric dimension of the first insulator structure differs from at least one geometric dimension of the second insulator structure by at least 10 percent.
3. The integrated circuit of claim 1, wherein the first insulator structure extends to a first depth within a semiconductor substrate and the second insulator structure extends to a second depth within the semiconductor substrate, the second depth differing from the first depth by at least 10 percent.
4. The integrated circuit of claim 3, wherein the second depth differs from the first depth by at least 50 percent.
5. The integrated circuit of claim 2, wherein the first insulator structure comprises a section having a first thickness and the second insulator structure has a second thickness differing from the first thickness by at least 10 percent.
6. The integrated circuit of claim 5, wherein the second thickness differs from the first thickness by at least 50 percent.
7. The integrated circuit of claim 6, wherein the gate dielectric has a thickness equal to one of the first thickness and the second thickness.
8. The integrated circuit of claim 6, wherein at least a portion of one of the first and second insulator structures comprises a Bird’s Beak structure that forms a wedge-shaped junction with a pattern surface of a semiconductor substrate in which the field-effect transistor is formed.
9. The integrated circuit of claim 1, wherein the gate electrode is arranged in a groove formed in a semiconductor substrate and extends between a pattern surface and a device depth of the semiconductor substrate, and the semiconductor substrate comprises the source, drain and channel regions.
10. The integrated circuit of claim 9, wherein the drain region extends between the pattern surface and a lower drain region edge that is formed at or above the device depth.
11. The integrated circuit of claim 10, wherein the lower drain region edge is aligned with a lower edge of the second insulator structure.
12. The integrated circuit of claim 9, wherein the source region extends between the pattern surface and a lower source region edge at or above the device depth.
13. The integrated circuit of claim 12, wherein the lower edge of the second insulator structure is aligned with a lower edge of the first insulator structure.
14. The integrated circuit of claim 12, wherein at least one of the source and drain regions comprises a heavily doped section adjacent the pattern surface and a low doped section extending between the heavily doped section and the channel region, wherein a lower edge of the low doped section is formed at or above the device depth and a lower edge of the heavily doped section is formed above the lower edge of the corresponding first or second insulator structure.
15. The integrated circuit of claim 1, wherein a portion of the channel region is formed below the gate electrode.
16. The integrated circuit of claim 1, wherein the source, drain and channel regions are formed within a semiconductor lamella extending along a longitudinal direction of a semiconductor substrate, the semiconductor lamella comprising vertical longitudinal sidewalls, the semiconductor lamella is confined in a pitch direction that extends perpendicular to the longitudinal direction by two insulator line structures, the two insulator line structures facing each other at the semiconductor lamella, and the semiconductor lamella has a lamella depth that exceeds the device depth.
17. The integrated circuit of claim 16, wherein the gate electrode extends with substantially the same profile between the insulator line structures.
18. The integrated circuit of claim 16, wherein:
the gate electrode comprises a main section and two corner sections;
the main section extends with substantially the same profile between the insulator line structures so as to form, with the semiconductor lamella, a device edge at each interface with the insulator line structures; and
each corner section is disposed between the semiconductor lamella and one of the insulator line structures and extends along one of the device edges, wherein electrical fields of the main section and the corner section superpose at two edge sections of the channel region extending along the device edges.
19. The integrated circuit of claim 18, wherein each corner section covers a sidewall of the semiconductor lamella in a uniform corner width along the corresponding device edge.
20. The integrated circuit of claim 18, wherein the device edge is U-shaped.
21. The integrated circuit of claim 16, wherein:
the gate electrode is arranged in a groove formed in a semiconductor substrate that comprises the source, drain and channel regions, the groove extends between a pattern surface of the semiconductor substrate and a device depth, and the groove further forms longitudinal sidewalls in a longitudinal direction with the insulator line structures and transverse sidewalls with the semiconductor lamella;
the semiconductor lamella comprises a semiconductor fin that is thinner than the semiconductor lamella, the semiconductor lamella extends in the longitudinal direction through the groove and, in a vertical direction, between an upper fin edge and a bottom of the groove; and
the channel region is formed at least partly within the semiconductor fin.
22. The integrated circuit of claim 21, wherein the gate electrode comprises two subsections facing each other at the semiconductor fin.
23. The integrated circuit of claim 21, wherein the upper fin edge is formed below the pattern surface.
24. The integrated circuit of claim 21, wherein the upper fin edge is formed below at least one of the lower edges of the insulator structures.
25. The integrated circuit of claim 21, wherein the semiconductor fin extends from one transverse sidewall to the other.
26. The integrated circuit of claim 25, wherein one of the first and second insulator structures is U-shaped and comprises two vertical insulator subsections, each vertical insulator subsection extending between the gate electrode and the semiconductor lamella, and a horizontal insulator subsection bearing on the semiconductor fin and connecting the vertical subsections.
27. The integrated circuit of claim 21, wherein the semiconductor fin is arranged adjacent one of the transverse sidewalls and is separated from the other transverse sidewall via a fin gap.
28. The integrated circuit of claim 27, wherein one of the first and second insulator structures fills at least an upper portion of the fin gap.
29. The integrated circuit of claim 21, wherein at least an upper section of the semiconductor fin has a fin width that enables a fully depleted operation mode.
30. The integrated circuit of claim 29, wherein the fin width is less than 40 nanometers.
31. The integrated circuit of claim 1, further comprising:
a storage capacitor coupled to the field-effect transistor such that the field-effect transistor and the storage capacitor are operable as a memory cell.
32. The integrated circuit of claim 31, wherein the first insulator structure extends to a first depth within a semiconductor substrate and the second insulator structure extends to a second depth within the semiconductor substrate, and the first depth exceeds the second depth by at least 50 percent.
33. The integrated circuit of claim 31, wherein the first insulator structure comprises a section of a first thickness and the second insulator structure has a second thickness, and the first thickness is greater than the second thickness by at least 50 percent.
34. The integrated circuit of claim 31, wherein the gate dielectric has a thickness being equal to one of the first thickness and the second thickness.
35. The integrated circuit of claim 31, wherein at least a portion of one of the first and second insulator structures comprises a Bird’s Beak structure that forms a wedge-shaped junction with a pattern surface of a semiconductor substrate in which the field-effect transistor is formed.
36. The integrated circuit of claim 31, wherein the source region comprises a heavily doped section adjacent the pattern surface and a low doped section extending between the heavily doped section and the channel region, a lower edge of the low doped section is formed at or above the device depth, and a lower edge of the heavily doped section is formed above the lower edge of the first insulator structure.
37. (canceled)
38. An electronic system comprising the integrated circuit of claim 1.
39. The integrated circuit of claim 1, wherein the gate electrode is arranged between the source region and the drain region.
40. The integrated circuit of claim 1, wherein at least one of the first and second insulator structures has a different thicknesses than the gate dielectric.
41. The integrated circuit of claim 1, wherein at least one of the first and second insulator structures extends into a semiconductor substrate to a different depth than the gate dielectric.
42. The integrated circuit of claim 1, wherein at least one of the first and second insulators comprises a different material than the gate dielectric.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A cleaning method for cleaning an object, the method comprising:
disposing the object in a cleaning liquid held in a cleaning tank; and
ultrasonically vibrating the cleaning liquid via an intermediate medium in contact with the cleaning tank,
wherein the ultrasonically vibrating includes:
ultrasonically vibrating the cleaning liquid with a first difference between respective sonic velocities allowable in the cleaning liquid and the intermediate medium; and
ultrasonically vibrating the cleaning liquid with a second difference between the respective sonic velocities allowable in the cleaning liquid and the intermediate medium,
wherein the second difference is different from the first difference.
2. The method of claim 1, wherein the ultrasonically vibrating the cleaning liquid via the intermediate medium includes modifying a temperature of the intermediate medium so as to change the first difference to the second difference in the respective sonic velocities.
3. The method of claim 2, wherein the modifying the temperature is performed using a heating member.
4. The method of claim 2, wherein the intermediate medium is degassed water, and
wherein the modifying the temperature includes varying a retention time of the degassed water being in contact with the cleaning tank.
5. The method of claim 1, wherein the ultrasonically vibrating the cleaning liquid via the intermediate medium includes
modifying a composition of the intermediate medium so as to change the first difference to the second difference in the respective sonic velocities.
6. The method of claim 5, wherein the ultrasonically vibrating the cleaning liquid via the intermediate medium further comprises:
ultrasonically vibrating the cleaning liquid with a third difference between the respective sonic velocities allowable in the cleaning liquid and the intermediate medium, the third difference being different from the first difference and the second difference.
7. A cleaning method for cleaning an object, the method comprising:
disposing the object in a first cleaning liquid held in a first cleaning tank;
ultrasonically vibrating the first cleaning liquid via a first intermediate medium in contact with the first cleaning tank;
disposing the object in a second cleaning liquid held in a second cleaning tank; and
ultrasonically vibrating the second cleaning liquid via a second intermediate medium in contact with the second cleaning tank,
wherein the first cleaning liquid and the first intermediate medium allow sonic velocities, respectively, having a first difference from each other,
wherein the second cleaning liquid and the second intermediate medium allow sonic velocities, respectively, having a second difference from each other, and
wherein the first and second differences are different from each other.
8. The method of claim 7, further comprising:
adjusting a temperature of at least one of the first intermediate medium and the second intermediate medium so as to set the first difference and the second difference differently.
9. The method of claim 8, wherein the adjusting the temperature is performed using a heating member.
10. The method of claim 8, wherein the first intermediate medium is degassed water, and
wherein the adjusting the temperature includes modifying a retention time of the first intermediate medium being in contact with the first cleaning tank.
11. The method claim 7, wherein the first intermediate medium and the second intermediate medium have mutually different compositions.