What is claimed is:
1. A thin-film magnetic head comprising:
a reproducing head including: a magnetoresistive element; a first shield layer and a second shield layer for shielding the magnetoresistive element, portions of the first shield layer and the second shield layer that face a recording medium being opposed to each other with the magnetoresistive element in between; a first insulating layer provided between the magnetoresistive element and the first shield layer and a second insulating layer provided between the magnetoresistive element and the second shield layer; and
a recording head including: a first magnetic layer and a second magnetic layer magnetically coupled to each other and each made up of at least one layer and including magnetic pole portions opposed to each other and placed in regions on a side of ends of the magnetic layers facing toward a recording medium; a gap layer placed between the pole portions of the first and second magnetic layers; and a thin-film coil at least part of which is placed between the first and second magnetic layers and insulated from the first and second magnetic layers; wherein:
the second shield layer includes a first portion placed in a plane the same as a plane in which the first shield layer is placed, the first portion being insulated from the first shield layer, and a second portion connected to the first portion and opposed to the first shield layer with the magnetoresistive element in between; and the second shield layer also functions as the first magnetic layer; and
the at least part of the thin-film coil is placed between the first portion of the second shield layer and the second magnetic layer.
2. The thin-film magnetic head according to claim 1, further comprising a conductive layer connected to the magnetoresistive element, wherein
at least part of the conductive layer is placed between the first shield layer and the first portion of the second shield layer, being insulated from the first shield layer and the first portion.
3. The thin-film magnetic head according to claim 2, further comprising a shield layer for shielding the at least part of the conductive layer.
4. A method of manufacturing a thin-film magnetic head comprising:
a reproducing head including: a magnetoresistive element; a first shield layer and a second shield layer for shielding the magnetoresistive element, portions of the first shield layer and the second shield layer that face a recording medium being opposed to each other with the magnetoresistive element in between; a first insulating layer provided between the magnetoresistive element and the first shield layer and a second insulating layer provided between the magnetoresistive element and the second shield layer; and
a recording head including: a first magnetic layer and a second magnetic layer magnetically coupled to each other and each made up of at least one layer and including magnetic pole portions opposed to each other and each located in a respective end region of the magnetic layers that faces toward a recording medium; a gap layer placed between the pole portions of the first and second magnetic layers; and a thin-film coil at least part of which is placed between the first and second magnetic layers and insulated from the first and second magnetic layers; wherein:
the second shield layer includes a first portion placed in a plane the same as a plane in which the first shield layer is placed, the first portion being insulated from the first shield layer by an insulating film, and a second portion connected to the first portion and opposed to the first shield layer with the magnetoresistive element in between, the first portion and the second portion being separate from each other; and the second shield layer also functions as the first magnetic layer; the method including the steps of:
forming the first shield layer and the first portion of the second shield layer to be placed in one plane and insulated from each other;
forming at least part of the thin-film coil on the first portion of the second shield layer such that the coil is insulated from the first portion;
forming the first insulating layer on the first shield layer;
forming the magnetoresistive element on the first insulating layer;
forming the second insulating layer on the magnetoresistive element;
forming the second portion of the second shield layer on the second insulating layer;
forming the gap layer on the second portion; and
forming the second magnetic layer on the gap layer.
5. The method according to claim 4, further including the step of forming at least part of a conductive layer to be connected to the magnetoresistive element such that the at least part of the conductive layer is placed between the first shield layer and the first portion of the second shield layer, the conductive layer being insulated from the first shield layer and the first portion by the insulating film.
6. The method according to claim 5, further including the step of forming a shield layer for shielding the at least part of the conductive layer.
7. The method according to claim 5, wherein a shield layer for shielding the at least part of the conductive layer is formed at the same time in the step of forming the second magnetic layer.
8. The method according to claim 5, wherein the at least part of the conductive layer and the at least part of the thin-film coil are formed in one step.
9. The method according to claim 5, wherein the at least part of the conductive layer is formed by plating.
10. The method according to claim 4, wherein the first shield layer and the first portion of the second shield layer are formed by plating.
11. A thin-film magnetic head material used for manufacturing a thin-film magnetic head, the head comprising:
a reproducing head including: a magnetoresistive element; a first shield layer and a second shield layer for shielding the magnetoresistive element, portions of the first shield layer and the second shield layer that face a recording medium being opposed to each other with the magnetoresistive element in between; a first insulating layer provided between the magnetoresistive element and the first shield layer and a second insulating layer provided between the magnetoresistive element and the second shield layer; and
a recording head including: a first magnetic layer and a second magnetic layer magnetically coupled to each other and each made up of at least one layer and including magnetic pole portions opposed to each other and placed in regions on a side of ends of the magnetic layers facing toward a recording medium; a gap layer placed between the pole portions of the first and second magnetic layers; and a thin-film coil at least part of which is placed between the first and second magnetic layers and insulated from the first and second magnetic layers; wherein:
the second shield layer includes a first portion placed in a plane the same as a plane in which the first shield layer is placed, the first portion being insulated from the first shield layer, and a second portion connected to the first portion and opposed to the first shield layer with the magnetoresistive element in between; and the second shield layer also functions as the first magnetic layer; the thin-film magnetic head material comprising:
the first shield layer;
the first portion of the second shield layer placed in the same plane as the first shield layer, being insulated from the first shield layer; and
at least part of the thin-film coil placed on the first portion of the second shield layer, being insulated from the first portion.
12. The thin-film magnetic head material according to claim 11, further comprising at least part of a conductive layer to be connected to the magnetoresistive element, wherein the at least part of the conductive layer is placed between the first shield layer and the first portion of the second shield layer, being insulated from the first shield layer and the first portion.
13. A method of manufacturing a thin-film magnetic head sub-structure used for a thin-film magnetic head that comprises:
a reproducing head including: a magnetoresistive element; a first shield layer and a second shield layer for shielding the magnetoresistive element, portions of the first shield layer and the second shield layer that face a recording medium being opposed to each other with the magnetoresistive element in between; a first insulating layer provided between the magnetoresistive element and the first shield layer and a second insulating layer provided between the magnetoresistive element and the second shield layer; and
a recording head including: a first magnetic layer and a second magnetic layer magnetically coupled to each other and each made up of at least one layer and including magnetic pole portions opposed to each other and each located in a respective end region of the magnetic layers that faces toward a recording medium; a gap layer placed between the pole portions of the first and second magnetic layers; and a thin-film coil at least part of which is placed between the first and second magnetic layers and insulated from the first and second magnetic layers; wherein:
the second shield layer includes a first portion placed in a plane the same as a plane in which the first shield layer is placed, the first portion being insulated from the first shield layer by an insulating film, and a second portion connected to the first portion and opposed to the first shield layer with the magnetoresistive element in between, the first portion and the second portion being separate from each other; and the second shield layer also functions as the first magnetic layer; the method of manufacturing the sub-structure including the steps of:
forming the first shield layer and the first portion of the second shield layer to be placed in one plane and insulated from each other; and
forming at least part of the thin-film coil on the first portion of the second shield layer such that the coil is insulated from the first portion.
14. The method according to claim 13, further including the step of forming at least part of a conductive layer to be connected to the magnetoresistive element such that the at least part of the conductive layer is placed between the first shield layer and the first portion of the second shield layer, the conductive layer being insulated from the first shield layer and the first portion by the insulating film.
15. The method according to claim 14, wherein the at least part of the conductive layer and the at least part of the thin-film coil are formed in one step.
16. The method according to claim 14, wherein the at least part of the conductive layer is formed by plating.
17. The method according to claim 13, wherein the first shield layer and the first portion of the second shield layer are formed by plating.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method for encrypting binary data blocks, comprising using at least one processing device to:
concatenate an input data block with a tag generating a tagged data block;
apply to the tagged data block a reversible scrambling process, the scrambling process providing a scrambled data block; and
apply to the scrambled data block a stream cipher encryption algorithm providing an encrypted data block, the scrambling process mixing bits of the tagged data block so that any modification of the encrypted data block has a probability of being detected after decryption at least equal to a difference between unity and two raised to a negative power of a tag length.
2. The method according to claim 1, further comprising steps of:
generating a tag to be concatenated with the input data block to be encrypted, wherein the scrambling process applied to the tagged data block is performed so that a modification of one bit in the encrypted data block has a probability of impacting the tag when the encrypted data block is decrypted at least equal to a difference between unity and two raised to a negative power of the tag length.
3. The method according to claim 1 wherein the scrambling process applies to the tagged data block at least three iterations of a Rijndael algorithm.
4. The method according to claim 1 wherein the stream cipher encryption algorithm combines each bit of the scrambled data block with a respective bit of a bit stream.
5. The method according to claim 4 wherein each bit of the scrambled data block is combined with a respective bit of the bit stream by a XOR logical operator.
6. The method according to claim 4 wherein the bit stream for encryption of the scrambled data block is generated by applying a cryptographic function to a counter value which is incremented each time the data block is changed in an external memory.
7. The method according to claim 1 wherein the stream cipher encryption algorithm comprises a bit stream generation step performed simultaneously with the scrambling step.
8. The method according to claim 1 wherein the tag comprises a random reference value.
9. The method according to claim 8 wherein the reference value is securely stored in a memory.
10. The method according to claim 9, further comprising steps of forming a reference block comprising the reference value of at least one data block, and applying the encryption method to the reference block so as to obtain an encrypted reference block which is stored in an external memory.
11. A method for decrypting an encrypted data block, comprising using at least one processing device to perform steps of:
applying to the encrypted data block a stream cipher decryption algorithm providing a scrambled data block; and
applying to the scrambled data block a reverse scrambling process, the reverse scrambling process providing a decrypted data block concatenated with a tag and corresponding to a scrambling process mixing bits of an input data block concatenated with the tag so that any modification of the encrypted data block has a probability of being detected at least equal to a difference between unity and two raised to a negative power of a tag length.
12. The method according to claim 11, further comprising steps of:
extracting the tag from the decrypted data block;
comparing at least a part of the tag with a reference value; and
generating an error signal if the part of the tag is different from the reference value, the scrambling process being applied to the input data block concatenated with the tag, so that a modification of one bit in the encrypted data block has a probability of impacting the tag when the encrypted data block is decrypted at least equal to a difference between unity and two raised to a negative power of the tag length.
13. The method according to claim 11 wherein the reverse scrambling process applies to the scrambled data block at least three iterations of a reverse Rijndael algorithm.
14. The method according to claim 11 wherein the stream cipher decryption algorithm combines each bit of the encrypted data block with a respective bit of a bit stream.
15. The method according to claim 14 wherein each bit of the encrypted data block is combined with a respective bit of the bit stream by a XOR logical operator.
16. The method according to claim 14 wherein the bit stream for decryption of the encrypted data block is generated by applying a cryptographic function to a counter value which is incremented each time the data block is changed in an external memory.
17. The method according to claim 11 wherein the tag comprises a random reference value.
18. The method according to claim 17 wherein the reference value is stored in a memory in a reference block comprising at least one reference value, said reference block being concatenated with a tag including a reference value and encrypted with said tag.
19. The method according to claim 18, further comprising steps of:
reading in the memory an encrypted reference block including the reference value of the data block; and
applying the decryption method to the read encrypted reference block to obtain the reference value of the data block.
20. An integrated circuit, comprising:
a processing unit;
a memory controller linked to an external memory through a memory bus, and configured to write and read data blocks in the external memory;
a scrambling module configured to generate from a tagged data block a scrambled data block;
a reverse scrambling module configured to retrieve a tagged data block from a scrambled data block;
an encryption module configured to apply to the scrambled data block a stream cipher encryption algorithm providing an encrypted data block to be stored in the external memory, the scrambling module mixing the bits of the tagged data block so that any modification of the encrypted data block has a probability of being detected at least equal to a difference between unity and two raised to a negative power of a tag length; and
a decryption module configured to apply to an encrypted data block read in the external memory a stream cipher decryption algorithm providing a scrambled data block.
21. The integrated circuit according to claim 20, further comprising:
a tag generator configured to generate a tag for an input data block to be encrypted;
means for concatenating the tag with the input data block, the scrambling module configured to scramble the block resulting from concatenation, so that a modification of one bit in the scrambled data block has a probability of impacting on every bit of the input data block and the tag at least equal to a difference between unity and two raised to a negative power of the tag length;
means for extracting a tag from a decrypted data block provided by the reverse scrambling module; and
a comparator configured to compare at least a part of the tag with a reference value and for generating an error signal if the part of the tag is different from the reference value.
22. The integrated circuit according to claim 20 wherein the scrambling module applies to the tagged data block at least three iterations of a Rijndael algorithm.
23. The integrated circuit according to claim 20 wherein the encryption module is configured to combine each bit of a scrambled data block with a respective bit of a bit stream.
24. The integrated circuit according to claim 23 wherein the encryption module comprises a XOR logical operator for combining each bit of the scrambled data block with a respective bit of the bit stream.
25. The integrated circuit according to claim 20 wherein the decryption module is configured to combine each bit of an encrypted data block with a respective bit of a bit stream.
26. The integrated circuit according to claim 25 wherein the decryption module comprises a XOR logical operator for combining each bit of the encrypted data block with a respective bit of the bit stream.
27. The integrated circuit according to claim 20, further comprising a bit stream generator for generating a bit stream for encryption and decryption, the bit stream generator comprising a counter providing a counter value and a cryptographic function encrypting the counter value.
28. The integrated circuit according to claim 27 wherein the bit stream generator is configured to generate a bit stream while a data block to be encrypted is processed by the scrambling module.
29. The integrated circuit according to claim 21 wherein the tag comprises a random reference value.
30. The integrated circuit according to claim 29 wherein the reference value is securely stored in a memory.
31. The integrated circuit according to claim 29, further comprising means for forming a reference block comprising the reference value of at least one data block, means for encrypting the reference block so as to obtain an encrypted reference block which is stored in the external memory, and means for decrypting a reference block which is read in the external memory.
32. An integrated circuit, comprising:
means for concatenating input data blocks to be encrypted with tags, generating tagged data blocks;
means for scrambling tagged data blocks, the means for scrambling being coupled to the means for concatenating;
means for encrypting scrambled data blocks coupled to the means for scrambling, the means for scrambling being configured to mix the bits of the tagged data blocks so that any modification of an encrypted data block has a probability of being detected at least equal to a difference between unity and two raised to a negative power of a tag length; and
means for decrypting encrypted scrambled data blocks.
33. The integrated circuit of claim 32, further comprising:
a processor configured to generate input data blocks; and
a memory controller configured to store encrypted, scrambled data blocks in an external memory.
34. The integrated circuit of claim 32, further comprising:
means for generating tags coupled to the means for scrambling tagged data blocks; and
means for comparing coupled to the means for generating tags and the means for decrypting encrypted scrambled data blocks.
35. The integrated circuit of claim 32, further comprising:
means for generating a binary stream coupled to the means for encrypting and the means for decrypting.
36. A method of controlling data storage in an external memory, comprising:
under control of at least one processing device,
adding a tag to an input data block to produce a tagged data block;
scrambling the tagged data block to produce a scrambled data block;
encrypting the scrambled data block, the tagged data block being scrambled so that any modification of the encrypted data block has a probability of detection at least equal to a difference between unity and two raised to a negative power of a tag length; and
storing the encrypted data block in the external memory.
37. The method of claim 36 wherein encrypting the scrambled data block comprises combining a bit stream with the scrambled data block.
38. The method of claim 36, further comprising:
retrieving a stored encrypted data block from the external memory;
decrypting the stored data block to produce a decrypted data block; and
descrambling the decrypted data block.
39. The method of claim 38 wherein descrambling the decrypted data block comprises separating a tag from a data portion of the decrypted data block.
40. The method of claim 39, further comprising comparing at least a portion of the tag to a reference value.
41. An integrated circuit, comprising:
a processor configured to generate and process data packets;
a memory controller configured to control transfers of data packets between the integrated circuit and an external memory; and
a data protector coupled to the processor and the memory controller and configured to:
add tags to data packets received from the processor to produce tagged data packets;
apply to tagged data packets a reversible scrambling process, the scrambling process providing scrambled data packets; and
encrypt scrambled data packets providing encrypted data packets, the scrambling process mixing bits of a tagged data packet so that any modification of an encrypted data packet has a probability of being detected at least equal to a difference between unity and two raised to a negative power of a tag length.
42. The integrated circuit of claim 41 wherein the data protector comprises:
a scrambling module configured to scramble tagged data packets; and
a random bit stream generator.
43. The integrated circuit of claim 42 wherein the data protector further comprises:
a descrambling module configured to descramble data packets received from the memory controller; and
a comparator.
44. A non-transitory computer-readable memory medium whose contents cause an embedded computing device to perform a method, the method comprising:
adding a tag to an input data block to produce a tagged data block;
scrambling the tagged data block by mixing bits in the tagged data block;
encrypting the scrambled data block using stream cipher encryption, the tagged data block being scrambled so that any modification of an encrypted data block has a probability of being detected after decryption at least equal to a difference between unity and two raised to a negative power of a tag length; and
storing the encrypted data block in an external memory.
45. The non-transitory computer-readable memory medium of claim 44 wherein the method further comprises:
retrieving an encrypted data block from the external memory; and
decrypting and unscrambling the retrieved data block.
46. The non-transitory computer-readable memory medium of claim 45 wherein the method further comprises:
comparing a portion of the unscrambled data block to a reference; and
selectively generating an error signal based on the comparison.