1. A visual simulator for a spectacle lens comprising:
a lens design data acquirer that acquires lens design data on design items of a spectacle lens including a prescription for a spectacle wearer’s naked eye;
a lens designer that designs the spectacle lens based on the lens design data;
an original image data acquirer that acquires an original image data;
a frame data acquirer that acquires frame data including shape data and layout information of a spectacle frame to which the spectacle lens is fitted;
an image processor that processes the original image data acquired by the original image data acquirer and generates image data representing an image viewed through a lens processed based on the frame data;
a display that comprises a screen that visually simulates by displaying the image based on the image data generated by the image processor;
a partial enlargement information acquirer that acquires partial enlargement information of a visual field, the partial enlargement information including a distance from a spectacle lens wearer to the screen of the display and a dimension of the screen, wherein
a processing mode of the image processor includes: an entire display mode in which the visual field based on the shape data is entirely displayed on the screen of the display; and a partial display mode in which a part of the visual field determined by the distance from the spectacle wearer to the screen of the display and the dimension of the screen acquired by the partial enlargement information acquirer is displayed,
the screen of the display is a flat display screen that satisfies the following relationship:
tan(\u03b8v2)tan(\u03b8h2)=DvDh\u2003\u2003(1)
L*tan(\u03b8h2)=K*Dh\u2003\u2003(2)
where a horizontal dimension of the flat display screen is Dh, a vertical dimension of the flat display screen is Dv, a distance from the spectacle wearer to the flat display screen is L, a horizontal angle of the visual field corresponding to the image displayed on the flat display screen is \u03b8h, a vertical angle of the visual field corresponding to the image displayed on the flat display screen is \u03b8v and K is a constant that satisfies a relationship of 0.35\u2266K\u22660.75.
2. The visual simulator for a spectacle lens according to claim 1, wherein the image processor includes an enlarged position image generator that generates an enlarged position image indicating a position and a size of the image displayed in the partial display mode within the spectacle frame,
3. The visual simulator for a spectacle lens according to claim 1, wherein the image processor receives a signal to switch between the entire display mode and the partial display mode and displays an image in the entire display mode or the partial display mode.
4. The visual simulator for a spectacle lens according to claim 1, wherein the spectacle lens is a progressive lens having a progressive surface.
5. A visual simulation method for a spectacle lens comprising:
acquiring lens design data on design items of a spectacle lens including a prescription for a naked eye of a spectacle wearer;
acquiring original image data;
designing the lens based on the lens design data;
acquiring frame data including shape data and layout information of a spectacle frame to which the spectacle lens is fitted;
processing the acquired original image data to generate image data viewed through a lens processed on the frame data; and
displaying the generated image data, wherein
in the displaying, the image data is visually simulated by displaying on a flat display screen,
the processing switches a processing mode between: an entire display mode in which a visual field of the spectacle frame is entirely displayed on the flat display screen; and a partial display mode in which a part of the visual field determined by a distance from the spectacle wearer to the flat display screen and a dimension of the flat display screen is displayed, and
the flat display screen satisfies the following relationship:
tan(\u03b8v2)tan(\u03b8h2)=DvDh\u2003\u2003(1)
L*tan(\u03b8h2)=K*Dh\u2003\u2003(2)
where a horizontal dimension of the flat display screen is Dh, a vertical dimension of the flat display screen is Dv, a distance from the spectacle wearer to the flat display screen is L, a horizontal angle of the visual field corresponding to the image displayed on the flat display screen is \u03b8h, a vertical angle of the visual field corresponding to the image displayed on the flat display screen is \u03b8v and K is a constant that satisfies a relationship of 0.35\u2266K\u22660.75.
6. A non-transitory computer readable recording medium storing computer executable instructions that when executed by a processor perform all steps of claim 5.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A system comprising:
control circuitry configured to provide one or more control pulses in response to a command signal, the one or more control pulses being communicated from the control circuitry to associated circuitry via a connection;
a detector configured to detect a disturbing signal that mitigates reception of the one or more control pulses via the connection, wherein the command signal is controlled to cause the control circuitry to provide one or more additional control pulses when the disturbing signal is detected by the detector to improve a likelihood of the reception of the one or more control pulses via the connection.
2. The system of claim 1 further comprising high-side circuitry residing in a high voltage isolation region of an integrated circuit device, the high-side circuitry being coupled to the control circuitry via the connection for receiving the one or more control pulses, the control circuitry residing in the integrated circuit device outside of the high voltage isolation region.
3. The system of claim 2, wherein the high-side circuitry further comprises a high-side driver that is configured to drive an external power FET connected to an output of the integrated circuit device responsive to the control FET operating based on the control signal.
4. The system of claim 2, wherein the control circuitry comprises a control field effect transistor (FET) coupled to the high-side circuitry, the control FET having a parasitic capacitance through which the disturbing signal passes corresponding to a disturbing condition of the high voltage isolation region.
5. The system of claim 4, wherein the disturbing condition is a slewing condition of the high voltage isolation region, the detector being configured to detect the slewing condition and provide a corresponding slew output signal indicative of the slewing condition.
6. The system of claim 4, wherein the control FET comprises a lateral double diffused metal-oxide-semiconductor (LDMOS) transistor for transmitting a signal from a low voltage region in which the LDMOS resides to the high voltage isolation region to control the high-side circuitry, the parasitic capacitance being between a gate and drain of the LDMOS transistor.
7. The system of claim 5, wherein the control circuitry further comprises:
a current source coupled between the control FET and ground, the current source controlling current flow through the control FET to control the high-side circuitry in response to the control signal; and
a controller configured to provide the control signal to turn on the current source.
8. The system of claim 7, wherein the controller further comprises logic configured to provide the control signal as a series of one or more pulses during the stewing condition responsive to the slew output signal.
9. The system of claim 8, wherein the logic is configured to provide one or more one additional command pulses to the control circuitry after the slewing condition ends, such that the control circuitry provides at least one additional pulse to the connection after the slewing condition ends.
10. The system of claim 7, wherein the control FET is a turn-on control FET and the control signal is a turn-on control signal, the system further comprising:
a turn-off control FET also coupled to the high-side circuitry, the turn-off control FET having a parasitic capacitance through which slew current passes during the slewing condition of the high voltage isolation region; and
a second current source coupled between the turn-off control FET and ground, the second current source controlling current flow through the turn-off control FET for controlling the high-side circuitry in response to a turn-off control signal provided by the controller,
wherein the slew detector is configured to detect the slewing condition based on the slew current passing through the parasitic capacitance of at least one of the turn-on control FET and the turn-off control FET.
11. The system of claim 5, wherein the control circuitry further comprises a clamp circuit coupled to maintain a gate voltage for the control FET, the clamp circuit and the control FET defining a cascode, the detector being coupled to the cascode to detect slew current during the slew condition and provide the slew output signal accordingly.
12. The system of claim 11, wherein the detector further comprises:
a sense resistor coupled between the clamp circuit and ground; and
a comparator configured to provide the slew output signal based on comparing a slew voltage across the sense resistor relative to a threshold voltage.
13. The system of claim 11, wherein the detector further comprises a comparator configured to provide the slew output signal based on comparing the gate voltage for the control FET relative to a threshold voltage.
14. An integrated circuit (IC), comprising:
a high voltage isolation region that comprises a high-side driver, the high-side driver having a driver output configured to provide a high-side voltage for driving a gate of an external transistor; and
a low voltage region outside of the high voltage isolation region, the low voltage region comprising:
a lateral double diffused metal-oxide-semiconductor (LDMOS) transistor coupled to transmit a signal from the low voltage region to the high voltage isolation region for controlling the high-side driver, the LDMOS transistor having a parasitic capacitance through which slew current passes during a slewing condition in the high voltage isolation region;
a current source coupled in series with the LDMOS transistor for effecting current flow through the LDMOS transistor in response to a control signal; and
a slew detector configured to provide a slew detection signal based on the slew current passing through the parasitic capacitance.
15. The IC of claim 14, further comprising a controller configured to provide the control signal to turn on the current source, the controller comprising logic configured to provide the control signal as a series of control pulses during the slewing condition, such that the current flow through the LDMOS transistor is a series of corresponding current pulses.
16. The IC of claim 15, wherein the controller is configured to provide at least one additional control pulse in the control signal after the slewing condition ends.
17. The IC of claim 15, wherein the LDMOS transistor is a first LDMOS transistor and the control signal is a turn-on control signal, the IC further comprising:
a second LDMOS transistor coupled to the high-side driver, the second LDMOS FET having a parasitic capacitance through which the slew current passes during the slewing condition of the high voltage isolation region; and
a second current source coupled in series with the second LDMOS transistor for effecting current flow through the second LDMOS transistor in response to a turn-off control signal from the controller,
wherein the slew detector is configured to detect the slewing condition based on the slew current passing through the parasitic capacitance of at least one of the first and second LDMOS transistors.
18. The IC of claim 14, wherein the low voltage region further comprises a clamp coupled to maintain a gate voltage for the LDMOS transistor, the clamp and the control FET defining a cascode, the slew detector being coupled to the cascode to detect the slewing condition and provide the slew detection signal accordingly.
19. The IC of claim 18, wherein the slew detector further comprises:
a sense resistor coupled in series with the clamp; and
a comparator configured to provide the slew output signal based on comparing a slew voltage across the sense resistor relative to a threshold voltage.
20. The IC of claim 18, wherein the slew detector further comprises a comparator configured to provide the slew output signal based on comparing the gate voltage for the LDMOS transistor relative to a threshold voltage.
21. The IC of claim 15 wherein the IC further comprises:
a low-side driver, the IC being coupled to drive a bridge circuit, the bridge circuit comprising:
a high-side power FET having a gate coupled to an output of the high-side driver, the high-side power FET being connected between a high voltage and a switching node; and
a low-side power FET connected between the switching node and ground, the low-side power FET having a gate coupled to an output of the low-side driver in the low voltage region of the IC.
22. A method for controlling a power device comprising:
generating one or more control pulses in response to a command signal, the one or more control pulses being communicated to a connection for controlling the power device;
detecting a disturbing condition associated with the connection that mitigates reception of the one or more control pulses via the connection; and
controlling the command signal in response the detection of the disturbing condition so that one or more additional control pulses are generated during the disturbing condition to thereby increase an effectiveness of the command signal.