1-8. (canceled)
9. A hydraulic fracturing system comprising:
a plurality of fracturing units, each unit comprising:
an engine,
a fracturing pump connected to the engine,
a low pressure inlet connected to the fracturing pump and supplying the fracturing pump with fracturing fluid,
a high pressure outlet connected to the fracturing pump and providing the pressurized fracturing fluid,
a fuel tank supplying fuel to the engine, and
a heat exchanger which accepts exhaust from the engine and transfers heat from the engine exhaust to flow back water and produced water from a well to produce steam; and
a low pressure manifold connected to the low pressure inlets on each fracturing pump;
a high pressure manifold connected to the high pressure outlets on each fracturing pump and collecting them into a single outlet to the well head;
a steam manifold which collects the steam produced within each fracturing unit; and
a forced cooling fractioning unit (FCFU) which accepts the steam and cools the steam.
10. (canceled)
11. (canceled)
12. The hydraulic fracturing system of claim 9 wherein:
the FCFU contains a plurality of segments, each one having a cooling section and a rising section with a drain positioned at the bottom of each cooling section.
13. The hydraulic fracturing system of claim 12 wherein:
each cooling section contains a plurality of cooling tubes providing a flow of coolant.
14. The hydraulic fracturing system of claim 13 wherein:
each cooling section contains a temperature probe which is used to determine the proper flow rate of coolant through the cooling tubes.
15. The hydraulic fracturing system of claim 12 wherein:
the FCFU converts the steam to distilled water which is then transported to holding tanks for re-use as fracturing fluid.
16-17. (canceled)
18. A hydraulic fracturing system comprising:
a plurality of fracturing units, each unit comprising:
an engine,
a fracturing pump connected to the engine,
a low pressure inlet connected to the fracturing pump and supplying the fracturing pump with fracturing fluid,
a high pressure outlet connected to the fracturing pump and providing the pressurized fracturing fluid,
a fuel tank supplying fuel to the engine,
a tube and shell heat exchanger which accepts engine coolant and transfers heat from the engine coolant to the FBWPW from a well,
a water heater which accepts the heated FBWPW from the tube and shell heat exchanger and adds further heat to increase purification rates,
a engine exhaust heat exchanger which accepts the heated FBWPW from the water heater and produces steam,
a pump which forces water through the heat exchanger and water heater,
an AC generator coupled to the engine and providing power to the water heater and the pump; and
a steam manifold which collects the steam produced within each fracturing unit.
19. The hydraulic fracturing system of claim 18 further comprising:
a forced cooling fractioning unit (FCFU) which accepts the steam and cools the steam.
20-23. (canceled)
24. A hydraulic fracturing system comprising:
a plurality of fracturing units, each unit comprising:
an engine,
a fracturing pump connected to the engine,
a low pressure inlet connected to the fracturing pump and supplying the fracturing pump with fracturing fluid,
a high pressure outlet connected to the fracturing pump and providing the pressurized fracturing fluid,
a fuel tank supplying fuel to the engine, and
a heat exchanger which accepts exhaust from the engine and transfers heat from the engine exhaust to fresh water to produce steam; and
a steam manifold which collects the steam produced within each fracturing unit and directs the steam into a forced cooled fractioning unit for condensation.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method for programming a Flash memory array, the method for programming comprising:
coupling at least one of a current source and a potential source to at least one selected bitline of the Flash memory array, the Flash memory array further comprising a plurality of Flash memory cells, each Flash memory cell comprising two transistors;
monitoring a potential VAVSS of an array VSS line by means of a comparator, the array VSS line being coupled to each of the plurality of Flash memory cells comprising the Flash memory array;
allowing the array VSS line to electrically float until the potential VAVSS is approximately equal to a reference potential Vref; and
terminating the programming by de-coupling at least one of the current source and the potential source.
2. The method of claim 1, where the reference potential Vref is approximately four volts.
3. The method of claim 1, where the method of coupling at least one of the current source and the potential source further comprises raising a bitline potential VBL of the selected bitline from approximately zero volts to approximately twelve volts in approximately 0.5 milliseconds.
4. A method for programming a Flash memory cell, the method comprising:
in a Flash memory cell comprising a select transistor and a double gate transistor, the select transistor including a drain terminal coupled to a bitline, a gate terminal coupled to a word line, and a source terminal coupled to a drain terminal of the double gate transistor, the double gate transistor further including a control gate terminal coupled to a select line and a source terminal coupled to an array VSS line, applying a potential of approximately zero volts to the select line;
applying a word line potential VWL to the word line in order to bias the select transistor into conduction;
increasing a bitline potential VBL applied to the bitline from approximately zero volts to a programming potential in a controlled time interval;
electrically floating the array VSS line;
terminating the increase of the bitline potential VBL when an array VSS line potential VAVSS approximately reaches a reference voltage Vref;
maintaining the bitline potential VBL at the programming potential for a program time interval;
returning the bitline potential VBL to approximately zero volts in a controlled time interval; and
coupling the array VSS line to a potential of approximately zero volts.
5. The method of claim 4, where the program time interval is approximately 4 milliseconds and the controlled time interval is approximately 0.5 milliseconds.
6. The method of claim 4 where the programming potential is approximately eleven to twelve volts and the reference voltage Vref is approximately four volts.
7. A Flash memory array, the Flash memory array comprising:
a plurality of Flash memory cells, each Flash memory cell including a select transistor and a double gate transistor, the select transistor having a drain terminal coupled to one of a plurality of array bitlines, a gate terminal coupled to one of a plurality of array word lines, and a source terminal coupled to a drain terminal of the double gate transistor, the double gate transistor further having a control gate terminal coupled to one of a plurality of select lines, and a source terminal coupled to an array VSS line,
a current source coupled to at least one of the plurality of the array bitlines, and
a voltage comparator coupled to the array VSS line and to a reference voltage source having a reference voltage potential Vref , an output of the voltage comparator coupled to the current source, the output of the voltage comparator configured to terminate the operation of the current source in response to an array VSS line potential VAVSS being approximately equal to the reference voltage potential Vref .
8. A Flash memory cell in a Flash memory array, the Flash memory cell comprising:
a select transistor including source, gate and drain terminals;
a double gate transistor including a control gate and a floating gate; the double gate transistor further having a source terminal, a drain terminal, and a control gate terminal, the control gate terminal coupled to the control gate, the double gate transistor further having a first capacitance value CONO between the control gate and the floating gate, and a second capacitance value Cg between the floating gate and at least one of the source connection and a bulk connection of the double gate transistor, the double gate transistor being constructed so as to exhibit a controlled first coupling ratio as given by CONO divided by the sum of CONO plus Cg, the double gate transistor being further constructed so as to exhibit a controlled second coupling ratio as given by Cg divided by the sum of CONO plus Cg;
a bitline connection coupled to a bitline of the Flash memory array and to the drain terminal of the select transistor;
a word line connection coupled to a word line of the Flash memory array and to the gate terminal of the select transistor;
a select line connection coupled to a select line of the Flash memory array and to the control gate terminal of the floating gate transistor;
an array VSS line connection coupled to the source terminal of the double gate transistor and to an array VSS line, the array VSS line being further coupled to a plurality of Flash memory cells, the array VSS line capable of being electrically floated during a program operation.
9. The Flash memory cell of claim 8 wherein the first coupling ratio has a value of approximately 0.7 to 0.75 and the second coupling ratio has a value of approximately 0.25.
10. The Flash memory cell of claim 8 wherein the second coupling ratio has a value of approximately 0.25.