1. A junction terminal accommodated in a connector housing to connect a pin terminal fitted on a case of an electric instrument with a receptacle terminal of a wiring harness connector, the junction terminal comprising:
a female electrical contact portion to electrically connect with the pin terminal of the electric instrument,
a male electrical contact portion to electrically connect with the receptacle terminal of the wiring harness connector, and
a bridging portion to connect the female electrical contact portion with the male electrical contact portion, wherein the male electrical contact portion is arranged such that a first longitudinal line passing an intermediate point of the male electrical contact portion aligns with a second longitudinal line passing an intermediate point of the female electrical contact portion.
2. The junction terminal as claimed in claim 1, wherein the male electrical contact portion is constructed so as to be correctly positioned by a positioning member attached to the connector housing.
3. A connector comprising:
a connector housing and
a junction terminal accommodated in the connector housing to connect a pin terminal fitted on a case of an electric instrument with a receptacle terminal of a wiring harness connector,
wherein the junction terminal has a female electrical contact portion to electrically connect with the pin terminal of the electric instrument, a male electrical contact portion to electrically connect with the receptacle terminal of the wiring harness connector, and a bridging portion to connect the female electrical contact portion with the male electrical contact portion, wherein the male electrical contact portion is arranged such that a first longitudinal line passing an intermediate point of the male electrical contact portion aligns with a second longitudinal line passing an intermediate point of the female electrical contact portion.
4. The junction terminal as claimed in claim 3, wherein the male electrical contact portion is constructed so as to be correctly positioned by a positioning member attached to the connector housing.
5. The junction terminal as claimed in claim 4, wherein the positioning member has a through hole to pass the male electrical contact portion of the junction terminal, and a cross section of the male electrical contact portion fits in the through hole to position the junction terminal in the connecter housing.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method for controlling the impedance of a buffer having a plurality of pull-up transistors and a plurality of pull-down transistors, the method comprising:
receiving a data output signal, the data output signal being selected from one of a test data output signal and a normal data output signal;
receiving an output enable signal;
receiving a termination enable signal;
receiving a first plurality of impedance control bits, a second plurality of impedance control bits, a third plurality of impedance control bits, and a fourth plurality of impedance control bits;
enabling, when the output enable signal is in a first state and the data output signal is in a first state, one or more of the plurality of pull-up transistors determined by the first plurality of impedance control bits;
enabling, when the output enable signal is in a first state and the data output signal is in a second state, one or more of the plurality of pull-down transistors determined by the second plurality of impedance control bits; and
enabling, when the termination enable signal is in a first state, one or more of the plurality of pull-up transistors determined by the third plurality of impedance control bits and one or more of the plurality of pull-down transistors determined by the fourth plurality of impedance control bits;
wherein the first and second pluralities of impedance control bits are independently controlled with respect to the third and fourth pluralities of bits.
2. The method of claim 1, wherein:
the first state is a logic high state; and
the second state is a logic low state.
3. The method of claim 1, wherein:
each of the first plurality of impedance control bits corresponds to one of the plurality of pull-up transistors;
each of the second plurality of impedance control bits corresponds to one of the plurality of pull-down transistors;
each of the third plurality of impedance control bits corresponds to one of the plurality of pull-up transistors; and
each of the fourth plurality of impedance control bits corresponds to one of the plurality of pull-down transistors.
4. The method of claim 3, wherein:
enabling one or more of the plurality of pull-up transistors comprises enabling one or more of a first plurality of pre-drivers, each of the first plurality of pre-drivers being connected to a respective one of the one or more pull-up transistors; and
enabling one or more of the plurality of pull-down transistors comprises enabling one or more of a second plurality of pre-drivers, each of the second plurality of pre-drivers being connected to a respective one of the one or more pull-up transistors.
5. The method of claim 4, wherein:
each of the first plurality of pre-drivers is connected to one of the first plurality of impedance control bits and one of the third plurality of impedance control bits for enabling a corresponding one of the plurality of pull-up transistors; and
each of the second plurality of pre-drivers is connected to one of the second plurality of impedance control bits and one of the fourth plurality of impedance control bits for enabling a corresponding one of the plurality of pull-down transistors.
6. The method of claim 5, wherein:
each of the first plurality of pre-drivers is connected to the data output signal, the output enable signal, and the termination enable signal; and
each of the second plurality of pre-drivers is connected to the data output signal, the output enable signal, and the termination enable signal.
7. The method of claim 4, further comprising:
providing a first supply voltage to the first plurality of pre-drivers; and
providing a second supply voltage to the plurality of pull-up transistors.
8. The method of claim 7, wherein the first supply voltage is different from the second supply voltage.
9. The method of claim 8, wherein the first supply voltage is greater than the second supply voltage.
10. The method of claim 1, further comprising:
calibrating the first, second, third, and fourth pluralities of impedance control bits.
11. The method of claim 10, wherein calibrating comprises:
calibrating the first plurality of impedance control bits for when the output enable signal is in the first state and the data output signal is in the first state;
calibrating the second plurality of impedance control bits for when the output enable signal is in the first state and the data output signal is in the second state;
calibrating the third plurality of impedance control bits for when the termination enable signal is in the first state; and
calibrating the fourth plurality of impedance control bits for when the termination enable signal is in the first state.
12. The method of claim 10, wherein calibrating comprises:
calibrating the first plurality of impedance control bits for when the output enable signal is in the first state and the data output signal is in the first state, to produce a first calibration result;
calibrating the second plurality of impedance control bits for when the output enable signal is in the first state and the data output signal is in the second state, using the first calibration result;
calibrating the third plurality of impedance control bits for when the termination enable signal is in the first state, to produce a second calibration result; and
calibrating the fourth plurality of impedance control bits for when the termination enable signal is in the first state, using the second calibration result.
13. The method of claim 1, wherein each of the plurality of pull-up transistors is sized to provide identical impedances.
14. The method of claim 13, wherein each of the plurality of pull-down transistors is sized to provide identical impedances.
15. The method of claim 1, wherein the test data output signal and the normal data output signal are received by a multiplexer, and one of the test data output signal and the normal data output signal is selected as the selected data output signal in response to a control signal supplied to the multiplexer.
16. A method for controlling the impedance of a buffer having a plurality of pull-up transistors and a plurality of pull-down transistors, the method comprising:
receiving a data output signal;
receiving an output enable signal;
receiving a termination enable signal;
generating a drive pull-up signal based on the states of the output enable signal and the data output signal, a drive pull-down signal based on the states of the output enable signal and the data output signal, and a termination control signal based on the states of the termination enable signal and the output enable signal;
using a level translator circuit to produce a higher-voltage drive pull-up signal based on the drive pull-up signal, a higher-voltage drive pull-down signal based on the drive pull-down signal, and a higher-voltage termination control signal based on the termination control signal;
providing the higher-voltage drive pull-up signal and the higher-voltage termination control signal to a first plurality of pre-driver circuits each coupled to a respective one of the plurality of pull-up transistors;
providing the higher-voltage drive pull-up signal and the higher-voltage termination control signal to a second plurality of pre-driver circuits each coupled to a respective one of the plurality of pull-down transistors;
receiving a first plurality of impedance control bits, a second plurality of impedance control bits, a third plurality of impedance control bits, and a fourth plurality of impedance control bits, wherein the first plurality of impedance control bits and the third plurality of impedance control bits are received by the first plurality of pre-driver circuits and the second plurality of impedance control bits and the fourth plurality of impedance control bits are received by the second plurality of pre-driver circuits;
enabling, when the output enable signal is in a first state and the data output signal is in a first state, one or more of the plurality of pull-up transistors determined by the first plurality of impedance control bits;
enabling, when the output enable signal is in a first state and the data output signal is in a second state, one or more of the plurality of pull-down transistors determined by the second plurality of impedance control bits; and
enabling, when the termination enable signal is in a first state, one or more of the plurality of pull-up transistors determined by the third plurality of impedance control bits and one or more of the plurality of pull-down transistors determined by the fourth plurality of impedance control bits;
wherein the first and second pluralities of impedance control bits are independently controlled with respect to the third and fourth pluralities of bits.