I claim:
1. A method of making a high quality crystalline film on a non-lattice matched substrate, comprising the steps of:
depositing a first buffer layer onto the substrate,
depositing a second buffer layer on top of the first buffer layer, and
depositing a crystalline film layer on top of the second buffer layer.
2. A method as claimed in claim 1, wherein the second buffer layer deposition temperature is different from the first buffer layer deposition temperature.
3. A method as claimed in claim 1 or claim 2, wherein the first buffer layer is AlxGa1xN and the second buffer layer is gallium nitride.
4. A method as claimed in any one of claims 1 to 3, wherein the crystalline film is AlxInyGa(1xy)N.
5. A method as claimed in any one of claims 1 to 4, wherein the substrate is sapphire.
6. A method, as claimed in any one of claims 1 to 5, wherein the first buffer layer is 10 to 50 nm thick.
7. A method, as claimed in any one of claims 1 to 6, wherein the second buffer layer is 100 nm to 1500 nm thick.
8. A method as claimed in any one of claims 1 to 7, wherein the first buffer layer deposition temperature is 400 C. to 780 C.
9. A method as claimed in any one of claims 1 to 8, wherein the second buffer layer deposition temperature is 600 C. to 730 C.
10. A method as claimed in any one of claims 1 to 9, wherein the film deposition temperature is 730 C. to 800 C.
11. A high quality crystalline film, deposited onto a substrate via a double layer buffer, wherein the two layers of the buffer reduce the strain between the film and its substrate.
12. A double layer buffer for matching and reducing strain between a crystalline film and its substrate.
13. A semiconductor device made according to a process comprising the method described in any one of claims 1 to 10.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A semiconductor device, comprising:
a user circuit having a plurality of flip-flops; and
a connection path which, while in test mode, connects the plurality of flip-flops and forms a scan chain, and while in user mode, disconnects the plurality of flip-flops and does not form the scan chain, wherein
the connection path has an XOR or XNOR operation circuit which performs an XOR or XNOR operation on a first output value and a prescribed value and outputs a second output value, the first output value being an output value of at least one of the plurality of flip-flops, the second output value being different from the first output value or being same as the first output value depending on the prescribed value, the XOR or XNOR operation circuit being included in the scan chain while in test mode, and
the first output value is restorable based on the prescribed value and a logic of the XOR or XNOR operation circuit.
2. The semiconductor device according to claim 1, wherein the connection path comprises a plurality of the XOR or XNOR operation circuits.
3. The semiconductor device according to claim 1, wherein the prescribed value is a pseudorandom value.
4. A semiconductor device, comprising:
a user circuit having a plurality of flip-flops which operate in synchronization with a first clock signal;
a connection path which, while in test mode, connects the plurality of flip-flops and forms a scan chain performing a shift operation in synchronization with the first clock signal, and while in user mode, disconnects the plurality of flip-flops and does not form the scan chain; and
a clock generation circuit which performs a logic operation on a prescribed value and the first clock signal and outputs a second clock signal, the second clock signal being different from the first clock signal or being same as the first clock signal depending on the prescribed value, wherein,
a first flip-flop among the plurality of flip-flops operates in synchronization with the second clock signal while in test mode, and operates in synchronization with the first clock signal while in user mode, and
while in test mode, the first flip-flop does not input an output value according to the second clock signal when the second clock signal is different from the first clock signal, the output value being output from a second flip-flop at the preceding stage of the first flip-flop according to the first clock signal.
5. The semiconductor device according to claim 4, wherein the logical operation of the clock generation circuit is any of an AND operation, an OR operation, an XOR operation, a NAND operation, a NOR operation, and an XNOR operation.
6. The semiconductor device according to claim 4, wherein the prescribed value is a pseudorandom value.
7. The semiconductor device according to claim 4, wherein the connection path comprises a logic operation circuit or an inverted value connection path, the logic operation circuit configured to perform a logic operation on a non-inverted output value of any flip-flop among the plurality of flip-flops and outputs the result, the inverted value connection path configured to output to a following-stage flip-flop an inverted output value of any flip-flop among the plurality of flip-flops.